arch/riscv/mpfs: Switch to use riscv_exception_common
Clean up mpfs port by using the common code Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen
Xiang Xiao
parent
7b8eec3fa4
commit
6428c1fdc4
@ -24,7 +24,7 @@ HEAD_ASRC = mpfs_head.S
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# Specify our general Assembly files
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CMN_ASRCS += riscv_vectors.S riscv_testset.S
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CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_testset.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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@ -34,8 +34,6 @@
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* Public Symbols
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****************************************************************************/
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.global exception_common
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/* Imported symbols */
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.extern __trap_vec
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@ -215,169 +213,3 @@ _fini:
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/* These don't have to do anything since we use init_array/fini_array. */
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ret
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/****************************************************************************
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* Name: exception_common
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****************************************************************************/
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exception_common:
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addi sp, sp, -XCPTCONTEXT_SIZE
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sd x1, 1*8(sp) /* ra */
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/* leave gp(x3) in 3*8(sp) untouched */
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sd x4, 4*8(sp) /* tp */
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sd x5, 5*8(sp) /* t0 */
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sd x6, 6*8(sp) /* t1 */
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sd x7, 7*8(sp) /* t2 */
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sd x8, 8*8(sp) /* s0 */
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sd x9, 9*8(sp) /* s1 */
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sd x10, 10*8(sp) /* a0 */
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sd x11, 11*8(sp) /* a1 */
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sd x12, 12*8(sp) /* a2 */
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sd x13, 13*8(sp) /* a3 */
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sd x14, 14*8(sp) /* a4 */
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sd x15, 15*8(sp) /* a5 */
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sd x16, 16*8(sp) /* a6 */
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sd x17, 17*8(sp) /* a7 */
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sd x18, 18*8(sp) /* s2 */
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sd x19, 19*8(sp) /* s3 */
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sd x20, 20*8(sp) /* s4 */
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sd x21, 21*8(sp) /* s5 */
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sd x22, 22*8(sp) /* s6 */
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sd x23, 23*8(sp) /* s7 */
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sd x24, 24*8(sp) /* s8 */
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sd x25, 25*8(sp) /* s9 */
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sd x26, 26*8(sp) /* s10 */
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sd x27, 27*8(sp) /* s11 */
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sd x28, 28*8(sp) /* t3 */
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sd x29, 29*8(sp) /* t4 */
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sd x30, 30*8(sp) /* t5 */
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sd x31, 31*8(sp) /* t6 */
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csrr s0, mstatus
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sd s0, 32*8(sp) /* mstatus */
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addi s0, sp, XCPTCONTEXT_SIZE
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sd s0, 2*8(sp) /* original SP */
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/* Setup arg0(exception cause), arg1(context) */
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csrr a0, mcause /* exception cause */
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csrr s0, mepc
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sd s0, 0(sp) /* exception PC */
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mv a1, sp /* context = sp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 15
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/* Load mhartid (cpuid) */
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csrr s0, mhartid
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/* Switch to interrupt stack
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*
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* If booting on all harts, there are 5 irq stacks reserved,
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* one for each hart.
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* Just calculate the correct one for this hart
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*
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* For a single-hart boot mode just set the sp
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*/
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#ifdef CONFIG_MPFS_BOOTLOADER
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li s1, ((CONFIG_ARCH_INTERRUPTSTACK) & ~15)
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mul s1, s0, s1
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la s0, g_intstacktop
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sub sp, s0, s1
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#else
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la sp, g_intstacktop
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#endif /* CONFIG_MPFS_BOOTLOADER */
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#endif
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/* Call interrupt handler in C */
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jal x1, mpfs_dispatch_irq
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/* If context switch is needed, return a new sp */
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mv sp, a0
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ld s0, 0(sp) /* restore mepc */
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csrw mepc, s0
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ld s0, 32*8(sp) /* restore mstatus */
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csrw mstatus, s0
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/* leave gp(x3) in 3*8(sp) untouched */
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ld x4, 4*8(sp) /* tp */
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ld x5, 5*8(sp) /* t0 */
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ld x6, 6*8(sp) /* t1 */
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ld x7, 7*8(sp) /* t2 */
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ld x8, 8*8(sp) /* s0 */
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ld x9, 9*8(sp) /* s1 */
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ld x10, 10*8(sp) /* a0 */
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ld x11, 11*8(sp) /* a1 */
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ld x12, 12*8(sp) /* a2 */
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ld x13, 13*8(sp) /* a3 */
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ld x14, 14*8(sp) /* a4 */
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ld x15, 15*8(sp) /* a5 */
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ld x16, 16*8(sp) /* a6 */
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ld x17, 17*8(sp) /* a7 */
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ld x18, 18*8(sp) /* s2 */
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ld x19, 19*8(sp) /* s3 */
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ld x20, 20*8(sp) /* s4 */
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ld x21, 21*8(sp) /* s5 */
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ld x22, 22*8(sp) /* s6 */
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ld x23, 23*8(sp) /* s7 */
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ld x24, 24*8(sp) /* s8 */
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ld x25, 25*8(sp) /* s9 */
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ld x26, 26*8(sp) /* s10 */
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ld x27, 27*8(sp) /* s11 */
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ld x28, 28*8(sp) /* t3 */
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ld x29, 29*8(sp) /* t4 */
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ld x30, 30*8(sp) /* t5 */
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ld x31, 31*8(sp) /* t6 */
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ld x1, 1*8(sp) /* ra */
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ld sp, 2*8(sp) /* restore original sp */
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/* Return from Machine Interrupt */
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mret
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/************************************************************************************
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* Name: g_intstackalloc and g_intstackbase
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************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 15
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.bss
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.balign 16
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.global g_intstackalloc
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.global g_intstacktop
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.type g_intstackalloc, object
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.type g_intstacktop, object
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#ifdef CONFIG_MPFS_BOOTLOADER
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/* If booting on all harts, reserve an own interruptstack for every hart */
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g_intstackalloc:
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.skip (((CONFIG_ARCH_INTERRUPTSTACK * 5) + 8) & ~15)
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g_intstacktop:
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.size g_intstacktop, 0
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.size g_intstackalloc, ((CONFIG_ARCH_INTERRUPTSTACK * 5) & ~15)
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#else
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g_intstackalloc:
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.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
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g_intstacktop:
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.size g_intstacktop, 0
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.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
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#endif /* CONFIG_MPFS_BOOTLOADER */
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#endif
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@ -50,10 +50,10 @@ extern void up_fault(int irq, uint64_t *regs);
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****************************************************************************/
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/****************************************************************************
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* mpfs_dispatch_irq
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* riscv_dispatch_irq
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****************************************************************************/
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void *mpfs_dispatch_irq(uint64_t vector, uint64_t *regs)
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void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
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{
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uint32_t irq = (vector & 0x3f);
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uint64_t *mepc = regs;
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