arch/riscv/mpfs: Switch to use riscv_exception_common

Clean up mpfs port by using the common code

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

arch/risc-v/src/mpfs/Make.defs

@@ -24,7 +24,7 @@ HEAD_ASRC = mpfs_head.S
 
 # Specify our general Assembly files
 
-CMN_ASRCS += riscv_vectors.S riscv_testset.S
+CMN_ASRCS += riscv_vectors.S riscv_exception_common.S riscv_testset.S
 
 # Specify C code within the common directory to be included
 CMN_CSRCS += riscv_initialize.c riscv_swint.c

arch/risc-v/src/mpfs/mpfs_head.S

@@ -34,8 +34,6 @@
  * Public Symbols
  ****************************************************************************/
 
-  .global exception_common
-
   /* Imported symbols */
 
   .extern __trap_vec
@@ -215,169 +213,3 @@ _fini:
   /* These don't have to do anything since we use init_array/fini_array. */
 
   ret
-
-/****************************************************************************
- * Name: exception_common
- ****************************************************************************/
-
-exception_common:
-
-  addi sp, sp, -XCPTCONTEXT_SIZE
-
-  sd   x1,  1*8(sp)   /* ra */
-
-  /* leave gp(x3) in 3*8(sp) untouched */
-
-  sd   x4,  4*8(sp)   /* tp */
-  sd   x5,  5*8(sp)   /* t0 */
-  sd   x6,  6*8(sp)   /* t1 */
-  sd   x7,  7*8(sp)   /* t2 */
-  sd   x8,  8*8(sp)   /* s0 */
-  sd   x9,  9*8(sp)   /* s1 */
-  sd   x10, 10*8(sp)  /* a0 */
-  sd   x11, 11*8(sp)  /* a1 */
-  sd   x12, 12*8(sp)  /* a2 */
-  sd   x13, 13*8(sp)  /* a3 */
-  sd   x14, 14*8(sp)  /* a4 */
-  sd   x15, 15*8(sp)  /* a5 */
-  sd   x16, 16*8(sp)  /* a6 */
-  sd   x17, 17*8(sp)  /* a7 */
-  sd   x18, 18*8(sp)  /* s2 */
-  sd   x19, 19*8(sp)  /* s3 */
-  sd   x20, 20*8(sp)  /* s4 */
-  sd   x21, 21*8(sp)  /* s5 */
-  sd   x22, 22*8(sp)  /* s6 */
-  sd   x23, 23*8(sp)  /* s7 */
-  sd   x24, 24*8(sp)  /* s8 */
-  sd   x25, 25*8(sp)  /* s9 */
-  sd   x26, 26*8(sp)  /* s10 */
-  sd   x27, 27*8(sp)  /* s11 */
-  sd   x28, 28*8(sp)  /* t3 */
-  sd   x29, 29*8(sp)  /* t4 */
-  sd   x30, 30*8(sp)  /* t5 */
-  sd   x31, 31*8(sp)  /* t6 */
-
-  csrr s0, mstatus
-  sd   s0,  32*8(sp)  /* mstatus */
-
-  addi s0, sp, XCPTCONTEXT_SIZE
-  sd   s0,  2*8(sp)   /* original SP */
-
-  /* Setup arg0(exception cause), arg1(context) */
-
-  csrr a0, mcause  /* exception cause */
-  csrr s0, mepc
-  sd   s0, 0(sp)   /* exception PC */
-
-  mv   a1, sp      /* context = sp */
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 15
-  /* Load mhartid (cpuid) */
-
-  csrr s0, mhartid
-
-  /* Switch to interrupt stack
-   *
-   * If booting on all harts, there are 5 irq stacks reserved,
-   * one for each hart.
-   * Just calculate the correct one for this hart
-   *
-   * For a single-hart boot mode just set the sp
-   */
-
-#ifdef CONFIG_MPFS_BOOTLOADER
-  li s1, ((CONFIG_ARCH_INTERRUPTSTACK) & ~15)
-  mul s1, s0, s1
-  la s0, g_intstacktop
-  sub sp, s0, s1
-#else
-  la sp, g_intstacktop
-#endif /* CONFIG_MPFS_BOOTLOADER */
-
-#endif
-
-  /* Call interrupt handler in C */
-
-  jal  x1, mpfs_dispatch_irq
-
-  /* If context switch is needed, return a new sp */
-
-  mv   sp, a0
-  ld   s0, 0(sp)    /* restore mepc */
-  csrw mepc, s0
-
-  ld   s0, 32*8(sp) /* restore mstatus */
-  csrw mstatus, s0
-
-  /* leave gp(x3) in 3*8(sp) untouched */
-
-  ld  x4,  4*8(sp)  /* tp */
-  ld  x5,  5*8(sp)  /* t0 */
-  ld  x6,  6*8(sp)  /* t1 */
-  ld  x7,  7*8(sp)  /* t2 */
-  ld  x8,  8*8(sp)  /* s0 */
-  ld  x9,  9*8(sp)  /* s1 */
-  ld x10, 10*8(sp)  /* a0 */
-  ld x11, 11*8(sp)  /* a1 */
-  ld x12, 12*8(sp)  /* a2 */
-  ld x13, 13*8(sp)  /* a3 */
-  ld x14, 14*8(sp)  /* a4 */
-  ld x15, 15*8(sp)  /* a5 */
-  ld x16, 16*8(sp)  /* a6 */
-  ld x17, 17*8(sp)  /* a7 */
-  ld x18, 18*8(sp)  /* s2 */
-  ld x19, 19*8(sp)  /* s3 */
-  ld x20, 20*8(sp)  /* s4 */
-  ld x21, 21*8(sp)  /* s5 */
-  ld x22, 22*8(sp)  /* s6 */
-  ld x23, 23*8(sp)  /* s7 */
-  ld x24, 24*8(sp)  /* s8 */
-  ld x25, 25*8(sp)  /* s9 */
-  ld x26, 26*8(sp)  /* s10 */
-  ld x27, 27*8(sp)  /* s11 */
-  ld x28, 28*8(sp)  /* t3 */
-  ld x29, 29*8(sp)  /* t4 */
-  ld x30, 30*8(sp)  /* t5 */
-  ld x31, 31*8(sp)  /* t6 */
-
-  ld  x1,  1*8(sp)  /* ra */
-
-  ld  sp,  2*8(sp)  /* restore original sp */
-
-  /* Return from Machine Interrupt */
-
-  mret
-
-/************************************************************************************
- *  Name: g_intstackalloc and g_intstackbase
- ************************************************************************************/
-
-#if CONFIG_ARCH_INTERRUPTSTACK > 15
-  .bss
-  .balign 16
-  .global g_intstackalloc
-  .global g_intstacktop
-  .type   g_intstackalloc, object
-  .type   g_intstacktop, object
-
-#ifdef CONFIG_MPFS_BOOTLOADER
-
-/* If booting on all harts, reserve an own interruptstack for every hart */
-
-g_intstackalloc:
-  .skip  (((CONFIG_ARCH_INTERRUPTSTACK * 5) + 8) & ~15)
-g_intstacktop:
-  .size  g_intstacktop, 0
-  .size  g_intstackalloc, ((CONFIG_ARCH_INTERRUPTSTACK * 5) & ~15)
-
-#else
-
-g_intstackalloc:
-  .skip  ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
-g_intstacktop:
-  .size  g_intstacktop, 0
-  .size  g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
-
-#endif /* CONFIG_MPFS_BOOTLOADER */
-
-#endif

arch/risc-v/src/mpfs/mpfs_irq_dispatch.c

@@ -50,10 +50,10 @@ extern void up_fault(int irq, uint64_t *regs);
  ****************************************************************************/
 
 /****************************************************************************
- * mpfs_dispatch_irq
+ * riscv_dispatch_irq
  ****************************************************************************/
 
-void *mpfs_dispatch_irq(uint64_t vector, uint64_t *regs)
+void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
 {
   uint32_t irq = (vector & 0x3f);
   uint64_t *mepc = regs;