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armv7-a/r:cache: implemention clean&flush_dcache_all

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For armv7-a/r cache:
And clean_dcache_all, flush_dcache_all

Signed-off-by: zhuyanlin <zhuyanlin1@xiaomi.com>
This commit is contained in:
zhuyanlin 2022-01-21 11:46:09 +08:00 committed by Xiang Xiao
parent 1b08f607be
commit 644c2be3aa
13 changed files with 667 additions and 0 deletions
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1
arch/arm/src/a1x/Make.defs
View File

@ -46,6 +46,7 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S
# Common C source files

1
arch/arm/src/am335x/Make.defs
View File

@ -46,6 +46,7 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_testset.S vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S
# Common C source files

57
arch/arm/src/armv7-a/arm_cache.c
View File

@ -138,6 +138,35 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
l2cc_clean(start, end);
}
/****************************************************************************
* Name: up_clean_dcache_all
*
* Description:
* Clean the entire data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* NOTE: This operation is un-necessary if the DCACHE is configured in
* write-through mode.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void up_clean_dcache_all(void)
{
cp15_clean_dcache_all();
l2cc_clean_all();
}
/****************************************************************************
* Name: up_flush_dcache
*
@ -165,6 +194,34 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
l2cc_flush(start, end);
}
/****************************************************************************
* Name: up_flush_dcache_all
*
* Description:
* Flush the entire data cache by cleaning and invalidating the D cache.
*
* NOTE: If DCACHE write-through is configured, then this operation is the
* same as up_invalidate_cache_all().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void up_flush_dcache_all(void)
{
cp15_flush_dcache_all();
l2cc_flush_all();
}
/****************************************************************************
* Name: up_enable_icache
*

32
arch/arm/src/armv7-a/cp15_cacheops.h
View File

@ -1066,6 +1066,22 @@ void cp15_invalidate_dcache_all(void);
void cp15_clean_dcache(uintptr_t start, uintptr_t end);
/****************************************************************************
* Name: cp15_clean_dcache_all
*
* Description:
* Clean the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void cp15_clean_dcache_all(void);
/****************************************************************************
* Name: cp15_flush_dcache
*
@ -1084,6 +1100,22 @@ void cp15_clean_dcache(uintptr_t start, uintptr_t end);
void cp15_flush_dcache(uintptr_t start, uintptr_t end);
/****************************************************************************
* Name: cp15_flush_dcache_all
*
* Description:
* Flush the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void cp15_flush_dcache_all(void);
#undef EXTERN
#ifdef __cplusplus
}

121
arch/arm/src/armv7-a/cp15_clean_dcache_all.S Normal file
View File

@ -0,0 +1,121 @@
/****************************************************************************
* arch/arm/src/armv7-a/cp15_flush_dcache_all.S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Portions of this file derive from Atmel sample code for the SAMA5D3
* Cortex-A5 which also has a modified BSD-style license:
*
* Copyright (c) 2012, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
*
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
* DDI 0406C.b (ID072512)
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "cp15.h"
.file "cp15_flush_dcache_all.S"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl cp15_flush_dcache_all
/****************************************************************************
* Public Functions
****************************************************************************/
.text
/****************************************************************************
* Name: cp15_flush_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
.globl cp15_flush_dcache_all
.type cp15_flush_dcache_all, function
cp15_flush_dcache_all:
mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
and r0, r3, r0, lsr #13 /* r0=NumSets (number of sets - 1) */
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
add r4, r3, r0, lsr #3 /* r4=(number of ways - 1) */
mov r1, #0 /* r1 = way loop counter */
way_loop:
mov r3, #0 /* r3 = set loop counter */
set_loop:
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
mcr CP15_DCCISW(r2) /* Data Cache Invalidate by Set/Way */
add r3, r3, #1 /* Increment set counter */
cmp r0, r3 /* Last set? */
bne set_loop /* Keep looping if not */
add r1, r1, #1 /* Increment the way counter */
cmp r4, r1 /* Last way */
bne way_loop /* Keep looping if not */
dsb
bx lr
.size cp15_flush_dcache_all, . - cp15_flush_dcache_all
.end

121
arch/arm/src/armv7-a/cp15_flush_dcache_all.S Normal file
View File

@ -0,0 +1,121 @@
/****************************************************************************
* arch/arm/src/armv7-a/cp15_clean_dcache_all.S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Portions of this file derive from Atmel sample code for the SAMA5D3
* Cortex-A5 which also has a modified BSD-style license:
*
* Copyright (c) 2012, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
*
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
* DDI 0406C.b (ID072512)
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "cp15.h"
.file "cp15_clean_dcache_all.S"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl cp15_clean_dcache_all
/****************************************************************************
* Public Functions
****************************************************************************/
.text
/****************************************************************************
* Name: cp15_clean_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
.globl cp15_clean_dcache_all
.type cp15_clean_dcache_all, function
cp15_clean_dcache_all:
mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
and r0, r3, r0, lsr #13 /* r0=NumSets (number of sets - 1) */
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
add r4, r3, r0, lsr #3 /* r4=(number of ways - 1) */
mov r1, #0 /* r1 = way loop counter */
way_loop:
mov r3, #0 /* r3 = set loop counter */
set_loop:
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
mcr CP15_DCCSW(r2) /* Data Cache Invalidate by Set/Way */
add r3, r3, #1 /* Increment set counter */
cmp r0, r3 /* Last set? */
bne set_loop /* Keep looping if not */
add r1, r1, #1 /* Increment the way counter */
cmp r4, r1 /* Last way */
bne way_loop /* Keep looping if not */
dsb
bx lr
.size cp15_clean_dcache_all, . - cp15_clean_dcache_all
.end

57
arch/arm/src/armv7-r/arm_cache.c
View File

@ -138,6 +138,35 @@ void up_clean_dcache(uintptr_t start, uintptr_t end)
l2cc_clean(start, end);
}
/****************************************************************************
* Name: up_clean_dcache_all
*
* Description:
* Clean the entire data cache within the specified region by flushing the
* contents of the data cache to memory.
*
* NOTE: This operation is un-necessary if the DCACHE is configured in
* write-through mode.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void up_clean_dcache_all(void)
{
cp15_clean_dcache_all();
l2cc_clean_all();
}
/****************************************************************************
* Name: up_flush_dcache
*
@ -165,6 +194,34 @@ void up_flush_dcache(uintptr_t start, uintptr_t end)
l2cc_flush(start, end);
}
/****************************************************************************
* Name: up_flush_dcache_all
*
* Description:
* Flush the entire data cache by cleaning and invalidating the D cache.
*
* NOTE: If DCACHE write-through is configured, then this operation is the
* same as up_invalidate_cache_all().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
* Assumptions:
* This operation is not atomic. This function assumes that the caller
* has exclusive access to the address range so that no harm is done if
* the operation is pre-empted.
*
****************************************************************************/
void up_flush_dcache_all(void)
{
cp15_flush_dcache_all();
l2cc_flush_all();
}
/****************************************************************************
* Name: up_enable_icache
*

32
arch/arm/src/armv7-r/cp15_cacheops.h
View File

@ -1073,6 +1073,22 @@ void cp15_invalidate_dcache_all(void);
void cp15_clean_dcache(uintptr_t start, uintptr_t end);
/****************************************************************************
* Name: cp15_clean_dcache_all
*
* Description:
* Clean the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void cp15_clean_dcache_all(void);
/****************************************************************************
* Name: cp15_flush_dcache
*
@ -1091,6 +1107,22 @@ void cp15_clean_dcache(uintptr_t start, uintptr_t end);
void cp15_flush_dcache(uintptr_t start, uintptr_t end);
/****************************************************************************
* Name: cp15_flush_dcache_all
*
* Description:
* Flush the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void cp15_flush_dcache_all(void);
#undef EXTERN
#ifdef __cplusplus
}

121
arch/arm/src/armv7-r/cp15_clean_dcache_all.S Normal file
View File

@ -0,0 +1,121 @@
/****************************************************************************
* arch/arm/src/armv7-r/cp15_flush_dcache_all.S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Portions of this file derive from Atmel sample code for the SAMA5D3
* Cortex-A5 which also has a modified BSD-style license:
*
* Copyright (c) 2012, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
*
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
* DDI 0406C.b (ID072512)
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "cp15.h"
.file "cp15_flush_dcache_all.S"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl cp15_flush_dcache_all
/****************************************************************************
* Public Functions
****************************************************************************/
.text
/****************************************************************************
* Name: cp15_flush_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
.globl cp15_flush_dcache_all
.type cp15_flush_dcache_all, function
cp15_flush_dcache_all:
mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
and r0, r3, r0, lsr #13 /* r0=NumSets (number of sets - 1) */
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
add r4, r3, r0, lsr #3 /* r4=(number of ways - 1) */
mov r1, #0 /* r1 = way loop counter */
way_loop:
mov r3, #0 /* r3 = set loop counter */
set_loop:
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
mcr CP15_DCCISW(r2) /* Data Cache Invalidate by Set/Way */
add r3, r3, #1 /* Increment set counter */
cmp r0, r3 /* Last set? */
bne set_loop /* Keep looping if not */
add r1, r1, #1 /* Increment the way counter */
cmp r4, r1 /* Last way */
bne way_loop /* Keep looping if not */
dsb
bx lr
.size cp15_flush_dcache_all, . - cp15_flush_dcache_all
.end

121
arch/arm/src/armv7-r/cp15_flush_dcache_all.S Normal file
View File

@ -0,0 +1,121 @@
/****************************************************************************
* arch/arm/src/armv7-r/cp15_clean_dcache_all.S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Portions of this file derive from Atmel sample code for the SAMA5D3
* Cortex-A5 which also has a modified BSD-style license:
*
* Copyright (c) 2012, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor Atmel nor the names of the contributors may
* be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* References:
*
* "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
* Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
* "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
* Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
* DDI 0406C.b (ID072512)
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include "cp15.h"
.file "cp15_clean_dcache_all.S"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.globl cp15_clean_dcache_all
/****************************************************************************
* Public Functions
****************************************************************************/
.text
/****************************************************************************
* Name: cp15_clean_dcache_all
*
* Description:
* Invalidate the entire contents of D cache.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
.globl cp15_clean_dcache_all
.type cp15_clean_dcache_all, function
cp15_clean_dcache_all:
mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
and r0, r3, r0, lsr #13 /* r0=NumSets (number of sets - 1) */
ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
add r4, r3, r0, lsr #3 /* r4=(number of ways - 1) */
mov r1, #0 /* r1 = way loop counter */
way_loop:
mov r3, #0 /* r3 = set loop counter */
set_loop:
mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
mcr CP15_DCCSW(r2) /* Data Cache Invalidate by Set/Way */
add r3, r3, #1 /* Increment set counter */
cmp r0, r3 /* Last set? */
bne set_loop /* Keep looping if not */
add r1, r1, #1 /* Increment the way counter */
cmp r4, r1 /* Last way */
bne way_loop /* Keep looping if not */
dsb
bx lr
.size cp15_clean_dcache_all, . - cp15_clean_dcache_all
.end

1
arch/arm/src/imx6/Make.defs
View File

@ -49,6 +49,7 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S
# Common C source files

1
arch/arm/src/sama5/Make.defs
View File

@ -46,6 +46,7 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S
# Configuration dependent assembly language files

1
arch/arm/src/tms570/Make.defs
View File

@ -30,6 +30,7 @@ CMN_ASRCS += arm_saveusercontext.S arm_vectoraddrexcptn.S
CMN_ASRCS += arm_testset.S arm_fetchadd.S vfork.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S
CMN_ASRCS += cp15_clean_dcache_all.S cp15_flush_dcache_all.S
CMN_ASRCS += cp15_invalidate_dcache_all.S
# Configuration dependent assembly language files