Finishes LPC43xx uart bard configuration; LPC43 is ready to begin testing
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4918 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -319,7 +319,7 @@
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#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
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#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
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#define UART_FDR_MULVAL_SHIFT (3) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
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#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
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#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
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/* Bits 8-31: Reserved */
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/* Oversampling Register (USART only) */
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@ -73,28 +73,21 @@
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#if defined(USE_SERIALDRIVER) && defined(HAVE_UART)
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/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
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* much accuracy. This following is a "fudge factor" that represents the minimum
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* value of the divisor that we will permit.
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*/
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#define UART_MINDL 32
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/****************************************************************************
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* Private Types
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****************************************************************************/
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struct up_dev_s
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{
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uint32_t uartbase; /* Base address of UART registers */
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uint8_t basefreq; /* Base frequency of input clock */
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uint32_t baud; /* Configured baud */
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uint32_t ier; /* Saved IER value */
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uint8_t id; /* ID=0,1,2,3 */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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uintptr_t uartbase; /* Base address of UART registers */
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uint32_t basefreq; /* Base frequency of input clock */
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uint32_t baud; /* Configured baud */
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uint32_t ier; /* Saved IER value */
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uint8_t id; /* ID=0,1,2,3 */
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uint8_t irq; /* IRQ associated with this UART */
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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};
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/****************************************************************************
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@ -483,9 +476,9 @@ static uart_dev_t g_uart3port =
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# endif
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#endif /*HAVE_CONSOLE*/
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/************************************************************************************
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/****************************************************************************
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* Inline Functions
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************************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Name: up_serialin
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@ -548,29 +541,135 @@ static inline void up_enablebreaks(struct up_dev_s *priv, bool enable)
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr);
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}
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/************************************************************************************
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* Name: lpc43_uartdl
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*
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* Descrption:
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* Select a divider to produce the BAUD from the UART BASEFREQ.
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*
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* BAUD = BASEFREQ / (16 * DL), or
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* DL = BASEFREQ / BAUD / 16
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*
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* Ignoring the fractional divider for now.
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*
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************************************************************************************/
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static inline uint32_t lpc43_uartdl(uint32_t baud)
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{
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#warning "Missing logic"
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return 0;
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}
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_setbaud
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*
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* Description:
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* Configure the U[S]ART divisors to accomplish the desired BAUD given the
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* U[S]ART base frequency.
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*
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****************************************************************************/
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void up_setbaud(struct up_dev_s *priv)
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{
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uint32_t lcr; /* Line control register value */
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uint32_t dl; /* Best DLM/DLL full value */
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uint32_t mul; /* Best FDR MULVALL value */
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uint32_t divadd; /* Best FDR DIVADDVAL value */
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uint32_t best; /* Error value associated with best {dl, mul, divadd} */
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uint32_t cdl; /* Candidate DLM/DLL full value */
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uint32_t cmul; /* Candidate FDR MULVALL value */
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uint32_t cdivadd; /* Candidate FDR DIVADDVAL value */
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uint32_t errval; /* Error value associated with the candidate */
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/* The U[S]ART buad is given by:
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*
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* Fbaud = Fbase * mul / (mul + divadd) / (16 * dl)
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* dl = Fbase * mul / (mul + divadd) / Fbaud / 16
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* = Fbase * mul / ((mul + divadd) * Fbaud * 16)
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* = ((Fbase * mul) >> 4) / ((mul + divadd) * Fbaud)
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*
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* Where the value of MULVAL and DIVADDVAL comply with:
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*
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* 0 < mul < 16
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* 0 <= divadd < mul
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*/
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best = UINT32_MAX;
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divadd = 0;
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mul = 0;
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dl = 0;
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/* Try each mulitplier value in the valid range */
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for (cmul = 1 ; cmul < 16; cmul++)
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{
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/* Try each divider value in the valid range */
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for (cdivadd = 0 ; cdivadd < cmul ; cdivadd++)
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{
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/* Candidate:
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* dl = ((Fbase * mul) >> 4) / ((mul + cdivadd) * Fbaud)
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* (dl << 32) = (Fbase << 28) * cmul / ((mul + cdivadd) * Fbaud)
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*/
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uint64_t dl64 = ((uint64_t)priv->basefreq << 28) * cmul /
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((cmul + cdivadd) * priv->baud);
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/* The lower 32-bits of this value is the error */
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errval = (uint32_t)(dl64 & 0x00000000ffffffffull);
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/* The upper 32-bits is the candidate DL value */
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cdl = (uint32_t)(dl64 >> 32);
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/* Round up */
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if (errval > (1 << 31))
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{
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errval = -errval;
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cdl++;
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}
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/* Check if the resulting candidate DL value is within range */
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if (cdl < 1 || cdl > 65536)
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{
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/* No... try a different divadd value */
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continue;
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}
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/* Is this the best combination that we have seen so far? */
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if (errval < best)
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{
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/* Yes.. then the candidate is out best guess so far */
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best = errval;
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dl = cdl;
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divadd = cdivadd;
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mul = cmul;
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/* If the new best guess is exact (within our precision), then
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* we are finished.
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*/
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if (best == 0)
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{
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break;
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}
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}
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}
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}
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DEBUGASSERT(dl > 0);
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/* Enter DLAB=1 */
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lcr = up_serialin(priv, LPC43_UART_LCR_OFFSET);
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr | UART_LCR_DLAB);
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/* Save then divider values */
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up_serialout(priv, LPC43_UART_DLM_OFFSET, dl >> 8);
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up_serialout(priv, LPC43_UART_DLL_OFFSET, dl & 0xff);
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/* Clear DLAB */
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr & ~UART_LCR_DLAB);
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/* Then save the fractional divider values */
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up_serialout(priv, LPC43_UART_FDR_OFFSET,
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(mul << UART_FDR_MULVAL_SHIFT) | (divadd << UART_FDR_DIVADDVAL_SHIFT));
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}
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/****************************************************************************
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* Name: up_setup
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*
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@ -584,7 +683,6 @@ static int up_setup(struct uart_dev_s *dev)
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{
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#ifndef CONFIG_SUPPRESS_LPC43_UART_CONFIG
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struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
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uint16_t dl;
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uint32_t lcr;
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/* Clear fifos */
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@ -626,19 +724,13 @@ static int up_setup(struct uart_dev_s *dev)
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lcr |= (UART_LCR_PE|UART_LCR_PS_EVEN);
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}
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/* Enter DLAB=1 */
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/* Save the LCR */
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up_serialout(priv, LPC43_UART_LCR_OFFSET, (lcr | UART_LCR_DLAB));
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr);
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/* Set the BAUD divisor */
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dl = lpc43_uartdl(priv->baud);
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up_serialout(priv, LPC43_UART_DLM_OFFSET, dl >> 8);
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up_serialout(priv, LPC43_UART_DLL_OFFSET, dl & 0xff);
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/* Clear DLAB */
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up_serialout(priv, LPC43_UART_LCR_OFFSET, lcr);
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up_setbaud(priv);
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/* Configure the FIFOs */
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@ -648,7 +740,7 @@ static int up_setup(struct uart_dev_s *dev)
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/* Enable Auto-RTS and Auto-CS Flow Control in the Modem Control Register */
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#ifdef CONFIG_UART1_FLOWCONTROL
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if (priv->uartbase == LPC43_UART1_BASE)
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if (priv->id == 1)
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{
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up_serialout(priv, LPC43_UART_MCR_OFFSET, (UART_MCR_RTSEN|UART_MCR_CTSEN));
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}
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@ -155,9 +155,10 @@
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*
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* BASEFREQ = CCLK / divisor
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*
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* Ignoring the fractional divider for now.
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* Ignoring the fractional divider for now (the console UART will be reconfigured
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* later in the boot sequencye, then the fractional dividers will be set properly).
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*
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* Check divisor == 1. This works if the upper limit is met
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* Check divisor == 1. This works if the upper limit is met
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*
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* DL < 0xffff, or
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* BASEFREQ / BAUD / 16 < 0xffff, or
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@ -527,5 +528,3 @@ void lpc43_usart3_setup(void)
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irqrestore(flags);
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};
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#endif
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