arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/stm32l15xxx_rcc.c:
* Fix nxstyle errors.
This commit is contained in:
Nathan Hartman
Abdelatif Guettouche
parent
8ac184633b
commit
648ec7bee4
@ -78,24 +78,26 @@ static inline void rcc_reset(void)
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/* Make sure that all devices are out of reset */
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putreg32(0, STM32_RCC_AHBRSTR); /* Disable AHB Peripheral Reset */
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putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
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putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
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putreg32(0, STM32_RCC_AHBRSTR); /* Disable AHB Peripheral Reset */
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putreg32(0, STM32_RCC_APB2RSTR); /* Disable APB2 Peripheral Reset */
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putreg32(0, STM32_RCC_APB1RSTR); /* Disable APB1 Peripheral Reset */
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/* Disable all clocking (other than to FLASH) */
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putreg32(RCC_AHBENR_FLITFEN, STM32_RCC_AHBENR); /* FLITF Clock ON */
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putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
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putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
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putreg32(0, STM32_RCC_APB2ENR); /* Disable APB2 Peripheral Clock */
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putreg32(0, STM32_RCC_APB1ENR); /* Disable APB1 Peripheral Clock */
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/* Set the Internal clock sources calibration register to its reset value.
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* MSI to the default frequency (nominally 2.097MHz), MSITRIM=0, HSITRIM=0x10.
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* Preserve the factory HSICAL and MSICAL settings.
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* MSI to the default frequency (nominally 2.097MHz), MSITRIM=0,
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* HSITRIM=0x10. Preserve the factory HSICAL and MSICAL settings.
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*/
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regval = getreg32(STM32_RCC_ICSCR);
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regval &= (RCC_ICSCR_HSICAL_MASK | RCC_ICSCR_MSICAL_MASK);
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regval |= (RCC_ICSR_RSTVAL & ~(RCC_ICSCR_HSICAL_MASK | RCC_ICSCR_MSICAL_MASK));
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regval |= (RCC_ICSR_RSTVAL &
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~(RCC_ICSCR_HSICAL_MASK | RCC_ICSCR_MSICAL_MASK));
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putreg32(regval, STM32_RCC_ICSCR);
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/* Enable the internal MSI */
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@ -112,19 +114,24 @@ static inline void rcc_reset(void)
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
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RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCOSEL_MASK | RCC_CFGR_MCOPRE_MASK);
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RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCOSEL_MASK |
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RCC_CFGR_MCOPRE_MASK);
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putreg32(regval, STM32_RCC_CFGR);
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/* Make sure that the selected MSI source is used as the system clock source */
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/* Make sure that the selected MSI source is used as the system clock
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* source
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*/
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI);
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/* Now we can disable the alternative clock sources: HSE, HSI, PLL, CSS and RTCPRE. Also,
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* reset the HSE bypass. This restores the RCC CR to its reset state.
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/* Now we can disable the alternative clock sources: HSE, HSI, PLL, CSS and
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* RTCPRE. Also, reset the HSE bypass. This restores the RCC CR to its
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* reset state.
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*/
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regval = getreg32(STM32_RCC_CR); /* Disable the HSE and the PLL */
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regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_RTCPRE_MASK);
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regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_PLLON | RCC_CR_CSSON |
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RCC_CR_RTCPRE_MASK);
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putreg32(regval, STM32_RCC_CR);
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regval = getreg32(STM32_RCC_CR); /* Reset HSEBYP bit */
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@ -155,7 +162,9 @@ static inline void rcc_reset(void)
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regval &= ~FLASH_ACR_LATENCY; /* No wait states */
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putreg32(regval, STM32_FLASH_ACR);
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/* Check that the new number of WS is taken into account by reading FLASH_ACR */
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/* Check that the new number of WS is taken into account by reading
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* FLASH_ACR
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*/
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/* Program the 32-bit access by clearing ACC64 in FLASH_ACR */
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@ -184,8 +193,9 @@ static inline void rcc_enableahb(void)
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/* Enable GPIOA-E, H, F-G (not all parts have all ports) */
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regval |= (RCC_AHBENR_GPIOPAEN | RCC_AHBENR_GPIOPBEN | RCC_AHBENR_GPIOPCEN |
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RCC_AHBENR_GPIOPDEN | RCC_AHBENR_GPIOPEEN | RCC_AHBENR_GPIOPHEN |
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regval |= (RCC_AHBENR_GPIOPAEN | RCC_AHBENR_GPIOPBEN |
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RCC_AHBENR_GPIOPCEN | RCC_AHBENR_GPIOPDEN |
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RCC_AHBENR_GPIOPEEN | RCC_AHBENR_GPIOPHEN |
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RCC_AHBENR_GPIOPFEN | RCC_AHBENR_GPIOPGEN);
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#ifdef CONFIG_STM32_CRC
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@ -538,7 +548,8 @@ static void stm32_stdclockconfig(void)
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putreg32(regval, STM32_RCC_APB1ENR);
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/* Go to the high performance voltage range 1 if necessary. In this mode,
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* the PLL VCO frequency can be up to 96MHz. USB and SDIO can be supported.
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* the PLL VCO frequency can be up to 96MHz. USB and SDIO can be
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* supported.
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*
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* Range 1: PLLVCO up to 96MHz in range 1 (1.8V)
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* Range 2: PLLVCO up to 48MHz in range 2 (1.5V) (default)
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@ -654,25 +665,26 @@ static void stm32_stdclockconfig(void)
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/* Increasing the CPU frequency (in the same voltage range):
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*
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* After reset, the used clock is the MSI (2 MHz) with 0 WS configured in the
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* FLASH_ACR register. 32-bit access is enabled and prefetch is disabled.
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* ST strongly recommends to use the following software sequences to tune the
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* number of wait states needed to access the Flash memory with the CPU
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* frequency.
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* After reset, the used clock is the MSI (2 MHz) with 0 WS configured in
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* the FLASH_ACR register. 32-bit access is enabled and prefetch is
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* disabled. ST strongly recommends to use the following software
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* sequences to tune the number of wait states needed to access the Flash
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* memory with the CPU frequency.
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*
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* - Program the 64-bit access by setting the ACC64 bit in Flash access
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* control register (FLASH_ACR)
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* - Check that 64-bit access is taken into account by reading FLASH_ACR
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* - Program 1 WS to the LATENCY bit in FLASH_ACR
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* - Check that the new number of WS is taken into account by reading FLASH_ACR
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* - Check that the new number of WS is taken into account by reading
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* FLASH_ACR
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* - Modify the CPU clock source by writing to the SW bits in the Clock
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* configuration register (RCC_CFGR)
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* - If needed, modify the CPU clock prescaler by writing to the HPRE bits in
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* RCC_CFGR
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* - Check that the new CPU clock source or/and the new CPU clock prescaler
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* value is/are taken into account by reading the clock source status (SWS
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* bits) or/and the AHB prescaler value (HPRE bits), respectively, in the
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* RCC_CFGR register
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* - If needed, modify the CPU clock prescaler by writing to the HPRE
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* bits in RCC_CFGR
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* - Check that the new CPU clock source or/and the new CPU clock
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* prescaler value is/are taken into account by reading the clock
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* source status (SWS bits) or/and the AHB prescaler value (HPRE
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* bits), respectively, in the RCC_CFGR register
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*/
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regval = getreg32(STM32_FLASH_ACR);
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@ -723,8 +735,8 @@ static void stm32_stdclockconfig(void)
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#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
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/* Set the PLL divider and multiplier. NOTE: The PLL needs to be disabled
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* to do these operation. We know this is the case here because pll_reset()
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* was previously called by stm32_clockconfig().
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* to do these operation. We know this is the case here because
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* pll_reset() was previously called by stm32_clockconfig().
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*/
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regval = getreg32(STM32_RCC_CFGR);
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