From 64d149233bb10ab8eea198f1a75eab9c1a806413 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 26 Jun 2013 10:54:12 -0600 Subject: [PATCH] Fix integration of RAM test into the build and configuration system --- arch/arm/src/lpc31xx/Kconfig | 2 +- arch/arm/src/sam34/Kconfig | 8 ++ arch/arm/src/sam34/chip/sam4s_pinmap.h | 86 +++++++------- arch/arm/src/sam34/chip/sam_smc.h | 61 +++++++++- arch/arm/src/sam34/sam3u_gpio.c | 4 + arch/arm/src/sam34/sam4s_gpio.h | 2 +- arch/arm/src/sam34/sam_allocateheap.c | 154 ++++++++++++++++++++++--- arch/arm/src/stm32/stm32_ccm.c | 2 +- arch/arm/src/stm32/stm32_ccm.h | 2 +- 9 files changed, 257 insertions(+), 64 deletions(-) diff --git a/arch/arm/src/lpc31xx/Kconfig b/arch/arm/src/lpc31xx/Kconfig index 531cea0af6..1022cfe601 100644 --- a/arch/arm/src/lpc31xx/Kconfig +++ b/arch/arm/src/lpc31xx/Kconfig @@ -12,7 +12,7 @@ choice config ARCH_CHIP_LPC3130 bool "LPC3130" - select ARCH_HAVE_EXTNAN + select ARCH_HAVE_EXTNAND select ARCH_HAVE_EXTSRAM0 select ARCH_HAVE_EXTSRAM1 select ARCH_HAVE_EXTDRAM diff --git a/arch/arm/src/sam34/Kconfig b/arch/arm/src/sam34/Kconfig index 8bb2e6279c..927a6619d8 100644 --- a/arch/arm/src/sam34/Kconfig +++ b/arch/arm/src/sam34/Kconfig @@ -130,6 +130,10 @@ endchoice config ARCH_CHIP_SAM3U bool default n + select ARCH_HAVE_EXTNOR + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 config ARCH_CHIP_SAM4L bool @@ -139,6 +143,10 @@ config ARCH_CHIP_SAM4L config ARCH_CHIP_SAM4S bool default n + select ARCH_HAVE_EXTNOR + select ARCH_HAVE_EXTNAND + select ARCH_HAVE_EXTSRAM0 + select ARCH_HAVE_EXTSRAM1 menu "AT91SAM3/4 Peripheral Support" diff --git a/arch/arm/src/sam34/chip/sam4s_pinmap.h b/arch/arm/src/sam34/chip/sam4s_pinmap.h index cb6d7eb182..91779aecb7 100644 --- a/arch/arm/src/sam34/chip/sam4s_pinmap.h +++ b/arch/arm/src/sam34/chip/sam4s_pinmap.h @@ -154,49 +154,49 @@ /* Static Memory Controller (SMC) */ -#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN18) -#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN19) -#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN20) -#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN21) -#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN22) -#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN23) -#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN24) -#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN25) -#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN26) -#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN27) -#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN28) -#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN29) -#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN30) -#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN31) -#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN18) -#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN19) -#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN20) -#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN0) -#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN1) -#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23) -#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN24) -#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN25) -#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN0) -#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN1) -#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN2) -#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN3) -#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN4) -#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN5) -#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN6) -#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN7) -#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN16) -#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN17) -#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN9) -#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN10) -#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN14) -#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN15) -#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22) -#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN12) -#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN11) -#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN13) -#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOC | GPIO_PIN8) +#define GPIO_SMC_A0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN18) +#define GPIO_SMC_A1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN19) +#define GPIO_SMC_A2 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN20) +#define GPIO_SMC_A3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN21) +#define GPIO_SMC_A4 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN22) +#define GPIO_SMC_A5 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN23) +#define GPIO_SMC_A6 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN24) +#define GPIO_SMC_A7 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN25) +#define GPIO_SMC_A8 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN26) +#define GPIO_SMC_A9 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN27) +#define GPIO_SMC_A10 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN28) +#define GPIO_SMC_A11 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN29) +#define GPIO_SMC_A12 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN30) +#define GPIO_SMC_A13 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN31) +#define GPIO_SMC_A14 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN18) +#define GPIO_SMC_A15 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN19) +#define GPIO_SMC_A16 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN20) +#define GPIO_SMC_A17 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN0) +#define GPIO_SMC_A18 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN1) +#define GPIO_SMC_A19 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN23) +#define GPIO_SMC_A20 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN24) +#define GPIO_SMC_A21 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_A22 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_A23 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN25) +#define GPIO_SMC_D0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN0) +#define GPIO_SMC_D1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN1) +#define GPIO_SMC_D2 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN2) +#define GPIO_SMC_D3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN3) +#define GPIO_SMC_D4 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN4) +#define GPIO_SMC_D5 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN5) +#define GPIO_SMC_D6 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN6) +#define GPIO_SMC_D7 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN7) +#define GPIO_SMC_NANDALE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN16) +#define GPIO_SMC_NANDCLE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN17) +#define GPIO_SMC_NANDOE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN9) +#define GPIO_SMC_NANDWE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN10) +#define GPIO_SMC_NCS0 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN14) +#define GPIO_SMC_NCS1 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN15) +#define GPIO_SMC_NCS2 (GPIO_PERIPHC | GPIO_CFG_PULLUP | GPIO_PORT_PIOA | GPIO_PIN22) +#define GPIO_SMC_NCS3 (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN12) +#define GPIO_SMC_NRD (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN11) +#define GPIO_SMC_NWAIT (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN13) +#define GPIO_SMC_NWE (GPIO_PERIPHA | GPIO_CFG_PULLUP | GPIO_PORT_PIOC | GPIO_PIN8) /* Serial Peripheral Interface (SPI) */ diff --git a/arch/arm/src/sam34/chip/sam_smc.h b/arch/arm/src/sam34/chip/sam_smc.h index e729c1519e..f099132f0f 100644 --- a/arch/arm/src/sam34/chip/sam_smc.h +++ b/arch/arm/src/sam34/chip/sam_smc.h @@ -83,6 +83,11 @@ # define SAM_SMC_ECCPR15_OFFSET 0x006c /* SMC ECC parity 15 Register */ # define SAM_SMCCS_OFFSET(n) (0x0070+((n)*0x014)) +# define SAM_SMCCS0_OFFSET 0x0070 /* SMC CS0 offset */ +# define SAM_SMCCS1_OFFSET 0x0084 /* SMC CS1 offset */ +# define SAM_SMCCS2_OFFSET 0x0098 /* SMC CS2 offset */ +# define SAM_SMCCS3_OFFSET 0x00ac /* SMC CS3 offset */ + # define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup register */ # define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ # define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ @@ -97,6 +102,11 @@ #elif defined(CONFIG_ARCH_CHIP_SAM4S) # define SAM_SMCCS_OFFSET(n) ((n) << 4) +# define SAM_SMCCS0_OFFSET 0x0000 /* SMC CS0 offset */ +# define SAM_SMCCS1_OFFSET 0x0010 /* SMC CS1 offset */ +# define SAM_SMCCS2_OFFSET 0x0020 /* SMC CS2 offset */ +# define SAM_SMCCS3_OFFSET 0x0030 /* SMC CS3 offset */ + # define SAM_SMCCS_SETUP_OFFSET 0x0000 /* SMC Setup Register */ # define SAM_SMCCS_PULSE_OFFSET 0x0004 /* SMC Pulse Register */ # define SAM_SMCCS_CYCLE_OFFSET 0x0008 /* SMC Cycle Register */ @@ -146,10 +156,11 @@ #endif #define SAM_SMCCS_BASE(n) (SAM_SMC_BASE+SAM_SMCCS_OFFSET(n)) -# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(0)) -# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(1)) -# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(2)) -# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS_OFFSET(3)) +# define SAM_SMC_CS0_BASE (SAM_SMC_BASE+SAM_SMCCS0_OFFSET) +# define SAM_SMC_CS1_BASE (SAM_SMC_BASE+SAM_SMCCS1_OFFSET) +# define SAM_SMC_CS2_BASE (SAM_SMC_BASE+SAM_SMCCS2_OFFSET) +# define SAM_SMC_CS3_BASE (SAM_SMC_BASE+SAM_SMCCS3_OFFSET) + #define SAM_SMCCS_SETUP(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_SETUP_OFFSET) #define SAM_SMCCS_PULSE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_PULSE_OFFSET) #define SAM_SMCCS_CYCLE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_CYCLE_OFFSET) @@ -158,6 +169,38 @@ #endif #define SAM_SMCCS_MODE(n) (SAM_SMCCS_BASE(n)+SAM_SMCCS_MODE_OFFSET) +# define SAM_SMCCS0_SETUP (SAM_SMC_CS0_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS0_PULSE (SAM_SMC_CS0_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS0_CYCLE (SAM_SMC_CS0_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS0_TIMINGS (SAM_SMC_CS0_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS0_MODE (SAM_SMC_CS0_BASE+SAM_SMCCS_MODE_OFFSET) + +# define SAM_SMCCS1_SETUP (SAM_SMC_CS1_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS1_PULSE (SAM_SMC_CS1_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS1_CYCLE (SAM_SMC_CS1_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS1_TIMINGS (SAM_SMC_CS1_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS1_MODE (SAM_SMC_CS1_BASE+SAM_SMCCS_MODE_OFFSET) + +# define SAM_SMCCS2_SETUP (SAM_SMC_CS2_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS2_PULSE (SAM_SMC_CS2_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS2_CYCLE (SAM_SMC_CS2_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS2_TIMINGS (SAM_SMC_CS2_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS2_MODE (SAM_SMC_CS2_BASE+SAM_SMCCS_MODE_OFFSET) + +# define SAM_SMCCS3_SETUP (SAM_SMC_CS3_BASE+SAM_SMCCS_SETUP_OFFSET) +# define SAM_SMCCS3_PULSE (SAM_SMC_CS3_BASE+SAM_SMCCS_PULSE_OFFSET) +# define SAM_SMCCS3_CYCLE (SAM_SMC_CS3_BASE+SAM_SMCCS_CYCLE_OFFSET) +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# define SAM_SMCCS3_TIMINGS (SAM_SMC_CS3_BASE+SAM_SMCCS_TIMINGS_OFFSET) +# endif +# define SAM_SMCCS3_MODE (SAM_SMC_CS3_BASE+SAM_SMCCS_MODE_OFFSET) + #define SAM_SMC_OCMS (SAM_SMC_BASE+SAM_SMC_OCMS_OFFSET) #define SAM_SMC_KEY1 (SAM_SMC_BASE+SAM_SMC_KEY1_OFFSET) #define SAM_SMC_KEY2 (SAM_SMC_BASE+SAM_SMC_KEY2_OFFSET) @@ -374,30 +417,40 @@ #define SMCCS_SETUP_NWESETUP_SHIFT (0) /* Bits 0-5: NWE Setup length */ #define SMCCS_SETUP_NWESETUP_MASK (63 << SMCCS_SETUP_NWESETUP_SHIFT) +# define SMCCS_SETUP_NWESETUP(n) ((n) << SMCCS_SETUP_NWESETUP_SHIFT) #define SMCCS_SETUP_NCSWRSETUP_SHIFT (8) /* Bits 8-13: NCS Setup length in Write access */ #define SMCCS_SETUP_NCSWRSETUP_MASK (63 << SMCCS_SETUP_NCSWRSETUP_SHIFT) +# define SMCCS_SETUP_NCSWRSETUP(n) ((n) << SMCCS_SETUP_NCSWRSETUP_SHIFT) #define SMCCS_SETUP_NRDSETUP_SHIFT (16) /* Bits 16-21: NRD Setup length */ #define SMCCS_SETUP_NRDSETUP_MASK (63 << SMCCS_SETUP_NRDSETUP_SHIFT) +# define SMCCS_SETUP_NRDSETUP(n) ((n) << SMCCS_SETUP_NRDSETUP_SHIFT) #define SMCCS_SETUP_NCSRDSETUP_SHIFT (24) /* Bits 24-29: NCS Setup length in Read access */ #define SMCCS_SETUP_NCSRDSETUP_MASK (63 << SMCCS_SETUP_NCSRDSETUP_SHIFT) +# define SMCCS_SETUP_NCSRDSETUP(n) ((n) << SMCCS_SETUP_NCSRDSETUP_SHIFT) /* SMC Pulse Register */ #define SMCCS_PULSE_NWEPULSE_SHIFT (0) /* Bits 0-5: NWE Pulse Length */ #define SMCCS_PULSE_NWEPULSE_MASK (63 << SMCCS_PULSE_NWEPULSE_SHIFT) +# define SMCCS_PULSE_NWEPULSE(n) ((n) << SMCCS_PULSE_NWEPULSE_SHIFT) #define SMCCS_PULSE_NCSWRPULSE_SHIFT (8) /* Bits 8-13: NCS Pulse Length in WRITE Access */ #define SMCCS_PULSE_NCSWRPULSE_MASK (63 << SMCCS_PULSE_NCSWRPULSE_SHIFT) +# define SMCCS_PULSE_NCSWRPULSE(n) ((n) << SMCCS_PULSE_NCSWRPULSE_SHIFT) #define SMCCS_PULSE_NRDPULSE_SHIFT (16) /* Bits 16-21: NRD Pulse Length */ #define SMCCS_PULSE_NRDPULSE_MASK (63 << SMCCS_PULSE_NRDPULSE_SHIFT) +# define SMCCS_PULSE_NRDPULSE(n) ((n) << SMCCS_PULSE_NRDPULSE_SHIFT) #define SMCCS_PULSE_NCSRDPULSE_SHIFT (24) /* Bits 24-29: NCS Pulse Length in READ Access */ #define SMCCS_PULSE_NCSRDPULSE_MASK (63 << SMCCS_PULSE_NCSRDPULSE_SHIFT) +# define SMCCS_PULSE_NCSRDPULSE(n) ((n) << SMCCS_PULSE_NCSRDPULSE_SHIFT) /* SMC Cycle Register */ #define SMCCS_CYCLE_NWECYCLE_SHIFT (0) /* Bits 0-8: Total Write Cycle Length */ #define SMCCS_CYCLE_NWECYCLE_MASK (0x1ff << SMCCS_CYCLE_NWECYCLE_SHIFT) +# define SMCCS_CYCLE_NWECYCLE(n) ((n) << SMCCS_CYCLE_NWECYCLE_SHIFT) #define SMCCS_CYCLE_NRDCYCLE_SHIFT (16) /* Bits 16-24: Total Read Cycle Length */ #define SMCCS_CYCLE_NRDCYCLE_MASK (0x1ff << SMCCS_CYCLE_NRDCYCLE_SHIFT) +# define SMCCS_CYCLE_NRDCYCLE(n) ((n) << SMCCS_CYCLE_NRDCYCLE_SHIFT) /* SMC Timings Register */ diff --git a/arch/arm/src/sam34/sam3u_gpio.c b/arch/arm/src/sam34/sam3u_gpio.c index a59878a3d1..d00e54ba50 100644 --- a/arch/arm/src/sam34/sam3u_gpio.c +++ b/arch/arm/src/sam34/sam3u_gpio.c @@ -388,6 +388,10 @@ int sam_configgpio(gpio_pinset_t cfgset) case GPIO_PERIPHA: case GPIO_PERIPHB: +#ifdef GPIO_HAVE_PERIPHCD + case GPIO_PERIPHC: + case GPIO_PERIPHD: +#endif ret = sam_configperiph(base, pin, cfgset); break; diff --git a/arch/arm/src/sam34/sam4s_gpio.h b/arch/arm/src/sam34/sam4s_gpio.h index 2217a16483..1d5ee82f2e 100644 --- a/arch/arm/src/sam34/sam4s_gpio.h +++ b/arch/arm/src/sam34/sam4s_gpio.h @@ -64,7 +64,7 @@ * MMM. .... .... .... .... */ -#define GPIO_MODE_SHIFT (17) /* Bits 17-23: GPIO mode */ +#define GPIO_MODE_SHIFT (17) /* Bits 17-19: GPIO mode */ #define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT) # define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */ # define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */ diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c index edacfc6172..47e01e23bd 100644 --- a/arch/arm/src/sam34/sam_allocateheap.c +++ b/arch/arm/src/sam34/sam_allocateheap.c @@ -47,30 +47,109 @@ #include -#include "chip.h" #include "mpu.h" #include "up_arch.h" #include "up_internal.h" + +#include "chip.h" #include "sam_mpuinit.h" +#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) +#endif + /**************************************************************************** * Private Definitions ****************************************************************************/ +/* All SAM's have SRAM0. The SAM3U family also have SRAM1 and possibly + * NFCSRAM. NFCSRAM may not be used, however, if NAND support is enabled. + * In addition, the SAM3U and SAM4S have external SRAM at CS0 (EXTSRAM0). + * Support for external SRAM at CS1-3 is not fully implemented. + */ -#if CONFIG_MM_REGIONS < 2 && SAM34_SRAM1_SIZE > 0 -# warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP" +#undef HAVE_SRAM1_REGION /* Assume no internal SRAM1 */ +#undef HAVE_NFCSRAM_REGION /* Assume no NFC SRAM */ +#undef HAVE_EXTSRAM0_REGION /* Assume no external SRAM at CS0 */ +#undef HAVE_EXTSRAM1_REGION /* Assume no external SRAM at CS1 */ +#undef HAVE_EXTSRAM2_REGION /* Assume no external SRAM at CS2 */ +#undef HAVE_EXTSRAM3_REGION /* Assume no external SRAM at CS3 */ + +/* Check if external SRAM is supported and, if so, it is is intended + * to be used as heap. + */ + +#if !defined(CONFIG_ARCH_EXTSRAM0) || !defined(CONFIG_ARCH_EXTSRAM0HEAP) +# undef CONFIG_ARCH_EXTSRAM0SIZE +# define CONFIG_ARCH_EXTSRAM0SIZE 0 #endif -#if CONFIG_MM_REGIONS < 3 && !defined(CONFIG_SAM34_NAND) -# warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP" +#if !defined(CONFIG_ARCH_EXTSRAM1) || !defined(CONFIG_ARCH_EXTSRAM1HEAP) +# undef CONFIG_ARCH_EXTSRAM1SIZE +# define CONFIG_ARCH_EXTSRAM1SIZE 0 #endif -#if CONFIG_MM_REGIONS > 2 && defined(CONFIG_SAM34_NAND) -# error "CONFIG_MM_REGIONS > 2 but cannot use NFC SRAM" -# undef CONFIG_MM_REGIONS -# define CONFIG_MM_REGIONS 2 +#if !defined(CONFIG_ARCH_EXTSRAM2) || !defined(CONFIG_ARCH_EXTSRAM2HEAP) +# undef CONFIG_ARCH_EXTSRAM2SIZE +# define CONFIG_ARCH_EXTSRAM2SIZE 0 #endif +#if !defined(CONFIG_ARCH_EXTSRAM3) || !defined(CONFIG_ARCH_EXTSRAM3HEAP) +# undef CONFIG_ARCH_EXTSRAM3SIZE +# define CONFIG_ARCH_EXTSRAM3SIZE 0 +#endif + +/* SAM3U Unique memory configurations */ + +#ifdef CONFIG_ARCH_CHIP_SAM3U +# ifdef CONFIG_SAM34_NAND +# undef SAM34_NFCSRAM_SIZE +# define SAM34_NFCSRAM_SIZE 0 +# endif + +# if SAM34_SRAM1_SIZE > 0 +# if CONFIG_MM_REGIONS > 1 +# define HAVE_SRAM1_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 2: SRAM1 not included in HEAP" +# endif +# endif + +# if SAM34_NFCSRAM_SIZE > 0 +# if CONFIG_MM_REGIONS > 2 +# define HAVE_NFCSRAM_REGION +# else +# warning "CONFIG_MM_REGIONS < 3: NFC SRAM not included in HEAP" +# endif + +# if CONFIG_ARCH_EXTSRAM0SIZE > 0 +# if CONFIG_MM_REGIONS > 3 +# define HAVE_EXTSRAM0_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 4: External SRAM not included in HEAP" +# endif +# endif + +# elif CONFIG_ARCH_EXTSRAM0SIZE > 0 +# if CONFIG_MM_REGIONS > 2 +# define HAVE_EXTSRAM0_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 3: External SRAM not included in HEAP" +# endif +# endif +#else + +/* The SAM4S and SAM4L may have only internal SRAM0 and external SRAM0 */ + +# if CONFIG_ARCH_EXTSRAM0SIZE > 0 +# if CONFIG_MM_REGIONS > 1 +# define HAVE_EXTSRAM0_REGION 1 +# else +# warning "CONFIG_MM_REGIONS < 2: External SRAM not included in HEAP" +# endif +# endif +#endif + +/* Check common SRAM0 configuration */ + #if CONFIG_DRAM_END > (SAM_INTSRAM0_BASE+SAM34_SRAM0_SIZE) # error "CONFIG_DRAM_END is beyond the end of SRAM0" # undef CONFIG_DRAM_END @@ -224,7 +303,11 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void up_addregion(void) { -#if SAM34_SRAM1_SIZE > 0 + /* The SAM3U also have SRAM1 and NFCSRAM, We will add these as regions + * the first two additional memory regions if we have them. + */ + +#ifdef HAVE_SRAM1_REGION /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); @@ -233,7 +316,9 @@ void up_addregion(void) kumm_addregion((FAR void*)SAM_INTSRAM1_BASE, SAM34_SRAM1_SIZE); -#if CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 +#endif /* HAVE_SRAM1_REGION */ + +#ifdef HAVE_NFCSRAM_REGION /* Allow user access to the heap memory */ sam_mpu_uheap(SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); @@ -242,7 +327,50 @@ void up_addregion(void) kumm_addregion((FAR void*)SAM_NFCSRAM_BASE, SAM34_NFCSRAM_SIZE); -#endif /* CONFIG_MM_REGIONS > 2 && SAM34_NFCSRAM_SIZE > 0 */ -#endif /* SAM34_SRAM1_SIZE > 0 */ +#endif /* HAVE_NFCSRAM_REGION */ + +#ifdef HAVE_EXTSRAM0_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS0_BASE, CONFIG_ARCH_EXTSRAM0SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS0_BASE, CONFIG_ARCH_EXTSRAM0SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ + +#ifdef HAVE_EXTSRAM1_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS1_BASE, CONFIG_ARCH_EXTSRAM1SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS1_BASE, CONFIG_ARCH_EXTSRAM1SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ + +#ifdef HAVE_EXTSRAM2_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS2_BASE, CONFIG_ARCH_EXTSRAM2SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS2_BASE, CONFIG_ARCH_EXTSRAM2SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ + +#ifdef HAVE_EXTSRAM3_REGION + /* Allow user access to the heap memory */ + + sam_mpu_uheap(SAM_EXTCS3_BASE, CONFIG_ARCH_EXTSRAM3SIZE); + + /* Add the region */ + + kumm_addregion((FAR void*)SAM_EXTCS3_BASE, CONFIG_ARCH_EXTSRAM3SIZE); + +#endif /* HAVE_EXTSRAM0_REGION */ } #endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/stm32/stm32_ccm.c index fbb97c0e92..c3f72a398e 100755 --- a/arch/arm/src/stm32/stm32_ccm.c +++ b/arch/arm/src/stm32/stm32_ccm.c @@ -3,7 +3,7 @@ * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt - * Based on a prototype by Petteri Amimonen + * Based on a prototype by Petteri Aimonen * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/stm32/stm32_ccm.h index 5960acd73d..1314210635 100755 --- a/arch/arm/src/stm32/stm32_ccm.h +++ b/arch/arm/src/stm32/stm32_ccm.h @@ -3,7 +3,7 @@ * * Copyright (C) 2013 Gregory Nutt. All rights reserved. * Author: Gregory Nutt - * Based on a prototype by Petteri Amimonen + * Based on a prototype by Petteri Aimonen * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions