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xtensa/esp32: Add power management of force-sleep

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This commit is contained in:
chenwen 2020-09-15 11:49:14 +08:00 committed by Abdelatif Guettouche
parent 29030557ff
commit 64e2f102ac
18 changed files with 3561 additions and 284 deletions
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4
arch/xtensa/include/xtensa/core_macros.h
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@ -36,4 +36,8 @@
__asm__ __volatile__("rsr.ccount %0":\
"=a"(__ccount)); __ccount; })
# define XTHAL_SET_CCOUNT(v) do { int __ccount = (int)(v); \
__asm__ __volatile__("wsr.ccount %0" :: "a"(__ccount):"memory");\
} while(0)
#endif /* __ARCH_XTENSA_INCUDE_XTENSA_CORE_H */

10
arch/xtensa/src/common/xtensa.h
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@ -40,6 +40,8 @@
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
@ -342,6 +344,14 @@ void up_usbuninitialize(void);
# define up_usbuninitialize()
#endif
/* Power management *********************************************************/
#ifdef CONFIG_PM
void xtensa_pminitialize(void);
#else
# define xtensa_pminitialize()
#endif
/* Debug ********************************************************************/
#ifdef CONFIG_STACK_COLORATION

2
arch/xtensa/src/common/xtensa_initialize.c
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@ -105,7 +105,7 @@ void up_initialize(void)
* with the power management subsystem).
*/
up_pminitialize();
xtensa_pminitialize();
#endif
#ifdef CONFIG_ARCH_DMA

11
arch/xtensa/src/esp32/Make.defs
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@ -57,7 +57,7 @@ CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
# Configuration-dependent common XTENSA files
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CMN_CSRCS += xtensa_idle.c
CMN_CSRCS += esp32_idle.c
endif
ifeq ($(CONFIG_DEBUG_ALERT),y)
@ -89,6 +89,15 @@ CHIP_CSRCS += esp32_timerisr.c
CHIP_CSRCS += esp32_user.c
CHIP_CSRCS += esp32_dma.c
ifeq ($(CONFIG_PM),y)
ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
CHIP_CSRCS += esp32_pminitialize.c
endif
CHIP_CSRCS += esp32_pm.c
endif
CHIP_CSRCS += esp32_rtc.c
ifeq ($(CONFIG_ESP32_I2C),y)
CHIP_CSRCS += esp32_i2c.c
endif

319
arch/xtensa/src/esp32/esp32_clockconfig.c
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@ -28,12 +28,15 @@
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "xtensa.h"
#include "xtensa_attr.h"
#include "hardware/esp32_dport.h"
#include "hardware/esp32_soc.h"
#include "hardware/esp32_uart.h"
#include "esp32_rtc.h"
/****************************************************************************
* Pre-processor Definitions
@ -43,18 +46,16 @@
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif
#ifndef CONFIG_ESP_CONSOLE_UART_NUM
#define CONFIG_ESP_CONSOLE_UART_NUM 0
#endif
#define DEFAULT_CPU_FREQ 80
/****************************************************************************
* Private Types
****************************************************************************/
enum xtal_freq_e
{
XTAL_40M = 40,
XTAL_26M = 26,
XTAL_24M = 24,
XTAL_AUTO = 0
};
enum cpu_freq_e
{
CPU_80M = 0,
@ -66,8 +67,37 @@ enum cpu_freq_e
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: esp32_uart_tx_wait_idle
*
* Description:
* Wait until uart tx full empty and the last char send ok.
*
* Input Parameters:
* uart_no - 0 for UART0, 1 for UART1, 2 for UART2
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32_uart_tx_wait_idle(uint8_t uart_no)
{
uint32_t status;
do
{
status = getreg32(UART_STATUS_REG(uart_no));
/* either tx count or state is non-zero */
}
while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
}
/****************************************************************************
* Public Functions
****************************************************************************/
extern uint32_t g_ticks_per_us_pro;
extern void ets_delay_us(int delay_us);
/****************************************************************************
* Name: esp32_set_cpu_freq
@ -84,10 +114,10 @@ extern void ets_delay_us(int delay_us);
*
****************************************************************************/
static void esp32_set_cpu_freq(int cpu_freq_mhz)
void IRAM_ATTR esp32_set_cpu_freq(int cpu_freq_mhz)
{
int dbias = DIG_DBIAS_80M_160M;
int per_conf;
int per_conf = CPU_240M;
uint32_t value;
switch (cpu_freq_mhz)
@ -115,233 +145,9 @@ static void esp32_set_cpu_freq(int cpu_freq_mhz)
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL,
RTC_CNTL_SOC_CLK_SEL_PLL);
g_ticks_per_us_pro = cpu_freq_mhz;
}
/****************************************************************************
* Name: esp32_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
{
uint8_t div_ref;
uint8_t div7_0;
uint8_t div10_8;
uint8_t lref;
uint8_t dcur;
uint8_t bw;
uint8_t i2c_bbpll_lref;
uint8_t i2c_bbpll_div_7_0;
uint8_t i2c_bbpll_dcur;
if (pll_freq == RTC_PLL_FREQ_320M)
{
/* Raise the voltage, if needed */
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK,
DIG_DBIAS_80M_160M);
/* Configure 320M PLL */
switch (xtal_freq)
{
case XTAL_40M:
div_ref = 0;
div7_0 = 32;
div10_8 = 0;
lref = 0;
dcur = 6;
bw = 3;
break;
case XTAL_26M:
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
lref = 1;
dcur = 0;
bw = 1;
break;
case XTAL_24M:
div_ref = 11;
div7_0 = 224;
div10_8 = 4;
lref = 1;
dcur = 0;
bw = 1;
break;
default:
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
lref = 0;
dcur = 0;
bw = 0;
break;
}
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP,
BBPLL_BBADC_DSMP_VAL_320M);
}
else
{
/* Raise the voltage */
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
ets_delay_us(DELAY_PLL_DBIAS_RAISE);
/* Configure 480M PLL */
switch (xtal_freq)
{
case XTAL_40M:
div_ref = 0;
div7_0 = 28;
div10_8 = 0;
lref = 0;
dcur = 6;
bw = 3;
break;
case XTAL_26M:
div_ref = 12;
div7_0 = 144;
div10_8 = 4;
lref = 1;
dcur = 0;
bw = 1;
break;
case XTAL_24M:
div_ref = 11;
div7_0 = 144;
div10_8 = 4;
lref = 1;
dcur = 0;
bw = 1;
break;
default:
div_ref = 12;
div7_0 = 224;
div10_8 = 4;
lref = 0;
dcur = 0;
bw = 0;
break;
}
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M);
I2C_WRITEREG_RTC(I2C_BBPLL,
I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M);
}
i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref);
i2c_bbpll_div_7_0 = div7_0;
i2c_bbpll_dcur = (bw << 6) | dcur;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
}
/****************************************************************************
* Name: esp32_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp32_bbpll_enable(void)
{
modifyreg32(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0);
/* reset BBPLL configuration */
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY,
BBPLL_IR_CAL_DELAY_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP,
BBPLL_IR_CAL_EXT_CAP_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL,
BBPLL_OC_ENB_FCAL_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON,
BBPLL_OC_ENB_VCON_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0,
BBPLL_BBADC_CAL_7_0_VAL);
}
/****************************************************************************
* Name: esp32_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
static void esp32_update_to_xtal(int freq, int div)
{
uint32_t value = (((freq * MHZ) >> 12) & UINT16_MAX)
| ((((freq * MHZ) >> 12) & UINT16_MAX) << 16);
putreg32(value, RTC_APB_FREQ_REG);
/* set divider from XTAL to APB clock */
REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
/* switch clock source */
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL,
RTC_CNTL_SOC_CLK_SEL_XTL);
/* adjust ref_tick */
modifyreg32(APB_CTRL_XTAL_TICK_CONF_REG, 0,
(freq * MHZ) / REF_CLK_FREQ - 1);
/* lower the voltage */
if (freq <= 2)
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
}
else
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
}
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32_clockconfig
*
@ -355,8 +161,9 @@ static void esp32_update_to_xtal(int freq, int div)
void esp32_clockconfig(void)
{
uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
uint32_t source_freq_mhz;
enum xtal_freq_e xtal_freq = XTAL_40M;
enum esp32_rtc_xtal_freq_e xtal_freq = RTC_XTAL_FREQ_40M;
switch (freq_mhz)
{
@ -373,19 +180,47 @@ void esp32_clockconfig(void)
return;
}
esp32_update_to_xtal(xtal_freq, 1);
esp32_bbpll_enable();
esp32_bbpll_configure(xtal_freq, source_freq_mhz);
esp32_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
esp32_rtc_update_to_xtal(xtal_freq, 1);
esp32_rtc_bbpll_enable();
esp32_rtc_bbpll_configure(xtal_freq, source_freq_mhz);
esp32_set_cpu_freq(freq_mhz);
}
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_clk_cpu_freq(void)
{
return g_ticks_per_us_pro * MHZ;
}
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int IRAM_ATTR esp_clk_apb_freq(void)
{
return MIN(g_ticks_per_us_pro, 80) * MHZ;
}

53
arch/xtensa/src/esp32/esp32_clockconfig.h
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@ -40,12 +40,29 @@
* Included Files
****************************************************************************/
#include "xtensa_attr.h"
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_set_cpu_freq
*
* Description:
* Switch to one of PLL-based frequencies.
* Current frequency can be XTAL or PLL.
*
* Input Parameters:
* cpu_freq_mhz - new CPU frequency
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_set_cpu_freq(int cpu_freq_mhz);
/****************************************************************************
* Name: esp32_clockconfig
*
@ -58,8 +75,36 @@
void esp32_clockconfig(void);
int IRAM_ATTR esp_clk_cpu_freq(void);
/****************************************************************************
* Name: esp_clk_cpu_freq
*
* Description:
* Get CPU frequency
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_clk_apb_freq(void);
int esp_clk_cpu_freq(void);
/****************************************************************************
* Name: esp_clk_apb_freq
*
* Description:
* Return current APB clock frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* APB clock frequency, in Hz
*
****************************************************************************/
int esp_clk_apb_freq(void);
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */

185
arch/xtensa/src/esp32/esp32_idle.c Normal file
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@ -0,0 +1,185 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <nuttx/arch.h>
#include <nuttx/power/pm.h>
#include "esp32_pm.h"
#include "xtensa.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Values for the RTC Alarm to wake up from the PM_STANDBY mode
* (which corresponds to ESP32 stop mode). If this alarm expires,
* the logic in this file will wakeup from PM_STANDBY mode and
* transition to PM_SLEEP mode (ESP32 standby mode).
*/
#ifdef CONFIG_PM
#ifndef CONFIG_PM_ALARM_SEC
# define CONFIG_PM_ALARM_SEC 15
#endif
#ifndef CONFIG_PM_ALARM_NSEC
# define CONFIG_PM_ALARM_NSEC 0
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = spin_lock_irqsave();
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
{
/* Configure the RTC alarm to Auto Wake the system */
esp32_pmstart(CONFIG_PM_ALARM_SEC * 1000000 +
CONFIG_PM_ALARM_NSEC / 1000);
/* Resume normal operation */
pm_relax(PM_IDLE_DOMAIN, PM_STANDBY);
}
break;
case PM_SLEEP:
{
pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL);
newstate = PM_NORMAL;
}
break;
default:
break;
}
spin_unlock_irqrestore(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when their is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* This would be an appropriate place to put some MCU-specific logic to
* sleep in a reduced power mode until an interrupt occurs to save power
*/
#if XCHAL_HAVE_INTERRUPTS
__asm__ __volatile__ ("waiti 0");
#endif
#endif
}

787
arch/xtensa/src/esp32/esp32_pm.c Normal file
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@ -0,0 +1,787 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_pm.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifdef CONFIG_PM
#include <arch/chip/chip.h>
#include <stdbool.h>
#include <stdint.h>
#include <stdio.h>
#include <errno.h>
#include <sys/time.h>
#include "hardware/esp32_rtccntl.h"
#include "hardware/esp32_uart.h"
#include "xtensa.h"
#include "xtensa_attr.h"
#include "esp32_rtc.h"
#include "esp32_clockconfig.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* If light sleep time is less than that, don't power down flash */
#define FLASH_PD_MIN_SLEEP_TIME_US 2000
/* Minimal amount of time we can sleep for. */
#define LIGHT_SLEEP_MIN_TIME_US 200
#ifndef MAX
#define MAX(a,b) a > b ? a : b
#endif
/* Time from VDD_SDIO power up to first flash read in ROM code */
#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700
/* Extra time it takes to enter and exit light sleep and deep sleep */
#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */
#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */
#define RTC_EXT0_TRIG_EN BIT(0) /* EXT0 GPIO wakeup */
#define RTC_EXT1_TRIG_EN BIT(1) /* EXT1 GPIO wakeup */
#define RTC_GPIO_TRIG_EN BIT(2) /* GPIO wakeup (light sleep only) */
#define RTC_TIMER_TRIG_EN BIT(3) /* Timer wakeup */
#define RTC_SDIO_TRIG_EN BIT(4) /* SDIO wakeup (light sleep only) */
#define RTC_MAC_TRIG_EN BIT(5) /* MAC wakeup (light sleep only) */
#define RTC_UART0_TRIG_EN BIT(6) /* UART0 wakeup (light sleep only) */
#define RTC_UART1_TRIG_EN BIT(7) /* UART1 wakeup (light sleep only) */
#define RTC_TOUCH_TRIG_EN BIT(8) /* Touch wakeup */
#define RTC_ULP_TRIG_EN BIT(9) /* ULP wakeup */
#define RTC_BT_TRIG_EN BIT(10) /* BT wakeup (light sleep only) */
/****************************************************************************
* Private Types
****************************************************************************/
/* Power down options */
enum esp32_sleep_pd_option_e
{
/* Power down the power domain in sleep mode */
ESP_PD_OPTION_OFF,
/* Keep power domain enabled during sleep mode */
ESP_PD_OPTION_ON,
/* Keep power domain enabled in sleep mode if it is needed
* by one of the wakeup options, otherwise power it down.
*/
ESP_PD_OPTION_AUTO
};
/* Power domains which can be powered down in sleep mode. */
enum esp_sleep_pd_domain_e
{
ESP_PD_DOMAIN_RTC_PERIPH, /* RTC IO, sensors and ULP co-processor */
ESP_PD_DOMAIN_RTC_SLOW_MEM, /* RTC slow memory */
ESP_PD_DOMAIN_RTC_FAST_MEM, /* RTC fast memory */
ESP_PD_DOMAIN_XTAL, /* XTAL oscillator */
ESP_PD_DOMAIN_MAX /* Number of domains */
};
/* Internal structure which holds all requested deep sleep parameters. */
struct esp32_sleep_config_t
{
enum esp32_sleep_pd_option_e pd_options[ESP_PD_DOMAIN_MAX];
uint64_t sleep_duration;
uint32_t wakeup_triggers : 11;
uint32_t ext1_trigger_mode : 1;
uint32_t ext1_rtc_gpio_mask : 18;
uint32_t ext0_trigger_level : 1;
uint32_t ext0_rtc_gpio_num : 5;
uint32_t sleep_time_adjustment;
uint64_t rtc_ticks_at_sleep_start;
};
/* Structure describing vddsdio configuration. */
struct rtc_vddsdio_config_s
{
uint32_t force : 1; /* If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. */
uint32_t enable : 1; /* Enable VDDSDIO regulator */
uint32_t tieh : 1; /* Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V */
uint32_t drefh : 2; /* Tuning parameter for VDDSDIO regulator */
uint32_t drefm : 2; /* Tuning parameter for VDDSDIO regulator */
uint32_t drefl : 2; /* Tuning parameter for VDDSDIO regulator */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void esp32_timer_wakeup_prepare(void);
static void IRAM_ATTR esp32_flush_uarts(void);
static void IRAM_ATTR esp32_suspend_uarts(void);
static void IRAM_ATTR esp32_resume_uarts(void);
static uint32_t esp32_get_power_down_flags(void);
static inline void esp32_uart_tx_wait_idle(uint8_t uart_no);
static void IRAM_ATTR esp32_set_vddsdio_config(
struct rtc_vddsdio_config_s config);
static int IRAM_ATTR esp32_get_vddsdio_config(
struct rtc_vddsdio_config_s *config);
int IRAM_ATTR esp32_light_sleep_inner(uint32_t pd_flags,
uint32_t time_us, struct rtc_vddsdio_config_s config);
static int IRAM_ATTR esp32_configure_cpu_freq(uint32_t cpu_freq_mhz);
/****************************************************************************
* Public Data
****************************************************************************/
extern uint32_t g_ticks_per_us_pro;
/****************************************************************************
* Private Data
****************************************************************************/
static struct esp32_sleep_config_t s_config =
{
.pd_options =
{ ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
.wakeup_triggers = 0
};
/****************************************************************************
* Private Functions
****************************************************************************/
extern void ets_delay_us(uint32_t us);
/****************************************************************************
* Name: esp32_uart_tx_wait_idle
*
* Description:
* Wait until uart tx full empty and the last char send ok.
*
* Input Parameters:
* uart_no - 0 for UART0, 1 for UART1, 2 for UART2
*
* Returned Value:
* None
*
****************************************************************************/
static inline void esp32_uart_tx_wait_idle(uint8_t uart_no)
{
uint32_t status;
do
{
status = getreg32(UART_STATUS_REG(uart_no));
/* either tx count or state is non-zero */
}
while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0);
}
/****************************************************************************
* Name: esp32_flush_uarts
*
* Description:
* Wait until UART0/UART1/UART2 tx full empty and the last char send ok
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void IRAM_ATTR esp32_flush_uarts(void)
{
int i;
for (i = 0; i < ESP32_NUARTS; ++i)
{
esp32_uart_tx_wait_idle(i);
}
}
/****************************************************************************
* Name: esp32_suspend_uarts
*
* Description:
* Suspend UART0/UART1/UART2 output
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void IRAM_ATTR esp32_suspend_uarts(void)
{
int i;
for (i = 0; i < ESP32_NUARTS; ++i)
{
modifyreg32(UART_FLOW_CONF_REG(i), 0, UART_FORCE_XOFF);
while (REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT) != 0);
}
}
/****************************************************************************
* Name: esp32_resume_uarts
*
* Description:
* Re-enable UART0/UART1/UART2 output
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void IRAM_ATTR esp32_resume_uarts(void)
{
int i;
for (i = 0; i < ESP32_NUARTS; ++i)
{
modifyreg32(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF, 0);
modifyreg32(UART_FLOW_CONF_REG(i), 0, UART_FORCE_XON);
modifyreg32(UART_FLOW_CONF_REG(i), UART_FORCE_XON, 0);
}
}
/****************************************************************************
* Name: esp32_get_power_down_flags
*
* Description:
* Get power domains that can be powered down
*
* Input Parameters:
* None
*
* Returned Value:
* Power domains
*
****************************************************************************/
static uint32_t esp32_get_power_down_flags(void)
{
uint32_t pd_flags = 0;
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO)
{
s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
}
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO)
{
if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN))
{
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
}
else if (s_config.wakeup_triggers &
(RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN))
{
/* In both rev. 0 and rev. 1 of ESP32,
* forcing power up of prevents ULP timer
* and touch FSMs from working correctly.
*/
s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
}
}
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO)
{
s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
}
/* Prepare flags based on the selected options */
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON)
{
pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
}
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON)
{
pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
}
if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON)
{
pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
}
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON)
{
pd_flags |= RTC_SLEEP_PD_XTAL;
}
return pd_flags;
}
/****************************************************************************
* Name: esp32_timer_wakeup_prepare
*
* Description:
* Configure timer to wake-up
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static void esp32_timer_wakeup_prepare(void)
{
uint32_t period;
int64_t sleep_duration;
int64_t rtc_count_delta;
period = getreg32(RTC_SLOW_CLK_CAL_REG);
sleep_duration = (int64_t) s_config.sleep_duration -
(int64_t) s_config.sleep_time_adjustment;
if (sleep_duration < 0)
{
sleep_duration = 0;
}
rtc_count_delta = esp32_rtc_time_us_to_slowclk(sleep_duration, period);
esp32_rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start +
rtc_count_delta);
}
/****************************************************************************
* Name: esp32_set_vddsdio_config
*
* Description:
* Set new VDDSDIO configuration using RTC registers.
*
* Input Parameters:
* New VDDSDIO configuration
*
* Returned Value:
* None
*
****************************************************************************/
static void IRAM_ATTR esp32_set_vddsdio_config(
struct rtc_vddsdio_config_s config)
{
uint32_t val = 0;
val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
val |= RTC_CNTL_SDIO_PD_EN;
putreg32((uint32_t)val, RTC_CNTL_SDIO_CONF_REG);
}
/****************************************************************************
* Name: esp32_get_vddsdio_config
*
* Description:
* Get current VDDSDIO configuration.
*
* Input Parameters:
* Incoming parameter address of VDDSDIO configuration to be saved
*
* Returned Value:
* Zero (OK) is returned on success.
*
****************************************************************************/
static int IRAM_ATTR esp32_get_vddsdio_config(
struct rtc_vddsdio_config_s *config)
{
struct rtc_vddsdio_config_s *result = config;
uint32_t efuse_reg;
uint32_t strap_reg;
uint32_t sdio_conf_reg = getreg32(RTC_CNTL_SDIO_CONF_REG);
result->drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M)
>> RTC_CNTL_DREFH_SDIO_S;
result->drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M)
>> RTC_CNTL_DREFM_SDIO_S;
result->drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M)
>> RTC_CNTL_DREFL_SDIO_S;
if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE)
{
/* Get configuration from RTC */
result->force = 1;
result->enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M)
>> RTC_CNTL_XPD_SDIO_REG_S;
result->tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M)
>> RTC_CNTL_SDIO_TIEH_S;
return OK;
}
efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG);
if (efuse_reg & EFUSE_RD_SDIO_FORCE)
{
/* Get configuration from EFUSE */
result->force = 0;
result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M)
>> EFUSE_RD_XPD_SDIO_REG_S;
result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M)
>> EFUSE_RD_SDIO_TIEH_S;
if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG,
EFUSE_RD_BLK3_PART_RESERVE) == 0)
{
result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M)
>> EFUSE_RD_SDIO_DREFH_S;
result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M)
>> EFUSE_RD_SDIO_DREFM_S;
result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M)
>> EFUSE_RD_SDIO_DREFL_S;
}
return OK;
}
/* Otherwise, VDD_SDIO is controlled by bootstrapping pin */
strap_reg = getreg32(GPIO_STRAP_REG);
result->force = 0;
result->tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V
: RTC_VDDSDIO_TIEH_3_3V;
result->enable = 1;
return OK;
}
/****************************************************************************
* Name: esp32_sleep_start
*
* Description:
* Enter low power mode.
*
* Input Parameters:
* Power domains
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
static int IRAM_ATTR esp32_sleep_start(uint32_t pd_flags)
{
int result;
uint32_t cur_freq;
/* Stop UART output so that output is not lost due to APB frequency change.
* For light sleep, suspend UART output — it will resume after wakeup.
* For deep sleep, wait for the contents of UART FIFO to be sent.
*/
if (pd_flags & RTC_SLEEP_PD_DIG)
{
esp32_flush_uarts();
}
else
{
esp32_suspend_uarts();
}
/* Save current frequency and switch to XTAL */
cur_freq = esp_clk_cpu_freq() / MHZ;
esp32_rtc_cpu_freq_set_xtal();
/* Enter sleep */
esp32_rtc_sleep_init(pd_flags);
/* Configure timer wakeup */
if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN)
&& s_config.sleep_duration > 0)
{
esp32_timer_wakeup_prepare();
}
esp32_rtc_sleep_start(s_config.wakeup_triggers, 0);
/* Restore CPU frequency */
result = esp32_configure_cpu_freq(cur_freq);
esp32_resume_uarts();
return result;
}
/****************************************************************************
* Name: esp32_light_sleep_inner
*
* Description:
* Enter low power mode, then wait for flash to be ready on wakeup
*
* Input Parameters:
* pd_flags - Power domains
* time_us - Time to wait for spi_flash become ready
* config - VDDSDIO configuration
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32_light_sleep_inner(uint32_t pd_flags,
uint32_t time_us, struct rtc_vddsdio_config_s config)
{
/* Enter sleep */
int err = esp32_sleep_start(pd_flags);
/* If VDDSDIO regulator was controlled by RTC registers before sleep.
* restore the configuration.
*/
if (config.force)
{
esp32_set_vddsdio_config(config);
}
/* If SPI flash was powered down, wait for it to become ready. */
if (pd_flags & RTC_SLEEP_PD_VDDSDIO)
{
/* Wait for the flash chip to start up. */
ets_delay_us(time_us);
}
return err;
}
/****************************************************************************
* Name: esp32_configure_cpu_freq
*
* Description:
* Switch to new CPU frequencies.
*
* Input Parameters:
* cpu_freq_mhz - new CPU frequency
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
static int IRAM_ATTR esp32_configure_cpu_freq(uint32_t cpu_freq_mhz)
{
uint32_t soc_clk_sel;
uint32_t source_freq_mhz;
enum esp32_rtc_xtal_freq_e xtal_freq;
if (cpu_freq_mhz == 240)
{
source_freq_mhz = RTC_PLL_FREQ_480M;
}
else if(cpu_freq_mhz == 80 || cpu_freq_mhz == 160)
{
source_freq_mhz = RTC_PLL_FREQ_320M;
}
else
{
return EINVAL;
}
xtal_freq = esp32_rtc_clk_xtal_freq_get();
soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL)
{
esp32_rtc_update_to_xtal(xtal_freq, 1);
esp32_rtc_wait_for_slow_cycle();
}
if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL)
{
esp32_rtc_bbpll_disable();
}
esp32_rtc_bbpll_enable();
esp32_rtc_wait_for_slow_cycle();
esp32_rtc_bbpll_configure(xtal_freq, source_freq_mhz);
esp32_set_cpu_freq(cpu_freq_mhz);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32_sleep_enable_timer_wakeup
*
* Description:
* Configure wake-up interval
*
* Input Parameters:
* time_in_us - Configure wake-up time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_sleep_enable_timer_wakeup(uint64_t time_in_us)
{
s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN;
s_config.sleep_duration = time_in_us;
}
/****************************************************************************
* Name: esp32_light_sleep_start
*
* Description:
* Enter sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32_light_sleep_start(void)
{
uint32_t pd_flags;
uint32_t flash_enable_time_us;
uint32_t vddsdio_pd_sleep_duration;
struct rtc_vddsdio_config_s vddsdio_config;
int ret = OK;
s_config.rtc_ticks_at_sleep_start = esp32_rtc_time_get();
/* Decide which power domains can be powered down */
pd_flags = esp32_get_power_down_flags();
/* Amount of time to subtract from actual sleep time.
* This is spent on entering and leaving light sleep.
*/
s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US;
/* Decide if VDD_SDIO needs to be powered down;
* If it needs to be powered down, adjust sleep time.
*/
flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US
+ CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY;
vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US
+ LIGHT_SLEEP_MIN_TIME_US);
if (s_config.sleep_duration > vddsdio_pd_sleep_duration)
{
pd_flags |= RTC_SLEEP_PD_VDDSDIO;
s_config.sleep_time_adjustment += flash_enable_time_us;
}
esp32_get_vddsdio_config(&vddsdio_config);
/* Enter sleep, then wait for flash to be ready on wakeup */
ret = esp32_light_sleep_inner(pd_flags, flash_enable_time_us,
vddsdio_config);
return ret;
}
/****************************************************************************
* Name: esp32_pminit
*
* Description:
* Initialize force sleep parameters.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_pminit(void)
{
/* Initialize RTC parameters */
esp32_rtc_init();
esp32_rtc_clk_set();
}
/****************************************************************************
* Name: esp32_pmstart
*
* Description:
* Enter force sleep time interval.
*
* Input Parameters:
* time_in_us - force sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_pmstart(uint64_t time_in_us)
{
/* don't power down XTAL — powering it up takes different time on. */
fflush(stdout);
esp32_sleep_enable_timer_wakeup(time_in_us);
esp32_light_sleep_start();
}
#endif /* CONFIG_PM */

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/****************************************************************************
* arch/xtensa/src/esp32/esp32_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_PMSLEEP_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_PMSLEEP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_sleep_enable_timer_wakeup
*
* Description:
* Configure wake-up interval
*
* Input Parameters:
* time_in_us - Configure wake-up time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp32_light_sleep_start
*
* Description:
* Enter sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32_light_sleep_start(void);
/****************************************************************************
* Name: esp32_pminit
*
* Description:
* Initialize force sleep parameters.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_pminit(void);
/****************************************************************************
* Name: esp32_pmstart
*
* Description:
* Enter force sleep time interval.
*
* Input Parameters:
* time_in_us - force sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_pmstart(uint64_t time_in_us);
#endif /* CONFIG_PM */
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_PMSLEEP_H */

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/****************************************************************************
* arch/xtensa/src/esp32/esp32_pminitialize.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/power/pm.h>
#include "esp32_pm.h"
#ifdef CONFIG_PM
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xtensa_pminitialize
*
* Description:
* Initialize the power management subsystem.
*
****************************************************************************/
void xtensa_pminitialize(void)
{
/* Initialize RTC parameters */
esp32_pminit();
/* Then initialize the NuttX power management subsystem proper */
pm_initialize();
}
#endif /* CONFIG_PM */

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/****************************************************************************
* arch/xtensa/src/esp32/esp32_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_H
#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/* Possible main XTAL frequency values.
* Enum values should be equal to frequency in MHz.
*/
enum esp32_rtc_xtal_freq_e
{
RTC_XTAL_FREQ_AUTO = 0, /* Automatic XTAL frequency detection */
RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */
RTC_XTAL_FREQ_26M = 26, /* 26 MHz XTAL */
RTC_XTAL_FREQ_24M = 24, /* 24 MHz XTAL */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32_rtc_xtal_freq_e esp32_rtc_clk_xtal_freq_get(void);
/****************************************************************************
* Name: esp32_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void esp32_rtc_update_to_xtal(int freq, int div);
/****************************************************************************
* Name: esp32_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_bbpll_enable(void);
/****************************************************************************
* Name: esp32_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_bbpll_configure(
enum esp32_rtc_xtal_freq_e xtal_freq, int pll_freq);
/****************************************************************************
* Name: esp32_rtc_clk_set
*
* Description:
* Set RTC CLK frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_clk_set(void);
/****************************************************************************
* Name: esp32_rtc_init
*
* Description:
* Initialize RTC clock and power control related functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_init(void);
/****************************************************************************
* Name: esp32_rtc_time_get
*
* Description:
* Get current value of RTC counter.
*
* Input Parameters:
* None
*
* Returned Value:
* current value of RTC counter
*
****************************************************************************/
uint64_t esp32_rtc_time_get(void);
/****************************************************************************
* Name: esp32_rtc_time_us_to_slowclk
*
* Description:
* Convert time interval from microseconds to RTC_SLOW_CLK cycles.
*
* Input Parameters:
* time_in_us - Time interval in microseconds
* slow_clk_period - Period of slow clock in microseconds
*
* Returned Value:
* number of slow clock cycles
*
****************************************************************************/
uint64_t esp32_rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
/****************************************************************************
* Name: esp32_rtc_bbpll_disable
*
* Description:
* disable BBPLL.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_bbpll_disable(void);
/****************************************************************************
* Name: esp32_rtc_sleep_set_wakeup_time
*
* Description:
* Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source.
*
* Input Parameters:
* t - value of RTC counter at which wakeup from sleep will happen.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_sleep_set_wakeup_time(uint64_t t);
/****************************************************************************
* Name: esp32_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void esp32_rtc_wait_for_slow_cycle(void);
/****************************************************************************
* Name: esp32_rtc_cpu_freq_set_xtal
*
* Description:
* Switch CPU clock source to XTAL
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_cpu_freq_set_xtal(void);
/****************************************************************************
* Name: esp32_rtc_sleep_init
*
* Description:
* Prepare the chip to enter sleep mode
*
* Input Parameters:
* flags - sleep mode configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32_rtc_sleep_init(uint32_t flags);
/****************************************************************************
* Name: esp32_rtc_sleep_start
*
* Description:
* Enter force sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
void esp32_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_H */

3
arch/xtensa/src/esp32/hardware/esp32_dport.h
View File

@ -201,6 +201,9 @@
#define DPORT_CPUPERIOD_SEL_M ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
#define DPORT_CPUPERIOD_SEL_V 0x3
#define DPORT_CPUPERIOD_SEL_S 0
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
#define DPORT_CPUPERIOD_SEL_240 2
#define DPORT_PRO_CACHE_CTRL_REG (DR_REG_DPORT_BASE + 0x040)

47
arch/xtensa/src/esp32/hardware/esp32_i2s.h Normal file
View File

@ -0,0 +1,47 @@
/****************************************************************************
* arch/xtensa/src/esp32/esp32_i2s.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_I2S_H
#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_I2S_H
#include "esp32_soc.h"
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + ((i)*0x1e000))
#define I2S_PD_CONF_REG(i) (REG_I2S_BASE(i) + 0x00a4)
/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */
#define I2S_PLC_MEM_FORCE_PU (BIT(3))
#define I2S_PLC_MEM_FORCE_PU_M (BIT(3))
#define I2S_PLC_MEM_FORCE_PU_V 0x1
#define I2S_PLC_MEM_FORCE_PU_S 3
/* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */
#define I2S_FIFO_FORCE_PU (BIT(1))
#define I2S_FIFO_FORCE_PU_M (BIT(1))
#define I2S_FIFO_FORCE_PU_V 0x1
#define I2S_FIFO_FORCE_PU_S 1
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_I2S_H */

257
arch/xtensa/src/esp32/hardware/esp32_rtccntl.h
View File

@ -479,6 +479,7 @@
#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF
#define RTC_CNTL_PLL_BUF_WAIT_S 24
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
@ -488,6 +489,7 @@
#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF
#define RTC_CNTL_XTL_BUF_WAIT_S 14
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20
/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
@ -497,6 +499,7 @@
#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
#define RTC_CNTL_CK8M_WAIT_V 0xFF
#define RTC_CNTL_CK8M_WAIT_S 6
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
@ -636,12 +639,13 @@
/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
/* Description: minimal sleep cycles in slow_clk_rtc */
/* description: minimal sleep cycles in slow_clk_rtc */
#define RTC_CNTL_MIN_SLP_VAL 0x000000FF
#define RTC_CNTL_MIN_SLP_VAL 0x000000ff
#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
#define RTC_CNTL_MIN_SLP_VAL_V 0xFF
#define RTC_CNTL_MIN_SLP_VAL_V 0xff
#define RTC_CNTL_MIN_SLP_VAL_S 8
#define RTC_CNTL_MIN_SLP_VAL_MIN 2
/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */
@ -1138,6 +1142,8 @@
#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50)
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
/* Description: 32-bit general purpose retention register */
@ -1320,15 +1326,6 @@
#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1
#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
/* Description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL */
#define RTC_CNTL_SOC_CLK_SEL 0x00000003
#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V)<<(RTC_CNTL_SOC_CLK_SEL_S))
#define RTC_CNTL_SOC_CLK_SEL_V 0x3
#define RTC_CNTL_SOC_CLK_SEL_S 27
/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
/* Description: CK8M force power up */
@ -1610,6 +1607,7 @@
#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S))
#define RTC_CNTL_DBG_ATTEN_V 0x3
#define RTC_CNTL_DBG_ATTEN_S 24
#define RTC_CNTL_DBG_ATTEN_DEFAULT 3
#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
@ -1678,15 +1676,6 @@
#define RTC_CNTL_SCK_DCAP_V 0xFF
#define RTC_CNTL_SCK_DCAP_S 14
/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
/* Description: DIG_REG_DBIAS during wakeup */
#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007
#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S))
#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7
#define RTC_CNTL_DIG_DBIAS_WAK_S 11
/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */
/* Description: DIG_REG_DBIAS during sleep */
@ -2962,4 +2951,230 @@
#define RTC_CNTL_CNTL_DATE_S 0
#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280
/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */
#define RTC_CNTL_CPU_ROM_RAM_PD_EN \
(RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\
RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\
RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN)
#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \
(RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\
RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\
RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU)
#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \
(RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\
RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\
RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD
/* Useful groups of RTC_CNTL_PWC_REG bits */
#define RTC_CNTL_MEM_FORCE_ISO \
(RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO)
#define RTC_CNTL_MEM_FORCE_NOISO \
(RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
#define RTC_CNTL_MEM_PD_EN \
(RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN)
#define RTC_CNTL_MEM_FORCE_PU \
(RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
#define RTC_CNTL_MEM_FORCE_PD \
(RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD)
#define RTC_CNTL_MEM_FOLW_CPU \
(RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
#define RTC_CNTL_MEM_FORCE_LPU \
(RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU)
#define RTC_CNTL_MEM_FORCE_LPD \
(RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD)
/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */
#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \
(RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\
RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\
RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO)
#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \
(RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\
RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\
RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO)
/* Deep sleep (power down digital domain) */
#define RTC_SLEEP_PD_DIG BIT(0)
/* Power down RTC peripherals */
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1)
/* Power down RTC SLOW memory */
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2)
/* Power down RTC FAST memory */
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3)
/* RTC FAST and SLOW memories are automatically
* powered up and down along with the CPU
*/
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)
/* Power down VDDSDIO regulator */
#define RTC_SLEEP_PD_VDDSDIO BIT(5)
/* Power down main XTAL */
#define RTC_SLEEP_PD_XTAL BIT(6)
#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xbc)
/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
/* description: select the wakeup source Ó0Ó select
* GPIO0 Ó1Ó select GPIO2 ...Ò17Ó select GPIO17
*/
#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001f
#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1f
#define RTC_IO_EXT_WAKEUP0_SEL_S 27
/* RTC_CNTL_WDT_STGX : */
/* description: stage action selection values */
#define RTC_WDT_STG_SEL_OFF 0
#define RTC_WDT_STG_SEL_INT 1
#define RTC_WDT_STG_SEL_RESET_CPU 2
#define RTC_WDT_STG_SEL_RESET_SYSTEM 3
#define RTC_WDT_STG_SEL_RESET_RTC 4
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK,
* RTC_CNTL_DBIAS_SLP, RTC_CNTL_DIG_DBIAS_WAK,
* RTC_CNTL_DIG_DBIAS_SLP values. Valid if RTC_CNTL_DBG_ATTEN is 0.
*/
#define RTC_CNTL_DBIAS_0V90 0
#define RTC_CNTL_DBIAS_0V95 1
#define RTC_CNTL_DBIAS_1V00 2
#define RTC_CNTL_DBIAS_1V05 3
#define RTC_CNTL_DBIAS_1V10 4
#define RTC_CNTL_DBIAS_1V15 5
#define RTC_CNTL_DBIAS_1V20 6
#define RTC_CNTL_DBIAS_1V25 7
#define RTC_IO_XTAL_32K_PAD_REG (DR_REG_RTCIO_BASE + 0x8c)
/* RTC_IO_XPD_XTAL_32K : R/W ;bitpos:[19] ;default: 1'd0 ; */
/* description: Power up 32kHz crystal oscillator */
#define RTC_IO_XPD_XTAL_32K (BIT(19))
#define RTC_IO_XPD_XTAL_32K_M (BIT(19))
#define RTC_IO_XPD_XTAL_32K_V 0x1
#define RTC_IO_XPD_XTAL_32K_S 19
/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[18] ;default: 1'd0 ; */
/* description: Ò1Ó select the digital function Ó0Óslection
* the rtc function
*/
#define RTC_IO_X32N_MUX_SEL (BIT(18))
#define RTC_IO_X32N_MUX_SEL_M (BIT(18))
#define RTC_IO_X32N_MUX_SEL_V 0x1
#define RTC_IO_X32N_MUX_SEL_S 18
/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
/* description: Ò1Ó select the digital function Ó0Óslection
* the rtc function
*/
#define RTC_IO_X32P_MUX_SEL (BIT(17))
#define RTC_IO_X32P_MUX_SEL_M (BIT(17))
#define RTC_IO_X32P_MUX_SEL_V 0x1
#define RTC_IO_X32P_MUX_SEL_S 17
/* RTC_IO_X32P_RDE : R/W ;bitpos:[23] ;default: 1'd0 ; */
/* description: the pull down enable of the pad */
#define RTC_IO_X32P_RDE (BIT(23))
#define RTC_IO_X32P_RDE_M (BIT(23))
#define RTC_IO_X32P_RDE_V 0x1
#define RTC_IO_X32P_RDE_S 23
/* RTC_IO_X32P_RUE : R/W ;bitpos:[22] ;default: 1'd0 ; */
/* description: the pull up enable of the pad */
#define RTC_IO_X32P_RUE (BIT(22))
#define RTC_IO_X32P_RUE_M (BIT(22))
#define RTC_IO_X32P_RUE_V 0x1
#define RTC_IO_X32P_RUE_S 22
/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
/* description: the pull up enable of the pad */
#define RTC_IO_X32N_RUE (BIT(27))
#define RTC_IO_X32N_RUE_M (BIT(27))
#define RTC_IO_X32N_RUE_V 0x1
#define RTC_IO_X32N_RUE_S 27
/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
/* description: the pull down enable of the pad */
#define RTC_IO_X32N_RDE (BIT(28))
#define RTC_IO_X32N_RDE_M (BIT(28))
#define RTC_IO_X32N_RDE_V 0x1
#define RTC_IO_X32N_RDE_S 28
/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[11] ;default: 1'd0 ; */
/* description: the input enable of the pad */
#define RTC_IO_X32N_FUN_IE (BIT(11))
#define RTC_IO_X32N_FUN_IE_M (BIT(11))
#define RTC_IO_X32N_FUN_IE_V 0x1
#define RTC_IO_X32N_FUN_IE_S 11
/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[5] ;default: 1'd0 ; */
/* description: the input enable of the pad */
#define RTC_IO_X32P_FUN_IE (BIT(5))
#define RTC_IO_X32P_FUN_IE_M (BIT(5))
#define RTC_IO_X32P_FUN_IE_V 0x1
#define RTC_IO_X32P_FUN_IE_S 5
/* RTC_IO_DAC_XTAL_32K : R/W ;bitpos:[21:20] ;default: 2'b01 ; */
/* description: 32K XTAL bias current DAC. */
#define RTC_IO_DAC_XTAL_32K 0x00000003
#define RTC_IO_DAC_XTAL_32K_M ((RTC_IO_DAC_XTAL_32K_V)<<(RTC_IO_DAC_XTAL_32K_S))
#define RTC_IO_DAC_XTAL_32K_V 0x3
#define RTC_IO_DAC_XTAL_32K_S 20
/* RTC_IO_DRES_XTAL_32K : R/W ;bitpos:[4:3] ;default: 2'b10 ; */
/* description: 32K XTAL resistor bias control. */
#define RTC_IO_DRES_XTAL_32K 0x00000003
#define RTC_IO_DRES_XTAL_32K_M ((RTC_IO_DRES_XTAL_32K_V)<<(RTC_IO_DRES_XTAL_32K_S))
#define RTC_IO_DRES_XTAL_32K_V 0x3
#define RTC_IO_DRES_XTAL_32K_S 3
/* RTC_IO_DBIAS_XTAL_32K : R/W ;bitpos:[2:1] ;default: 2'b00 ; */
/* description: 32K XTAL self-bias reference control. */
#define RTC_IO_DBIAS_XTAL_32K 0x00000003
#define RTC_IO_DBIAS_XTAL_32K_M ((RTC_IO_DBIAS_XTAL_32K_V)<<(RTC_IO_DBIAS_XTAL_32K_S))
#define RTC_IO_DBIAS_XTAL_32K_V 0x3
#define RTC_IO_DBIAS_XTAL_32K_S 1
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_XTENSA_ESP32_H */

239
arch/xtensa/src/esp32/hardware/esp32_soc.h
View File

@ -110,13 +110,13 @@
* used when _f is not left shifted by _f##_S
*/
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f))
#define REG_GET_FIELD(_r, _f) ((REG_READ(_r) >> (_f##_S)) & (_f##_V))
/* Set field to register,
* used when _f is not left shifted by _f##_S
*/
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f) << (_f##_S)))|(((_v) & (_f))<<(_f##_S)))))
#define REG_SET_FIELD(_r, _f, _v) (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))))
/* Set field value from a variable,
* used when _f is not left shifted by _f##_S
@ -207,6 +207,7 @@
#define DR_REG_GPIO_SD_BASE 0x3ff44f00
#define DR_REG_FE2_BASE 0x3ff45000
#define DR_REG_FE_BASE 0x3ff46000
#define DR_REG_FRC_TIMER_BASE 0x3ff47000
#define DR_REG_RTCCNTL_BASE 0x3ff48000
#define DR_REG_RTCIO_BASE 0x3ff48400
#define DR_REG_SARADC_BASE 0x3ff48800
@ -214,9 +215,9 @@
#define DR_REG_RTCMEM0_BASE 0x3ff61000
#define DR_REG_RTCMEM1_BASE 0x3ff62000
#define DR_REG_RTCMEM2_BASE 0x3ff63000
#define DR_REG_HINF_BASE 0x3ff4B000
#define DR_REG_UHCI1_BASE 0x3ff4C000
#define DR_REG_I2S_BASE 0x3ff4F000
#define DR_REG_HINF_BASE 0x3ff4b000
#define DR_REG_UHCI1_BASE 0x3ff4c000
#define DR_REG_I2S_BASE 0x3ff4f000
#define DR_REG_UART1_BASE 0x3ff50000
#define DR_REG_BT_BASE 0x3ff51000
#define DR_REG_I2C_EXT_BASE 0x3ff53000
@ -226,20 +227,22 @@
#define DR_REG_PCNT_BASE 0x3ff57000
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_LEDC_BASE 0x3ff59000
#define DR_REG_EFUSE_BASE 0x3ff5A000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5B000
#define DR_REG_PWM_BASE 0x3ff5E000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5F000
#define DR_REG_EFUSE_BASE 0x3ff5a000
#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5b000
#define DR_REG_NRX_BASE 0x3ff5cc00
#define DR_REG_BB_BASE 0x3ff5d000
#define DR_REG_PWM_BASE 0x3ff5e000
#define DR_REG_TIMERGROUP0_BASE 0x3ff5f000
#define DR_REG_TIMERGROUP1_BASE 0x3ff60000
#define DR_REG_SPI2_BASE 0x3ff64000
#define DR_REG_SPI3_BASE 0x3ff65000
#define DR_REG_I2C1_EXT_BASE 0x3ff67000
#define DR_REG_SDMMC_BASE 0x3ff68000
#define DR_REG_EMAC_BASE 0x3ff69000
#define DR_REG_PWM1_BASE 0x3ff6C000
#define DR_REG_I2S1_BASE 0x3ff6D000
#define DR_REG_UART2_BASE 0x3ff6E000
#define DR_REG_PWM2_BASE 0x3ff6F000
#define DR_REG_PWM1_BASE 0x3ff6c000
#define DR_REG_I2S1_BASE 0x3ff6d000
#define DR_REG_UART2_BASE 0x3ff6e000
#define DR_REG_PWM2_BASE 0x3ff6f000
#define DR_REG_PWM3_BASE 0x3ff70000
#define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE
@ -317,6 +320,10 @@
#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */
#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */
#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010)
#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c)
#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038)
/* Interrupt cpu using table */
/****************************************************************************
@ -418,6 +425,9 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
#define I2C_WRITEREG_RTC(block, reg_add, indata) \
rom_i2c_writeReg(block, block##_HOSTID, reg_add, indata)
#define I2C_READREG_RTC(block, reg_add) \
rom_i2c_readReg(block, block##_HOSTID, reg_add)
/* BBPLL configuration values */
#define BBPLL_ENDIV5_VAL_320M 0x43
@ -432,9 +442,83 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
#define BBPLL_BBADC_CAL_7_0_VAL 0x00
#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
/* description: This field stores the voltage level for
* CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
* 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
*/
#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S))
#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03
#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */
/* description: read for sdio_force */
#define EFUSE_RD_SDIO_FORCE (BIT(16))
#define EFUSE_RD_SDIO_FORCE_M (BIT(16))
#define EFUSE_RD_SDIO_FORCE_V 0x1
#define EFUSE_RD_SDIO_FORCE_S 16
/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */
/* description: read for XPD_SDIO_REG */
#define EFUSE_RD_XPD_SDIO_REG (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14))
#define EFUSE_RD_XPD_SDIO_REG_V 0x1
#define EFUSE_RD_XPD_SDIO_REG_S 14
/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */
/* description: read for SDIO_TIEH */
#define EFUSE_RD_SDIO_TIEH (BIT(15))
#define EFUSE_RD_SDIO_TIEH_M (BIT(15))
#define EFUSE_RD_SDIO_TIEH_V 0x1
#define EFUSE_RD_SDIO_TIEH_S 15
/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */
/* description: If set, this bit indicates that
* BLOCK3[143:96] is reserved for internal use
*/
#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14))
#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S))
#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1
#define EFUSE_RD_BLK3_PART_RESERVE_S 14
/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFH 0x00000003
#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S))
#define EFUSE_RD_SDIO_DREFH_V 0x3
#define EFUSE_RD_SDIO_DREFH_S 8
/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFM 0x00000003
#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S))
#define EFUSE_RD_SDIO_DREFM_V 0x3
#define EFUSE_RD_SDIO_DREFM_S 10
/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space.
* Newer versions of ESP32 come with EFUSE_ADC_VREF already burned,
* therefore SDIO_DREFH/M/L is only available in older versions of ESP32
*/
/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */
#define EFUSE_RD_SDIO_DREFL 0x00000003
#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S))
#define EFUSE_RD_SDIO_DREFL_V 0x3
#define EFUSE_RD_SDIO_DREFL_S 12
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
@ -463,6 +547,8 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007
#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V) << (RTC_CNTL_DIG_DBIAS_WAK_S))
#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7
#define RTC_CNTL_DIG_DBIAS_WAK_S 11
/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ;
@ -470,6 +556,8 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
*/
#define RTC_CNTL_SOC_CLK_SEL 0x00000003
#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V) << (RTC_CNTL_SOC_CLK_SEL_S))
#define RTC_CNTL_SOC_CLK_SEL_V 0x3
#define RTC_CNTL_SOC_CLK_SEL_S 27
#define RTC_CNTL_SOC_CLK_SEL_XTL 0
#define RTC_CNTL_SOC_CLK_SEL_PLL 1
@ -492,6 +580,9 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
#else
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
#endif
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
@ -536,4 +627,126 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
#define TIMG_RTC_CALI_CLK_SEL 0x00000003
#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V) << (TIMG_RTC_CALI_CLK_SEL_S))
#define TIMG_RTC_CALI_CLK_SEL_V 0x3
#define TIMG_RTC_CALI_CLK_SEL_S 13
/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12))
#define TIMG_RTC_CALI_START_CYCLING_V 0x1
#define TIMG_RTC_CALI_START_CYCLING_S 12
/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
#define TIMG_RTC_CALI_START (BIT(31))
#define TIMG_RTC_CALI_START_M (BIT(31))
#define TIMG_RTC_CALI_START_V 0x1
#define TIMG_RTC_CALI_START_S 31
/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
#define TIMG_RTC_CALI_MAX 0x00007fff
#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V) << (TIMG_RTC_CALI_MAX_S))
#define TIMG_RTC_CALI_MAX_V 0x7fff
#define TIMG_RTC_CALI_MAX_S 16
/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
#define TIMG_RTC_CALI_VALUE 0x01ffffff
#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V) << (TIMG_RTC_CALI_VALUE_S))
#define TIMG_RTC_CALI_VALUE_V 0x1ffffff
#define TIMG_RTC_CALI_VALUE_S 7
/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
#define TIMG_RTC_CALI_RDY (BIT(15))
#define TIMG_RTC_CALI_RDY_M (BIT(15))
#define TIMG_RTC_CALI_RDY_V 0x1
#define TIMG_RTC_CALI_RDY_S 15
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c)
/* Some of the baseband control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
#define BB_FFT_FORCE_PU (BIT(3))
#define BB_FFT_FORCE_PU_M (BIT(3))
#define BB_FFT_FORCE_PU_V 1
#define BB_FFT_FORCE_PU_S 3
#define BB_FFT_FORCE_PD (BIT(2))
#define BB_FFT_FORCE_PD_M (BIT(2))
#define BB_FFT_FORCE_PD_V 1
#define BB_FFT_FORCE_PD_S 2
#define BB_DC_EST_FORCE_PU (BIT(1))
#define BB_DC_EST_FORCE_PU_M (BIT(1))
#define BB_DC_EST_FORCE_PU_V 1
#define BB_DC_EST_FORCE_PU_S 1
#define BB_DC_EST_FORCE_PD (BIT(0))
#define BB_DC_EST_FORCE_PD_M (BIT(0))
#define BB_DC_EST_FORCE_PD_V 1
#define BB_DC_EST_FORCE_PD_S 0
/* Some of the WiFi RX control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
#define NRX_RX_ROT_FORCE_PU (BIT(5))
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
#define NRX_RX_ROT_FORCE_PU_V 1
#define NRX_RX_ROT_FORCE_PU_S 5
#define NRX_RX_ROT_FORCE_PD (BIT(4))
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
#define NRX_RX_ROT_FORCE_PD_V 1
#define NRX_RX_ROT_FORCE_PD_S 4
#define NRX_VIT_FORCE_PU (BIT(3))
#define NRX_VIT_FORCE_PU_M (BIT(3))
#define NRX_VIT_FORCE_PU_V 1
#define NRX_VIT_FORCE_PU_S 3
#define NRX_VIT_FORCE_PD (BIT(2))
#define NRX_VIT_FORCE_PD_M (BIT(2))
#define NRX_VIT_FORCE_PD_V 1
#define NRX_VIT_FORCE_PD_S 2
#define NRX_DEMAP_FORCE_PU (BIT(1))
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
#define NRX_DEMAP_FORCE_PU_V 1
#define NRX_DEMAP_FORCE_PU_S 1
#define NRX_DEMAP_FORCE_PD (BIT(0))
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
#define NRX_DEMAP_FORCE_PD_V 1
#define NRX_DEMAP_FORCE_PD_S 0
/* Some of the RF frontend control registers.
* PU/PD fields defined here are used in sleep related functions.
*/
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
#define FE_IQ_EST_FORCE_PU (BIT(5))
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
#define FE_IQ_EST_FORCE_PU_V 1
#define FE_IQ_EST_FORCE_PU_S 5
#define FE_IQ_EST_FORCE_PD (BIT(4))
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
#define FE_IQ_EST_FORCE_PD_V 1
#define FE_IQ_EST_FORCE_PD_S 4
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
#define FE2_TX_INF_FORCE_PU (BIT(10))
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
#define FE2_TX_INF_FORCE_PU_V 1
#define FE2_TX_INF_FORCE_PU_S 10
#define FE2_TX_INF_FORCE_PD (BIT(9))
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
#define FE2_TX_INF_FORCE_PD_V 1
#define FE2_TX_INF_FORCE_PD_S 9
#define PIN_CTRL (DR_REG_IO_MUX_BASE +0x00)
#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */

18
boards/xtensa/esp32/esp32-core/Kconfig
View File

@ -63,4 +63,22 @@ choice
depends on FS_LITTLEFS
endchoice
if PM
config PM_ALARM_SEC
int "PM_STANDBY delay (seconds)"
default 15
depends on PM
---help---
Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode.
config PM_ALARM_NSEC
int "PM_STANDBY delay (nanoseconds)"
default 0
depends on PM
---help---
Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode.
endif # PM
endif # ARCH_BOARD_ESP32CORE

50
boards/xtensa/esp32/esp32-core/configs/pm/defconfig Normal file
View File

@ -0,0 +1,50 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDOPT_HEXDUMP is not set
# CONFIG_NSH_CMDPARMS is not set
CONFIG_ARCH="xtensa"
CONFIG_ARCH_BOARD="esp32-core"
CONFIG_ARCH_BOARD_ESP32CORE=y
CONFIG_ARCH_CHIP="esp32"
CONFIG_ARCH_CHIP_ESP32=y
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_XTENSA=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_ESP32_UART0=y
CONFIG_EXPERIMENTAL=y
CONFIG_FS_PROCFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=3072
CONFIG_INTELHEX_BINARY=y
CONFIG_MAX_TASKS=16
CONFIG_MM_REGIONS=2
CONFIG_NFILE_DESCRIPTORS=8
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_LINELEN=64
CONFIG_NSH_READLINE=y
CONFIG_PM=y
CONFIG_PM_GOVERNOR_GREEDY=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_RAM_SIZE=114688
CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_WAITPID=y
CONFIG_SDCLONE_DISABLE=y
CONFIG_SPI=y
CONFIG_START_DAY=6
CONFIG_START_MONTH=12
CONFIG_START_YEAR=2011
CONFIG_SYSTEM_NSH=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_USER_ENTRYPOINT="nsh_main"