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PIC32MZ: Fix reserved RAM for MPLABX; Revert FPLLRNG calculation; Fix maximum DMTCNT value

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This commit is contained in:
Gregory Nutt 2015-02-28 12:49:03 -06:00
parent 80f298ebf7
commit 64e8b5624c
4 changed files with 37 additions and 15 deletions
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2
arch/mips/src/pic32mz/chip/pic32mzec-features.h
View File

@ -440,7 +440,7 @@
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
# define DEVCFG1_DMTCNT_MIN (0 << DEVCFG1_DMTCNT_SHIFT) /* 2**8 (256) */
# define DEVCFG1_DMTCNT_MAX (12 << DEVCFG1_DMTCNT_SHIFT) /* 2**318 (2147483648) */
# define DEVCFG1_DMTCNT_MAX (28 << DEVCFG1_DMTCNT_SHIFT) /* 2**318 (2147483648) */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */

8
arch/mips/src/pic32mz/pic32mz-config.h
View File

@ -211,13 +211,13 @@
#if (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 5000000
# error BOARD_PLL_INPUT / BOARD_PLL_IDIV too low
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_BYPASS /* < 5 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 8000000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 9000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_5_10MHZ /* 5-10 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 13000000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 14500000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_8_16MHZ /* 8-16 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 210000000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 23500000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_13_26MHZ /* 13-26 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 36000000
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 39000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_21_42MHZ /* 21-42 MHz */
#elif (BOARD_PLL_INPUT / BOARD_PLL_IDIV) < 64000000
# define CONFIG_PIC32MZ_FPLLRNG DEVCFG2_FPLLRNG_34_64MHZ /* 36-64 MHz */

21
configs/pic32mz-starterkit/scripts/c32-release.ld
View File

@ -44,8 +44,19 @@ MEMORY
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
* FLASH at physical address 0x1fc00000. The initial reset vector is in
* KSEG1, but all other accesses are in KSEG0.
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
* may be mappled to the lower boot alias region (0x1fc00000,
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
* This linker script assumes that Boot Flash 1 is mapped to the lower
* alias region and Boot Flash 2 to the upper region.
*
* NOTE: This linker script simply writes into the lower boot alias,
* whichever boot FLASH that may correspond to. The other boot FLASH
* is simply ignored.
*
* The initial reset vector is in KSEG1, but all other accesses are in
* KSEG0.
*
* REGION PHYSICAL KSEG SIZE
* DESCRIPTION START ADDR (BYTES)
@ -85,11 +96,11 @@ MEMORY
* of data memory at physical address 0x00000000. Since the PIC32MZ
* has no data cache, this memory is always accessed through KSEG1.
*
* When used with MPLAB, we need to set aside 512 bytes of memory
* for use by MPLAB.
* When used with MPLABX, we need to set aside 512 bytes of memory
* for use by MPLABX and 128 for DSP register storage.
*/
kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 512
kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
}
OUTPUT_FORMAT("elf32-tradlittlemips")

21
configs/pic32mz-starterkit/scripts/mips-release.ld
View File

@ -44,8 +44,19 @@ MEMORY
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
* FLASH at physical address 0x1fc00000. The initial reset vector is in
* KSEG1, but all other accesses are in KSEG0.
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
* may be mappled to the lower boot alias region (0x1fc00000,
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
* This linker script assumes that Boot Flash 1 is mapped to the lower
* alias region and Boot Flash 2 to the upper region.
*
* NOTE: This linker script simply writes into the lower boot alias,
* whichever boot FLASH that may correspond to. The other boot FLASH
* is simply ignored.
*
* The initial reset vector is in KSEG1, but all other accesses are in
* KSEG0.
*
* REGION PHYSICAL KSEG SIZE
* DESCRIPTION START ADDR (BYTES)
@ -85,11 +96,11 @@ MEMORY
* of data memory at physical address 0x00000000. Since the PIC32MZ
* has no data cache, this memory is always accessed through KSEG1.
*
* When used with MPLAB, we need to set aside 512 bytes of memory
* for use by MPLAB.
* When used with MPLABX, we need to set aside 512 bytes of memory
* for use by MPLABX and 128 for DSP register storage.
*/
kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 512
kseg1_datamem (w!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
}
OUTPUT_FORMAT("elf32-littlemips")