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Merged in raiden00/nuttx_lora/g0_port (pull request #878)

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arch/stm32g0, configs/nucleo-g071rb: the basic NSH configuration is now functional

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
raiden00pl 2019-05-30 11:44:10 +00:00 committed by Gregory Nutt
parent c9ecd548e0
commit 64feadfc21
8 changed files with 57 additions and 33 deletions
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1
arch/arm/Kconfig
View File

@ -320,7 +320,6 @@ config ARCH_CHIP_STM32L0
config ARCH_CHIP_STM32G0
bool "STMicro STM32 G0"
select ARCH_CORTEXM0
depends on EXPERIMENTAL
---help---
STMicro STM32G0 architectures (ARM Cortex-M0).

10
arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h
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@ -123,11 +123,11 @@
/* AHB2 Base Addresses **************************************************************/
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
#define STM32_GPIOD_BASE 0X48000C00 /* 0x48000c00-0x48000fff: GPIO Port D */
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
#define STM32_GPIOA_BASE 0x50000000 /* 0x50000000-0x500003ff: GPIO Port A */
#define STM32_GPIOB_BASE 0x50000400 /* 0x50000400-0x500007ff: GPIO Port B */
#define STM32_GPIOC_BASE 0x50000800 /* 0x50000800-0x50000bff: GPIO Port C */
#define STM32_GPIOD_BASE 0X50000C00 /* 0x50000c00-0x50000fff: GPIO Port D */
#define STM32_GPIOF_BASE 0x50001400 /* 0x50001400-0x500017ff: GPIO Port F */
/* Cortex-M4 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this

14
arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h
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@ -111,6 +111,8 @@
#define RCC_CR_PLLRDY (1 << 25) /* Bit 25: PLL clock ready flag */
/* Bits 26-27: Reserved */
#define RCC_CR_RESET 0x00000500
/* Internal clock sources calibration register */
#define RCC_ICSCR_HSICAL_SHIFT (0) /* Bits 0-7: Internal high speed clock calibration */
@ -159,6 +161,8 @@
#define RCC_CFGR_MCOPRE_SHIFT (28) /* Bits 28-30: Microcontroller clock output selection */
#define RCC_CFGR_MCOPRE_MASK (7 << RCC_CFGR_MCOPRE_SHIFT)
#define RCC_CFGR_RESET 0x00000000
/* PLL clock configuration register */
#define RCC_PLLCFG_PLLSRC_SHIFT (0) /* Bits 0-1: PLL entry clock source */
@ -169,7 +173,7 @@
/* Bits 2-3: Reserved */
#define RCC_PLLCFG_PLLM_SHIFT (4) /* Bits 4-6: Division factor M of the PLL input clock divider */
#define RCC_PLLCFG_PLLM_MASK (7 << RCC_PLLCFG_PLLM_SHIFT)
#define RCC_PLLCFG_PLLM(n) ((n) << RCC_PLLCFG_PLLM_SHIFT)
#define RCC_PLLCFG_PLLM(n) ((n-1) << RCC_PLLCFG_PLLM_SHIFT)
/* Bit 7: Reserved */
#define RCC_PLLCFG_PLLN_SHIFT (8) /* Bits 8-14: PLL frequency multiplication factor N */
#define RCC_PLLCFG_PLLN_MASK (0x7f << RCC_PLLCFG_PLLN_SHIFT)
@ -178,16 +182,18 @@
#define RCC_PLLCFG_PLLPEN (1 << 16) /* Bit 16: PLLPCLK clock output enable */
#define RCC_PLLCFG_PLLP_SHIFT (17) /* Bits 17-21: PLL VCO division factor P for PLLPCLK clock output */
#define RCC_PLLCFG_PLLP_MASK (0x1f << RCC_PLLCFG_PLLP_SHIFT)
#define RCC_PLLCFG_PLLP(n) ((n+1) << RCC_PLLCFG_PLLP_SHIFT) /* n=2,...,32 */
#define RCC_PLLCFG_PLLP(n) ((n-1) << RCC_PLLCFG_PLLP_SHIFT) /* n=2,...,32 */
/* Bits 22-23: Reserved */
#define RCC_PLLCFG_PLLQEN (1 << 24) /* Bit 24: PLLQCLK clock output enable */
#define RCC_PLLCFG_PLLQ_SHIFT (25) /* Bits 25-27: Division factor Q of the PLL input clock divider */
#define RCC_PLLCFG_PLLQ_MASK (7 << RCC_PLLCFG_PLLQ_SHIFT)
#define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT)
#define RCC_PLLCFG_PLLQ(n) ((n-1) << RCC_PLLCFG_PLLQ_SHIFT)
#define RCC_PLLCFG_PLLREN (1 << 28) /* Bit 28: PLLRCLK clock output enable */
#define RCC_PLLCFG_PLLR_SHIFT (29) /* Bits 29-31: Division factor R of the PLL input clock divider */
#define RCC_PLLCFG_PLLR_MASK (7 << RCC_PLLCFG_PLLR_SHIFT)
#define RCC_PLLCFG_PLLR(n) ((n) << RCC_PLLCFG_PLLR_SHIFT)
#define RCC_PLLCFG_PLLR(n) ((n-1) << RCC_PLLCFG_PLLR_SHIFT)
#define RCC_PLLCFGR_RESET 0x00001000
/* TODO: Clock Source Interrupt enable register */

2
arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c
View File

@ -62,7 +62,7 @@
#ifdef HAVE_CONSOLE
# if defined(CONFIG_USART1_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART1_BASE
# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART1_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY

16
arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c
View File

@ -82,8 +82,8 @@
# elif defined(CONFIG_USART2_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART2_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART2EN
# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART2_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY
@ -101,8 +101,8 @@
# elif defined(CONFIG_USART3_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART3_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART3EN
# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART3_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY
@ -120,8 +120,8 @@
# elif defined(CONFIG_USART4_SERIAL_CONSOLE)
# define STM32_CONSOLE_BASE STM32_USART4_BASE
# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY
# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR
# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART4EN
# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR
# define STM32_CONSOLE_APBEN RCC_APB1ENR_USART4EN
# define STM32_CONSOLE_BAUD CONFIG_USART4_BAUD
# define STM32_CONSOLE_BITS CONFIG_USART4_BITS
# define STM32_CONSOLE_PARITY CONFIG_USART4_PARITY
@ -290,7 +290,7 @@ void up_lowputc(char ch)
void stm32_lowsetup(void)
{
#if defined(HAVE_UART)
#if defined(HAVE_USART)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
uint32_t cr;
#endif
@ -360,5 +360,5 @@ void stm32_lowsetup(void)
putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET);
#endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */
#endif /* HAVE_UART */
#endif /* HAVE_USART */
}

18
arch/arm/src/stm32f0l0g0/stm32g0_rcc.c
View File

@ -75,7 +75,17 @@ static inline void rcc_reset(void)
{
uint32_t regval;
regval = getreg32(STM32_RCC_APB1ENR);
/* Reset CFGR register */
putreg32(RCC_CFGR_RESET, STM32_RCC_CFGR);
/* Reset CR register */
putreg32(RCC_CR_RESET, STM32_RCC_CR);
/* Reset PLLCFGR register */
putreg32(RCC_PLLCFGR_RESET, STM32_RCC_PLLCFG);
#if 1
/* DBG clock enable */
@ -561,6 +571,12 @@ static void stm32_stdclockconfig(void)
/* Write PLLCFG register */
putreg32(regval, STM32_RCC_PLLCFG);
/* Enable PLL */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLON;
putreg32(regval, STM32_RCC_CR);
#endif
/* Select the system clock source (probably the PLL) */

2
configs/nucleo-g071rb/README.txt
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@ -30,3 +30,5 @@ STATUS
2019-05-27: Brings in initial WIP support for the STM32 G0.
Not tested on hardware.
2019-05-30: The basic NSH configuration is now functional.

27
configs/nucleo-g071rb/include/board.h
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@ -54,22 +54,22 @@
/* Clocking *****************************************************************/
/* HSI - Internal 8 MHz RC Oscillator
/* HSI - Internal 16 MHz RC Oscillator
* LSI - 32 KHz RC
* HSE - 8 MHz from MCO output of ST-LINK
* HSE - 8 MHz from MCO output of ST-LINK (disabled by default)
* LSE - 32.768 kHz
*/
#define STM32_BOARD_XTAL 8000000ul
#define STM32_HSI_FREQUENCY 8000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000 /* Between 30kHz and 60kHz */
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* Main PLL Configuration.
*
* PLL source is HSE = 8,000,000
* PLL source is HSI = 16,000,000
*
* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* Subject to:
@ -82,33 +82,34 @@
*
*/
#define STM32_BOARD_USEHSE
#define STM32_HSEBYP_ENABLE
/* PLL source is HSE, PLLN=50, PLLM=2
/* PLL source is HSI, PLLN=50, PLLM=4
* PLLP enable, PLLQ enable, PLLR enable
*
* 2 <= PLLP <= 32
* 2 <= PLLQ <= 8
* 2 <= PLLR <= 8
*
* PLLR <= 64MHz
* PLLQ <= 128MHz
* PLLP <= 128MHz
*
* PLL_VCO = (8,000,000 / 2) * 50 = 200 MHz
* PLL_VCO = (16,000,000 / 4) * 50 = 200 MHz
*
* PLLP = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
* PLLQ = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
* PLLR = PLL_VCO/4 = 200 MHz / 4 = 40 MHz
*/
#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSE
#define STM32_PLLCFG_PLLSRC RCC_PLLCFG_PLLSRC_HSI
#define STM32_PLLCFG_PLLCFG (RCC_PLLCFG_PLLPEN | \
RCC_PLLCFG_PLLQEN | \
RCC_PLLCFG_PLLREN)
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2)
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(4)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(50)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP(4)
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLQ(8)
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4)
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(4)
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 50)
#define STM32_PLLP_FREQUENCY (STM32_VCO_FREQUENCY / 4)