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Fix nxstyle warnings

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This commit is contained in:
raiden00pl 2020-10-10 17:00:18 +02:00 committed by patacongo
parent 17255414b5
commit 650997e1f6
48 changed files with 1175 additions and 1062 deletions
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62
arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
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@ -1,4 +1,4 @@
/****************************************************************************************************
/************************************************************************************
* arch/arm/src/stm32/hardware/stm32f33xxx_comp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,30 +16,30 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H
/****************************************************************************************************
/************************************************************************************
* Included Files
****************************************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
************************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_COMP2_CSR_OFFSET 0x0020 /* COMP2 Control register */
#define STM32_COMP4_CSR_OFFSET 0x0028 /* COMP4 Control register */
#define STM32_COMP6_CSR_OFFSET 0x0030 /* COMP6 Control register */
/* Register Addresses *******************************************************************************/
/* Register Addresses ***************************************************************/
#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET)
#define STM32_COMP4_CSR (STM32_COMP_BASE+STM32_COMP4_CSR_OFFSET)
@ -49,9 +49,9 @@
/* COMP control and status register */
#define COMP_CSR_COMPEN (1 << 0) /* Bit 0: Comparator enable */
/* Bits 1-3: Reserved */
#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 4-6: Comparator inverting input selection */
#define COMP_CSR_COMPEN (1 << 0) /* Bit 0: Comparator enable */
/* Bits 1-3: Reserved */
#define COMP_CSR_INMSEL_SHIFT (4) /* Bits 4-6: Comparator inverting input selection */
#define COMP_CSR_INMSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT)
# define COMP_CSR_INMSEL_1P4VREF (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: 1/4 of Vrefint */
# define COMP_CSR_INMSEL_1P2VREF (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: 1/2 of Vrefint */
@ -64,8 +64,8 @@
# define COMP_CSR_INMSEL_PB2 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB2 (COMP4 only) */
# define COMP_CSR_INMSEL_PB15 (7 << COMP_CSR_INMSEL_SHIFT) /* 0111: PB15 (COMP6 only) */
/* 1000: DAC2_CH1 output, look at bit 22 */
/* Bits 7-9: Reserved */
#define COMP_CSR_OUTSEL_SHIFT (4) /* Bits 10-13: Comparator output selection */
/* Bits 7-9: Reserved */
#define COMP_CSR_OUTSEL_SHIFT (4) /* Bits 10-13: Comparator output selection */
#define COMP_CSR_OUTSEL_MASK (15 << COMP_CSR_INMSEL_SHIFT)
# define COMP_CSR_OUTSEL_NOSEL (0 << COMP_CSR_INMSEL_SHIFT) /* 0000: No selection */
# define COMP_CSR_OUTSEL_BRKACTH (1 << COMP_CSR_INMSEL_SHIFT) /* 0001: Timer 1 break input */
@ -86,25 +86,23 @@
# define COMP_CSR_OUTSEL_T15OCC (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 15 OCREF_CLR input (COMP4 only) */
# define COMP_CSR_OUTSEL_T16CAP1 (10 << COMP_CSR_INMSEL_SHIFT) /* 1010: Timer 16 input capture 1 (COMP6 only) */
# define COMP_CSR_OUTSEL_T3OCC (11 << COMP_CSR_INMSEL_SHIFT) /* 1011: Timer 3 OCREF_CLR input (COMP2,COMP4 only) */
/* Bit 14: Reserved */
#define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */
/* Bits 16-17: Reserved */
#define COMP_CSR_BLANKING_SHIFT (18) /* Bit 18-20: comparator output blanking source */
/* Bit 14: Reserved */
#define COMP_CSR_POL (1 << 15) /* Bit 15: comparator output polarity */
/* Bits 16-17: Reserved */
#define COMP_CSR_BLANKING_SHIFT (18) /* Bit 18-20: comparator output blanking source */
#define COMP_CSR_BLANKING_MASK (7 << COMP_CSR_BLANKING_SHIFT)
# define COMP_CSR_BLANKING_DIS (0 << COMP_CSR_BLANKING_SHIFT) /* 000: No blanking */
# define COMP_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1 OC5 as blanking source (COMP2 only) */
# define COMP_CSR_BLANKING_T3OC4 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM3 OC4 as blanking source (COMP4 only) */
# define COMP_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2 OC3 as blanking source (COMP2 only) */
# define COMP_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3 OC3 as blanking source (COMP2 only) */
# define COMP_CSR_BLANKING_T15OC1 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15 OC1 as blanking source (COMP4 only) */
# define COMP_CSR_BLANKING_T2OC4 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM2 OC4 as blanking source (COMP6 only) */
# define COMP_CSR_BLANKING_T15OC2 (4 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15 OC2 as blanking source (COMP6 only) */
/* Bit 21: Reserved */
#define COMP_CSR_INMSEL_DAC2CH1 (1 << 22) /* Bit 22: used with bits 4-6, DAC2_CH1 output */
/* Bits 23-29: Reserved */
#define COMP_CSR_OUT (1 << 30) /* Bit 30: comparator output */
#define COMP_CSR_LOCK (1 << 31) /* Bit 31: comparator lock */
# define COMP_CSR_BLANKING_DIS (0 << COMP_CSR_BLANKING_SHIFT) /* 000: No blanking */
# define COMP_CSR_BLANKING_T1OC5 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM1 OC5 as blanking source (COMP2 only) */
# define COMP_CSR_BLANKING_T3OC4 (1 << COMP_CSR_BLANKING_SHIFT) /* 001: TIM3 OC4 as blanking source (COMP4 only) */
# define COMP_CSR_BLANKING_T2OC3 (2 << COMP_CSR_BLANKING_SHIFT) /* 010: TIM2 OC3 as blanking source (COMP2 only) */
# define COMP_CSR_BLANKING_T3OC3 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM3 OC3 as blanking source (COMP2 only) */
# define COMP_CSR_BLANKING_T15OC1 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15 OC1 as blanking source (COMP4 only) */
# define COMP_CSR_BLANKING_T2OC4 (3 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM2 OC4 as blanking source (COMP6 only) */
# define COMP_CSR_BLANKING_T15OC2 (4 << COMP_CSR_BLANKING_SHIFT) /* 011: TIM15 OC2 as blanking source (COMP6 only) */
/* Bit 21: Reserved */
#define COMP_CSR_INMSEL_DAC2CH1 (1 << 22) /* Bit 22: used with bits 4-6, DAC2_CH1 output */
/* Bits 23-29: Reserved */
#define COMP_CSR_OUT (1 << 30) /* Bit 30: comparator output */
#define COMP_CSR_LOCK (1 << 31) /* Bit 31: comparator lock */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */

1076
arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h
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File diff suppressed because it is too large Load Diff

52
arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h
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@ -1,4 +1,4 @@
/****************************************************************************************************
/************************************************************************************
* arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,28 +16,28 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OPAMP_H
#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OPAMP_H
/****************************************************************************************************
/************************************************************************************
* Included Files
****************************************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
************************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *****************************************************************/
#define STM32_OPAMP2_CSR_OFFSET 0x003C /* OPAMP2 Control register */
/* Register Addresses *******************************************************************************/
/* Register Addresses ***************************************************************/
#define STM32_OPAMP2_CSR (STM32_OPAMP_BASE+STM32_OPAMP2_CSR_OFFSET)
@ -45,38 +45,38 @@
/* OPAMP control and status register */
#define OPAMP_CSR_OPAMPEN (1 << 0) /* Bit 0: OPAMP enable */
#define OPAMP_CSR_FORCE_VP (1 << 1) /* Bit 1: Force a calibration reference voltage on non-nverting */
/* input and disables external connections */
#define OPAMP_CSR_VPSEL_SHIFT (3) /* Bits 2-3: OPAMP non inverting input selection */
#define OPAMP_CSR_OPAMPEN (1 << 0) /* Bit 0: OPAMP enable */
#define OPAMP_CSR_FORCE_VP (1 << 1) /* Bit 1: Force a calibration reference voltage on non-nverting */
/* input and disables external connections */
#define OPAMP_CSR_VPSEL_SHIFT (3) /* Bits 2-3: OPAMP non inverting input selection */
#define OPAMP_CSR_VPSEL_MASK (3 << OPAMP_CSR_VPSEL_SHIFT)
/* 00: Reserved */
# define OPAMP_CSR_VPSEL_PB14 (1 << OPAMP_CSR_VPSEL_SHIFT) /* 01: PB14 */
# define OPAMP_CSR_VPSEL_PB0 (2 << OPAMP_CSR_VPSEL_SHIFT) /* 10: PB0 */
# define OPAMP_CSR_VPSEL_PA7 (3 << OPAMP_CSR_VPSEL_SHIFT) /* 11: PA7 */
/* Bit 4: Reserved */
#define OPAMP_CSR_VMSEL_SHIFT (5) /* Bits 5-6: OPAMP inverting input selection */
/* Bit 4: Reserved */
#define OPAMP_CSR_VMSEL_SHIFT (5) /* Bits 5-6: OPAMP inverting input selection */
#define OPAMP_CSR_VMSEL_MASK (3 << OPAMP_CSR_VMSEL_SHIFT)
# define OPAMP_CSR_VMSEL_PC5 (0 << OPAMP_CSR_VMSEL_SHIFT) /* 00: PC5 */
# define OPAMP_CSR_VMSEL_PA5 (1 << OPAMP_CSR_VMSEL_SHIFT) /* 01: PA5 */
# define OPAMP_CSR_VMSEL_PGA (2 << OPAMP_CSR_VMSEL_SHIFT) /* 10: Resistor feedback output (PGA mode)*/
# define OPAMP_CSR_VMSEL_FOLLOWER (3 << OPAMP_CSR_VMSEL_SHIFT) /* 11: Follower mode */
#define OPAMP_CSR_TCMEN (1 << 7) /* Bit 7: Timer controlled Mux mode enable */
#define OPAMP_CSR_VMSSEL (1 << 8) /* Bit 8: OPAMP inverting input secondary selection */
#define OPAMP_CSR_VPSSEL_SHIFT (1 << 9) /* Bits 9-10: OPAMP Non inverting input secondary selection */
#define OPAMP_CSR_TCMEN (1 << 7) /* Bit 7: Timer controlled Mux mode enable */
#define OPAMP_CSR_VMSSEL (1 << 8) /* Bit 8: OPAMP inverting input secondary selection */
#define OPAMP_CSR_VPSSEL_SHIFT (1 << 9) /* Bits 9-10: OPAMP Non inverting input secondary selection */
#define OPAMP_CSR_VPSSEL_MASK (3 << OPAMP_CSR_VPSSEL_SHIFT)
/* 00: Reserved */
# define OPAMP_CSR_VPSSEL_PB14 (1 << OPAMP_CSR_VPSSEL_SHIFT) /* 01: PB14 */
# define OPAMP_CSR_VPSSEL_PB0 (2 << OPAMP_CSR_VPSSEL_SHIFT) /* 10: PB0 */
# define OPAMP_CSR_VPSSEL_PA7 (3 << OPAMP_CSR_VPSSEL_SHIFT) /* 11: PA7 */
#define OPAMP_CSR_CALON (1 << 11) /* Bit 11: Calibration mode enable */
#define OPAMP_CSR_CALSEL_SHIFT (12) /* Bits 12-13: Calibration selection */
#define OPAMP_CSR_CALON (1 << 11) /* Bit 11: Calibration mode enable */
#define OPAMP_CSR_CALSEL_SHIFT (12) /* Bits 12-13: Calibration selection */
#define OPAMP_CSR_CALSEL_MASK (3 << OPAMP_CSR_CALSEL_SHIFT)
# define OPAMP_CSR_CALSEL_3P3 (0 << OPAMP_CSR_CALSEL_SHIFT) /* 00 V_REFOPAMP = 3.3% V_DDA */
# define OPAMP_CSR_CALSEL_10 (1 << OPAMP_CSR_CALSEL_SHIFT) /* 01 V_REFOPAMP = 10% V_DDA */
# define OPAMP_CSR_CALSEL_50 (2 << OPAMP_CSR_CALSEL_SHIFT) /* 10 V_REFOPAMP = 50% V_DDA */
# define OPAMP_CSR_CALSEL_90 (3 << OPAMP_CSR_CALSEL_SHIFT) /* 11 V_REFOPAMP = 90% V_DDA */
#define OPAMP_CSR_PGAGAIN_SHIFT (14) /* Bits 14-17: Gain in PGA mode */
#define OPAMP_CSR_PGAGAIN_SHIFT (14) /* Bits 14-17: Gain in PGA mode */
#define OPAMP_CSR_PGAGAIN_MASK (15 << OPAMP_CSR_PGAGAIN_SHIFT)
# define OPAMP_CSR_PGAGAIN_2 (0 << OPAMP_CSR_PGAGAIN_SHIFT) /* 0X00: Non-inverting gain = 2 */
# define OPAMP_CSR_PGAGAIN_4 (1 << OPAMP_CSR_PGAGAIN_SHIFT) /* 0X01: Non-inverting gain = 4 */
@ -90,13 +90,13 @@
# define OPAMP_CSR_PGAGAIN_4VM1 (13 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1101: Non-inverting gain = 4 - VM1*/
# define OPAMP_CSR_PGAGAIN_8VM1 (14 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1110: Non-inverting gain = 8 - VM1*/
# define OPAMP_CSR_PGAGAIN_16VM1 (15 << OPAMP_CSR_PGAGAIN_SHIFT) /* 1111: Non-inverting gain = 16 - VM1*/
#define OPAMP_CSR_USERTRIM (1 << 18) /* Bit 18: User trimming enable */
#define OPAMP_CSR_TRIMOFFSETP_SHIFT (19) /* Bits 19-23: Offset trimming value (PMOS)*/
#define OPAMP_CSR_USERTRIM (1 << 18) /* Bit 18: User trimming enable */
#define OPAMP_CSR_TRIMOFFSETP_SHIFT (19) /* Bits 19-23: Offset trimming value (PMOS)*/
#define OPAMP_CSR_TRIMOFFSETP_MASK (31 << OPAMP_CSR_TRIMOFFSETP_SHIFT)
#define OPAMP_CSR_TRIMOFFSETN_SHIFT (24) /* Bits 24-28: Offset trimming value (NMOS) */
#define OPAMP_CSR_TRIMOFFSETN_SHIFT (24) /* Bits 24-28: Offset trimming value (NMOS) */
#define OPAMP_CSR_TRIMOFFSETN_MASK (31 << OPAMP_CSR_TRIMOFFSETN_SHIFT)
#define OPAMP_CSR_TSTREF (1 << 29) /* Bit 29: Output the internal reference voltage */
#define OPAMP_CSR_OUTCAL (1 << 30) /* Bit 30: OPAMP output status flag */
#define OPAMP_CSR_LOCK (1 << 31) /* Bit 31: OPAMP 2 lock */
#define OPAMP_CSR_TSTREF (1 << 29) /* Bit 29: Output the internal reference voltage */
#define OPAMP_CSR_OUTCAL (1 << 30) /* Bit 30: OPAMP output status flag */
#define OPAMP_CSR_LOCK (1 << 31) /* Bit 31: OPAMP 2 lock */
#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OPAMP_H */

29
arch/arm/src/stm32/stm32_comp.c
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@ -38,6 +38,7 @@
#include "stm32_comp.h"
/* Some COMP peripheral must be enabled */
/* Up to 7 comparators in STM32F3 Series */
#if defined(CONFIG_STM32_COMP1) || defined(CONFIG_STM32_COMP2) || \
@ -183,7 +184,8 @@ static int stm32_complock(FAR struct stm32_comp_s *priv, bool lock);
static void comp_shutdown(FAR struct comp_dev_s *dev);
static int comp_setup(FAR struct comp_dev_s *dev);
static int comp_read(FAR struct comp_dev_s *dev);
static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg);
static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd,
unsigned long arg);
/* Initialization */
@ -657,30 +659,36 @@ static int stm32_compconfig(FAR struct stm32_comp_s *priv)
/* COMP2_INM can be PA2 or PA4 */
stm32_configgpio(GPIO_COMP2_INM);
regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ? COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4);
regval |= (GPIO_COMP2_INM == GPIO_COMP2_INM_1 ?
COMP_CSR_INMSEL_PA2 : COMP_CSR_INMSEL_PA4);
break;
}
#endif
#ifdef CONFIG_STM32_COMP4
case 4:
{
/* COMP4_INM can be PB2 or PA4 */
stm32_configgpio(GPIO_COMP4_INM);
regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ? COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4);
regval |= (GPIO_COMP4_INM == GPIO_COMP4_INM_1 ?
COMP_CSR_INMSEL_PB2 : COMP_CSR_INMSEL_PA4);
break;
}
#endif
#ifdef CONFIG_STM32_COMP6
case 6:
{
/* COMP6_INM can be PB15 or PA4 */
stm32_configgpio(GPIO_COMP6_INM);
regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ? COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4);
regval |= (GPIO_COMP6_INM == GPIO_COMP6_INM_1 ?
COMP_CSR_INMSEL_PB15 : COMP_CSR_INMSEL_PA4);
break;
}
#endif
default :
return -EINVAL;
}
@ -892,7 +900,8 @@ static int stm32_compenable(FAR struct stm32_comp_s *priv, bool enable)
static int comp_setup(FAR struct comp_dev_s *dev)
{
#warning "Missing logic"
return OK;
return OK;
}
/****************************************************************************
@ -984,9 +993,9 @@ static int comp_ioctl(FAR struct comp_dev_s *dev, int cmd, unsigned long arg)
*
****************************************************************************/
FAR struct comp_dev_s* stm32_compinitialize(int intf)
FAR struct comp_dev_s *stm32_compinitialize(int intf)
{
FAR struct comp_dev_s *dev;
FAR struct comp_dev_s *dev;
FAR struct stm32_comp_s *comp;
int ret;
@ -1061,7 +1070,9 @@ FAR struct comp_dev_s* stm32_compinitialize(int intf)
}
#endif /* CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F33XX ||
* CONFIG_STM32_STM32F37XX*/
* CONFIG_STM32_STM32F37XX
*/
#endif /* CONFIG_STM32_COMP2 || CONFIG_STM32_COMP4 ||
* CONFIG_STM32_COMP6 */
* CONFIG_STM32_COMP6
*/

36
arch/arm/src/stm32/stm32_comp.h
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@ -172,25 +172,25 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_compinitialize
*
* Description:
* Initialize the COMP.
*
* Input Parameters:
* intf - The COMP interface number.
*
* Returned Value:
* Valid COMP device structure reference on success; a NULL on failure.
*
* Assumptions:
* 1. Clock to the COMP block has enabled,
* 2. Board-specific logic has already configured
*
****************************************************************************/
/************************************************************************************
* Name: stm32_compinitialize
*
* Description:
* Initialize the COMP.
*
* Input Parameters:
* intf - The COMP interface number.
*
* Returned Value:
* Valid COMP device structure reference on success; a NULL on failure.
*
* Assumptions:
* 1. Clock to the COMP block has enabled,
* 2. Board-specific logic has already configured
*
************************************************************************************/
FAR struct comp_dev_s* stm32_compinitialize(int intf);
FAR struct comp_dev_s *stm32_compinitialize(int intf);
#undef EXTERN
#ifdef __cplusplus

89
arch/arm/src/stm32/stm32_hrtim.h
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@ -249,23 +249,23 @@
enum stm32_hrtim_tim_e
{
HRTIM_TIMER_MASTER = (1<<0),
HRTIM_TIMER_MASTER = (1 << 0),
#ifdef CONFIG_STM32_HRTIM_TIMA
HRTIM_TIMER_TIMA = (1<<1),
HRTIM_TIMER_TIMA = (1 << 1),
#endif
#ifdef CONFIG_STM32_HRTIM_TIMB
HRTIM_TIMER_TIMB = (1<<2),
HRTIM_TIMER_TIMB = (1 << 2),
#endif
#ifdef CONFIG_STM32_HRTIM_TIMC
HRTIM_TIMER_TIMC = (1<<3),
HRTIM_TIMER_TIMC = (1 << 3),
#endif
#ifdef CONFIG_STM32_HRTIM_TIMD
HRTIM_TIMER_TIMD = (1<<4),
HRTIM_TIMER_TIMD = (1 << 4),
#endif
#ifdef CONFIG_STM32_HRTIM_TIME
HRTIM_TIMER_TIME = (1<<5),
HRTIM_TIMER_TIME = (1 << 5),
#endif
HRTIM_TIMER_COMMON = (1<<6),
HRTIM_TIMER_COMMON = (1 << 6),
HRTIM_TIMERS_MASK = 0x3f
};
@ -354,52 +354,52 @@ enum stm32_hrtim_tim_rst_e
{
/* Timer owns events */
HRTIM_RST_UPDT = (1<<1),
HRTIM_RST_CMP4 = (1<<2),
HRTIM_RST_CMP2 = (1<<3),
HRTIM_RST_UPDT = (1 << 1),
HRTIM_RST_CMP4 = (1 << 2),
HRTIM_RST_CMP2 = (1 << 3),
/* Master Timer Events */
HRTIM_RST_MSTPER = (1<<4),
HRTIM_RST_MSTCMP1 = (1<<5),
HRTIM_RST_MSTCMP2 = (1<<6),
HRTIM_RST_MSTCMP3 = (1<<7),
HRTIM_RST_MSTCMP4 = (1<<8),
HRTIM_RST_MSTPER = (1 << 4),
HRTIM_RST_MSTCMP1 = (1 << 5),
HRTIM_RST_MSTCMP2 = (1 << 6),
HRTIM_RST_MSTCMP3 = (1 << 7),
HRTIM_RST_MSTCMP4 = (1 << 8),
/* External Events */
HRTIM_RST_EXTEVNT1 = (1<<9),
HRTIM_RST_EXTEVNT2 = (1<<10),
HRTIM_RST_EXTEVNT3 = (1<<11),
HRTIM_RST_EXTEVNT4 = (1<<12),
HRTIM_RST_EXTEVNT5 = (1<<13),
HRTIM_RST_EXTEVNT6 = (1<<14),
HRTIM_RST_EXTEVNT7 = (1<<15),
HRTIM_RST_EXTEVNT8 = (1<<16),
HRTIM_RST_EXTEVNT9 = (1<<17),
HRTIM_RST_EXTEVNT10 = (1<<18),
HRTIM_RST_EXTEVNT1 = (1 << 9),
HRTIM_RST_EXTEVNT2 = (1 << 10),
HRTIM_RST_EXTEVNT3 = (1 << 11),
HRTIM_RST_EXTEVNT4 = (1 << 12),
HRTIM_RST_EXTEVNT5 = (1 << 13),
HRTIM_RST_EXTEVNT6 = (1 << 14),
HRTIM_RST_EXTEVNT7 = (1 << 15),
HRTIM_RST_EXTEVNT8 = (1 << 16),
HRTIM_RST_EXTEVNT9 = (1 << 17),
HRTIM_RST_EXTEVNT10 = (1 << 18),
/* TimerX events */
HRTIM_RST_TACMP1 = (1<<19),
HRTIM_RST_TACMP2 = (1<<20),
HRTIM_RST_TACMP4 = (1<<21),
HRTIM_RST_TBCMP1 = (1<<22),
HRTIM_RST_TBCMP2 = (1<<23),
HRTIM_RST_TBCMP4 = (1<<24),
HRTIM_RST_TCCMP1 = (1<<25),
HRTIM_RST_TCCMP2 = (1<<26),
HRTIM_RST_TCCMP4 = (1<<27),
HRTIM_RST_TDCMP1 = (1<<28),
HRTIM_RST_TDCMP2 = (1<<29),
HRTIM_RST_TDCMP4 = (1<<30),
HRTIM_RST_TECMP1 = (1<<31),
HRTIM_RST_TACMP1 = (1 << 19),
HRTIM_RST_TACMP2 = (1 << 20),
HRTIM_RST_TACMP4 = (1 << 21),
HRTIM_RST_TBCMP1 = (1 << 22),
HRTIM_RST_TBCMP2 = (1 << 23),
HRTIM_RST_TBCMP4 = (1 << 24),
HRTIM_RST_TCCMP1 = (1 << 25),
HRTIM_RST_TCCMP2 = (1 << 26),
HRTIM_RST_TCCMP4 = (1 << 27),
HRTIM_RST_TDCMP1 = (1 << 28),
HRTIM_RST_TDCMP2 = (1 << 29),
HRTIM_RST_TDCMP4 = (1 << 30),
HRTIM_RST_TECMP1 = (1 << 31),
};
/* This definitions does not fit to the above 32 bit enum */
#define HRTIM_RST_TECMP2 (1ull<<32)
#define HRTIM_RST_TECMP4 (1ull<<33)
#define HRTIM_RST_TECMP2 (1ull << 32)
#define HRTIM_RST_TECMP4 (1ull << 33)
/* HRTIM Timer X prescaler */
@ -958,6 +958,7 @@ enum stm32_hrtim_burst_triggers_e
};
/* HRTIM Capture triggers */
enum stm32_hrtim_capture_index_e
{
HRTIM_CAPTURE1 = 0,
@ -1093,7 +1094,7 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
/************************************************************************************
* Name: stm32_hrtiminitialize
*
* Description:
@ -1109,13 +1110,13 @@ extern "C"
* 1. Clock to the HRTIM block has enabled,
* 2. Board-specific logic has already configured
*
****************************************************************************/
************************************************************************************/
FAR struct hrtim_dev_s *stm32_hrtiminitialize(void);
/****************************************************************************
/************************************************************************************
* Name: hrtim_register
****************************************************************************/
************************************************************************************/
#ifndef CONFIG_STM32_HRTIM_DISABLE_CHARDRV
int hrtim_register(FAR const char *path, FAR struct hrtim_dev_s *dev);

27
arch/arm/src/stm32/stm32_opamp.c
View File

@ -42,6 +42,7 @@
#ifdef CONFIG_STM32_OPAMP
/* Some OPAMP peripheral must be enabled */
/* Up to 4 OPAMPs in STM32F3 Series */
#if defined(CONFIG_STM32_OPAMP1) || defined(CONFIG_STM32_OPAMP2) || \
@ -143,7 +144,7 @@
# endif
#endif
/* Some assertions *******************************************************/
/* Some assertions *********************************************************/
/* Check OPAMPs inputs selection */
@ -212,7 +213,9 @@
# endif
#endif
/* When OPAMP MUX enabled, make sure that secondary selection inputs are configured */
/* When OPAMP MUX enabled, make sure that secondary selection inputs are
* configured
*/
#ifdef CONFIG_STM32_OPAMP1
# if (OPAMP1_MUX == OPAMP_MUX_ENABLE)
@ -276,8 +279,8 @@ struct stm32_opamp_s
static inline void opamp_modify_csr(FAR struct stm32_opamp_s *priv,
uint32_t clearbits, uint32_t setbits);
static inline uint32_t opamp_getreg_csr(FAR struct stm32_opamp_s* priv);
static inline void opamp_putreg_csr(FAR struct stm32_opamp_s* priv,
static inline uint32_t opamp_getreg_csr(FAR struct stm32_opamp_s *priv);
static inline void opamp_putreg_csr(FAR struct stm32_opamp_s *priv,
uint32_t value);
static bool stm32_opamplock_get(FAR struct stm32_opamp_s *priv);
static int stm32_opamplock(FAR struct stm32_opamp_s *priv, bool lock);
@ -295,7 +298,8 @@ static int stm32_opampcalibrate(FAR struct stm32_opamp_s *priv);
static void opamp_shutdown(FAR struct opamp_dev_s *dev);
static int opamp_setup(FAR struct opamp_dev_s *dev);
static int opamp_ioctl(FAR struct opamp_dev_s *dev, int cmd, unsigned long arg);
static int opamp_ioctl(FAR struct opamp_dev_s *dev, int cmd,
unsigned long arg);
/****************************************************************************
* Private Data
@ -1107,8 +1111,8 @@ static int stm32_opampconfig(FAR struct stm32_opamp_s *priv)
stm32_opampenable(priv, true);
/* TODO: OPAMP user calibration */
/* stm32_opampcalibrate(priv); */
/* stm32_opampcalibrate(priv); */
/* Lock OPAMP if needed */
@ -1243,13 +1247,13 @@ static int stm32_opampgain_set(FAR struct stm32_opamp_s *priv, uint8_t gain)
priv->gain = gain;
return OK;
}
#if 0
static int stm32_opampcalibrate(FAR struct stm32_opamp_s *priv)
{
#warning "Missing logic"
return OK;
}
#endif
@ -1258,8 +1262,8 @@ static int stm32_opampcalibrate(FAR struct stm32_opamp_s *priv)
* Name: opamp_shutdown
*
* Description:
* Disable the OPAMP. This method is called when the OPAMP device is closed.
* This method reverses the operation the setup method.
* Disable the OPAMP. This method is called when the OPAMP device is
* closed. This method reverses the operation the setup method.
* Works only if OPAMP device is not locked.
*
* Input Parameters:
@ -1310,7 +1314,8 @@ static int opamp_setup(FAR struct opamp_dev_s *dev)
*
****************************************************************************/
static int opamp_ioctl(FAR struct opamp_dev_s* dev, int cmd, unsigned long arg)
static int opamp_ioctl(FAR struct opamp_dev_s *dev, int cmd,
unsigned long arg)
{
#warning "Missing logic"
return -ENOTTY;
@ -1338,7 +1343,7 @@ static int opamp_ioctl(FAR struct opamp_dev_s* dev, int cmd, unsigned long arg)
*
****************************************************************************/
FAR struct opamp_dev_s* stm32_opampinitialize(int intf)
FAR struct opamp_dev_s *stm32_opampinitialize(int intf)
{
FAR struct opamp_dev_s *dev;
FAR struct stm32_opamp_s *opamp;

37
arch/arm/src/stm32/stm32_opamp.h
View File

@ -121,6 +121,7 @@ enum stm32_opamp2_vpsel_e
{
#ifndef CONFIG_STM32_STM32F33XX
/* TODO: STM32F303xB/C and STM32F358C devices only */
OPAMP2_VPSEL_PD14,
#endif
OPAMP2_VPSEL_PB14,
@ -186,25 +187,25 @@ extern "C"
#define EXTERN extern
#endif
/****************************************************************************
* Name: stm32_opampinitialize
*
* Description:
* Initialize the OPAMP.
*
* Input Parameters:
* intf - The OPAMP interface number.
*
* Returned Value:
* Valid OPAMP device structure reference on success; a NULL on failure.
*
* Assumptions:
* 1. Clock to the OPAMP block has enabled,
* 2. Board-specific logic has already configured
*
****************************************************************************/
/************************************************************************************
* Name: stm32_opampinitialize
*
* Description:
* Initialize the OPAMP.
*
* Input Parameters:
* intf - The OPAMP interface number.
*
* Returned Value:
* Valid OPAMP device structure reference on success; a NULL on failure.
*
* Assumptions:
* 1. Clock to the OPAMP block has enabled,
* 2. Board-specific logic has already configured
*
************************************************************************************/
FAR struct opamp_dev_s* stm32_opampinitialize(int intf);
FAR struct opamp_dev_s *stm32_opampinitialize(int intf);
#undef EXTERN
#ifdef __cplusplus

23
arch/arm/src/stm32h7/hardware/stm32_dmamux.h
View File

@ -54,18 +54,18 @@
#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13)
#define STM32_DMAMUX_C14CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(14)
#define STM32_DMAMUX_C15CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(15)
/* 0x040-0x07C: Reserved */
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */
/* 0x088-0x0FC: Reserved */
/* 0x040-0x07C: Reserved */
#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX12 request line multiplexer interrupt channel status register */
#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX12 request line multiplexer interrupt clear flag register */
/* 0x088-0x0FC: Reserved */
#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX12 request generator channel x configuration register */
#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0)
#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1)
#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2)
#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3)
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */
/* 0x148-0x3FC: Reserved */
#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX12 request generator interrupt status register */
#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX12 request generator interrupt clear flag register */
/* 0x148-0x3FC: Reserved */
/* Register Addresses ***************************************************************/
@ -155,8 +155,9 @@
/* DMAMUX12 request generator channel x configuration register */
#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction */
/* WARNING: different length for DMAMUX1 and DMAMUX2 !*/
#define DMAMUX_RGCR_SIGID_SHIFT (0) /* Bits 0-4: Signal identifiaction
* WARNING: different length for DMAMUX1 and DMAMUX2 !
*/
#define DMAMUX_RGCR_SIGID_MASK (0x1f << DMAMUX_RGCR_SIGID_SHIFT)
#define DMAMUX_RGCR_OIE (8) /* Bit 8: Trigger overrun interrupt enable */
#define DMAMUX_RGCR_GE (16) /* Bit 16: DMA request generator channel X enable*/
@ -185,6 +186,10 @@
#define DMAMAP_CONTROLLER(m) ((m) >> 8 & 0x07)
#define DMAMAP_REQUEST(m) ((m) >> 0 & 0xff)
/************************************************************************************
* Included Files
************************************************************************************/
/* Import DMAMUX map */
#if defined(CONFIG_STM32H7_STM32H7X3XX)

68
arch/arm/src/stm32h7/hardware/stm32_mdma.h
View File

@ -494,7 +494,9 @@
#define MDMA_CXISR_GIF(x) (1 << x)
/* MDMA channel x interrupt/status register and channel x interrupt flag clear register */
/* MDMA channel x interrupt/status register and channel x interrupt flag clear
* register
*/
#define MDMA_INT_TEIF (1 << 0) /* Bit 0: Channel X transfer error flag */
#define BDMA_INT_CTCIF (1 << 1) /* Bit 1: Channel X transfer complete flag */
@ -515,60 +517,60 @@
/* MDMA channel x control register */
#define MDMA_CCR_EN (0) /* Bit 0: Channel enable / flag channel ready */
#define MDMA_CCR_TEIE (1) /* Bit 1: Transfer error interrupt enable */
#define MDMA_CCR_CTCIE (2) /* Bit 2: Channel transfer complete interrupt enable */
#define MDMA_CCR_BRTIE (3) /* Bit 3: Block repeat transfer interrupt enable */
#define MDMA_CCR_BTIE (4) /* Bit 4: Block transfer interrupt enable */
#define MDMA_CCR_TCIE (5) /* Bit 5: Buffer transfer complete interrupt enable */
#define MDMA_CCR_PL_SHIFT (6) /* Bis 6-7: Priority level */
#define MDMA_CCR_EN (0) /* Bit 0: Channel enable / flag channel ready */
#define MDMA_CCR_TEIE (1) /* Bit 1: Transfer error interrupt enable */
#define MDMA_CCR_CTCIE (2) /* Bit 2: Channel transfer complete interrupt enable */
#define MDMA_CCR_BRTIE (3) /* Bit 3: Block repeat transfer interrupt enable */
#define MDMA_CCR_BTIE (4) /* Bit 4: Block transfer interrupt enable */
#define MDMA_CCR_TCIE (5) /* Bit 5: Buffer transfer complete interrupt enable */
#define MDMA_CCR_PL_SHIFT (6) /* Bis 6-7: Priority level */
#define MDMA_CCR_PL_MASK (3 << MDMA_CCR_PL_SHIFT)
# define MDMA_CCR_PRILO (0 << MDMA_CCR_PL_SHIFT) /* 00: Low */
# define MDMA_CCR_PRIMED (1 << MDMA_CCR_PL_SHIFT) /* 01: Medium */
# define MDMA_CCR_PRIHI (2 << MDMA_CCR_PL_SHIFT) /* 10: High */
# define MDMA_CCR_PRIVERYHI (3 << MDMA_CCR_PL_SHIFT) /* 11: Very high */
#define MDMA_CCR_BEX (12) /* Bit 12: Byte endianness exchange */
#define MDMA_CCR_HEX (13) /* Bit 13: Half word endianness exchange */
#define MDMA_CCR_WEX (14) /* Bit 14: Word endianness exchange */
#define MDMA_CCR_SWRQ (16) /* Bit 16: Software request */
#define MDMA_CCR_BEX (12) /* Bit 12: Byte endianness exchange */
#define MDMA_CCR_HEX (13) /* Bit 13: Half word endianness exchange */
#define MDMA_CCR_WEX (14) /* Bit 14: Word endianness exchange */
#define MDMA_CCR_SWRQ (16) /* Bit 16: Software request */
/* MDMA channel x transfer configuration register */
#define MDMA_CTCR_SINC_SHIFT (0) /* Bits 0-1: Source increment mode */
#define MDMA_CTCR_SINC_SHIFT (0) /* Bits 0-1: Source increment mode */
#define MDMA_CTCR_SINC_MASK (3 << MDMA_CTCR_SINC_SHIFT)
# define MDMA_CTCR_SINC_FIXED (0 << MDMA_CTCR_SINC_SHIFT) /* 00: */
# define MDMA_CTCR_SINC_INCR (2 << MDMA_CTCR_SINC_SHIFT) /* 10: */
# define MDMA_CTCR_SINC_DECR (3 << MDMA_CTCR_SINC_SHIFT) /* 11: */
#define MDMA_CTCR_DINC_SHIFT (2) /* Bits 2-3: Destination increment mode */
#define MDMA_CTCR_DINC_SHIFT (2) /* Bits 2-3: Destination increment mode */
#define MDMA_CTCR_DINC_MASK (3 << MDMA_CTCR_DINC_SHIFT)
# define MDMA_CTCR_DINC_FIXED (0 << MDMA_CTCR_DINC_SHIFT) /* 00: */
# define MDMA_CTCR_DINC_INCR (2 << MDMA_CTCR_DINC_SHIFT) /* 10: */
# define MDMA_CTCR_DINC_DECR (3 << MDMA_CTCR_DINC_SHIFT) /* 11: */
#define MDMA_CTCR_SSIZE_SHIFT (4) /* Bits 4-5: Source data size */
#define MDMA_CTCR_SSIZE_SHIFT (4) /* Bits 4-5: Source data size */
#define MDMA_CTCR_SSIZE_MASK (3 << MDMA_CTCR_SSIZE_SHIFT)
# define MDMA_CTCR_SSIZE_8BITS (0 << MDMA_CTCR_SSIZE_SHIFT) /* 00: */
# define MDMA_CTCR_SSIZE_16BITS (1 << MDMA_CTCR_SSIZE_SHIFT) /* 01: */
# define MDMA_CTCR_SSIZE_32BITS (2 << MDMA_CTCR_SSIZE_SHIFT) /* 10: */
# define MDMA_CTCR_SSIZE_64BITS (3 << MDMA_CTCR_SSIZE_SHIFT) /* 11: */
#define MDMA_CTCR_DSIZE_SHIFT (6) /* Bits 6-7: Destination data size */
#define MDMA_CTCR_DSIZE_SHIFT (6) /* Bits 6-7: Destination data size */
#define MDMA_CTCR_DSIZE_MASK (3 << MDMA_CTCR_DSIZE_SHIFT)
# define MDMA_CTCR_DSIZE_8BITS (0 << MDMA_CTCR_DSIZE_SHIFT) /* 00: */
# define MDMA_CTCR_DSIZE_16BITS (1 << MDMA_CTCR_DSIZE_SHIFT) /* 01: */
# define MDMA_CTCR_DSIZE_32BITS (2 << MDMA_CTCR_DSIZE_SHIFT) /* 10: */
# define MDMA_CTCR_DSIZE_64BITS (3 << MDMA_CTCR_DSIZE_SHIFT) /* 11: */
#define MDMA_CTCR_SINCOS_SHIFT (8) /* Bits 8-9: Source increment offset size */
#define MDMA_CTCR_SINCOS_SHIFT (8) /* Bits 8-9: Source increment offset size */
#define MDMA_CTCR_SINCOS_MASK (3 << MDMA_CTCR_SINCOS_SHIFT)
# define MDMA_CTCR_SINCOS_8BITS (0 << MDMA_CTCR_SINCOS_SHIFT) /* 00: */
# define MDMA_CTCR_SINCOS_16BITS (1 << MDMA_CTCR_SINCOS_SHIFT) /* 01: */
# define MDMA_CTCR_SINCOS_32BITS (2 << MDMA_CTCR_SINCOS_SHIFT) /* 10: */
# define MDMA_CTCR_SINCOS_64BITS (3 << MDMA_CTCR_SINCOS_SHIFT) /* 11: */
#define MDMA_CTCR_DINCOS_SHIFT (10) /* Bits 10-11: Destination increment offset size */
#define MDMA_CTCR_DINCOS_SHIFT (10) /* Bits 10-11: Destination increment offset size */
#define MDMA_CTCR_DINCOS_MASK (7 << MDMA_CTCR_DINCOS_SHIFT)
# define MDMA_CTCR_DINCOS_8BITS (0 << MDMA_CTCR_DINCOS_SHIFT) /* 00: */
# define MDMA_CTCR_DINCOS_16BITS (1 << MDMA_CTCR_DINCOS_SHIFT) /* 01: */
# define MDMA_CTCR_DINCOS_32BITS (2 << MDMA_CTCR_DINCOS_SHIFT) /* 10: */
# define MDMA_CTCR_DINCOS_64BITS (3 << MDMA_CTCR_DINCOS_SHIFT) /* 11: */
#define MDMA_CTCR_SBURST_SHIFT (12) /* Bits 12-14: Source burst transfer configuration */
#define MDMA_CTCR_SBURST_SHIFT (12) /* Bits 12-14: Source burst transfer configuration */
#define MDMA_CTCR_SBURST_MASK (7 << MDMA_CTCR_SBURST_SHIFT)
# define MDMA_CTCR_SBURST_1 (0 << MDMA_CTCR_SBURST_SHIFT) /* 000: */
# define MDMA_CTCR_SBURST_2 (1 << MDMA_CTCR_SBURST_SHIFT) /* 001: */
@ -578,7 +580,7 @@
# define MDMA_CTCR_SBURST_32 (5 << MDMA_CTCR_SBURST_SHIFT) /* 101: */
# define MDMA_CTCR_SBURST_64 (6 << MDMA_CTCR_SBURST_SHIFT) /* 110: */
# define MDMA_CTCR_SBURST_128 (7 << MDMA_CTCR_SBURST_SHIFT) /* 111: */
#define MDMA_CTCR_DBURST_SHIFT (15) /* Bits 15-16: Destination burst transfer configuration */
#define MDMA_CTCR_DBURST_SHIFT (15) /* Bits 15-16: Destination burst transfer configuration */
#define MDMA_CTCR_DBURST_MASK (7 << MDMA_CTCR_DBURST_SHIFT)
# define MDMA_CTCR_DBURST_1 (0 << MDMA_CTCR_DBURST_SHIFT) /* 000: */
# define MDMA_CTCR_DBURST_2 (1 << MDMA_CTCR_DBURST_SHIFT) /* 001: */
@ -588,23 +590,23 @@
# define MDMA_CTCR_DBURST_32 (5 << MDMA_CTCR_DBURST_SHIFT) /* 101: */
# define MDMA_CTCR_DBURST_64 (6 << MDMA_CTCR_DBURST_SHIFT) /* 110: */
# define MDMA_CTCR_DBURST_128 (7 << MDMA_CTCR_DBURST_SHIFT) /* 111: */
#define MDMA_CTCR_TLEN_SHIFT (18) /* Bits 18-24: Buffer transfer length - 1 */
#define MDMA_CTCR_TLEN_SHIFT (18) /* Bits 18-24: Buffer transfer length - 1 */
#define MDMA_CTCR_TLEN_MASK (0x7f << MDMA_CTCR_TLEN_SHIFT)
# define MDMA_CTCR_TLEN(len) (((len-1) << MDMA_CTCR_TLEN_SHIFT) & MDMA_CTCR_TLEN_MASK)
#define MDMA_CTCR_PKE (25) /* Bit 25: Pack enable */
#define MDMA_CTCR_PAM_SHIFT (26) /* Bits 26-27: Padding/alignment mode */
#define MDMA_CTCR_PKE (25) /* Bit 25: Pack enable */
#define MDMA_CTCR_PAM_SHIFT (26) /* Bits 26-27: Padding/alignment mode */
#define MDMA_CTCR_PAM_MASK (3 << MDMA_CTCR_PAM_SHIFT)
# define MDMA_CTCR_PAM_RIGHT (0 << MDMA_CTCR_PAM_SHIFT) /* 00: */
# define MDMA_CTCR_PAM_SINRIGHT (1 << MDMA_CTCR_PAM_SHIFT) /* 01: */
# define MDMA_CTCR_PAM_LEFT (2 << MDMA_CTCR_PAM_SHIFT) /* 10: */
#define MDMA_CTCR_TRGM_SHIFT (28) /* Bits 28-29: Trigger mode */
# define MDMA_CTCR_PAM_RIGHT (0 << MDMA_CTCR_PAM_SHIFT) /* 00: */
# define MDMA_CTCR_PAM_SINRIGHT (1 << MDMA_CTCR_PAM_SHIFT) /* 01: */
# define MDMA_CTCR_PAM_LEFT (2 << MDMA_CTCR_PAM_SHIFT) /* 10: */
#define MDMA_CTCR_TRGM_SHIFT (28) /* Bits 28-29: Trigger mode */
#define MDMA_CTCR_TRGM_MASK (3 << MDMA_CTCR_TRGM_SHIFT)
# define MDMA_CTCR_TRGM_BUFFER (0 << MDMA_CTCR_TRGM_SHIFT) /* 00: */
# define MDMA_CTCR_TRGM_BLOCK (1 << MDMA_CTCR_TRGM_SHIFT) /* 01: */
# define MDMA_CTCR_TRGM_RBLOCK (2 << MDMA_CTCR_TRGM_SHIFT) /* 10: */
# define MDMA_CTCR_TRGM_DATA (3 << MDMA_CTCR_TRGM_SHIFT) /* 11: */
#define MDMA_CTCR_SWRM (30) /* Bit 30: Software request mode */
#define MDMA_CTCR_BWM (31) /* Bit 31: Bufferable write mode */
# define MDMA_CTCR_TRGM_BUFFER (0 << MDMA_CTCR_TRGM_SHIFT) /* 00: */
# define MDMA_CTCR_TRGM_BLOCK (1 << MDMA_CTCR_TRGM_SHIFT) /* 01: */
# define MDMA_CTCR_TRGM_RBLOCK (2 << MDMA_CTCR_TRGM_SHIFT) /* 10: */
# define MDMA_CTCR_TRGM_DATA (3 << MDMA_CTCR_TRGM_SHIFT) /* 11: */
#define MDMA_CTCR_SWRM (30) /* Bit 30: Software request mode */
#define MDMA_CTCR_BWM (31) /* Bit 31: Bufferable write mode */
/* MDMA channel x block number of data register */

370
arch/arm/src/stm32h7/hardware/stm32_otg.h
View File

@ -25,9 +25,11 @@
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* General definitions */
#define OTG_EPTYPE_CTRL (0) /* Control */
@ -41,7 +43,8 @@
#define OTG_PID_MDATA (3) /* Non-control */
#define OTG_PID_SETUP (3) /* Control */
/* Register Offsets ****************************************************************/
/* Register Offsets *****************************************************************/
/* Core global control and status registers */
#define STM32_OTG_GOTGCTL_OFFSET 0x0000 /* Control and status register */
@ -133,7 +136,7 @@
#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
/* Register Addresses **************************************************************/
/* Register Addresses ***************************************************************/
#define STM32_OTG_GOTGCTL (STM32_OTG_BASE+STM32_OTG_GOTGCTL_OFFSET)
#define STM32_OTG_GOTGINT (STM32_OTG_BASE+STM32_OTG_GOTGINT_OFFSET)
@ -214,7 +217,8 @@
#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n))
#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n))
/* Register Bitfield Definitions ***************************************************/
/* Register Bitfield Definitions ****************************************************/
/* Core global control and status registers */
/* Control and status register */
@ -241,6 +245,7 @@
/* Bits 21-31: Reserved */
/* Interrupt register */
/* Bits 1-0 Reserved */
#define OTG_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */
/* Bits 3-7: Reserved */
@ -263,6 +268,7 @@
#define OTG_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */
#define OTG_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */
/* Bits 20-31: Reserved */
/* USB configuration register */
#define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */
@ -290,23 +296,24 @@
#define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */
#define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */
/* Bit 31: Reserved */
/* Reset register */
#define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */
#define OTG_GRSTCTL_PSRST (1 << 1) /* Bit 1: Partial soft reset */
/* Bits 2-3 Reserved */
#define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */
#define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */
#define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */
#define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */
#define OTG_GRSTCTL_PSRST (1 << 1) /* Bit 1: Partial soft reset */
/* Bits 2-3 Reserved */
#define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */
#define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */
#define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */
#define OTG_GRSTCTL_TXFNUM_MASK (31 << OTG_GRSTCTL_TXFNUM_SHIFT)
# define OTG_GRSTCTL_TXFNUM_HNONPER (0 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */
# define OTG_GRSTCTL_TXFNUM_HPER (1 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */
# define OTG_GRSTCTL_TXFNUM_HALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/
# define OTG_GRSTCTL_TXFNUM_D(n) ((n) << OTG_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */
# define OTG_GRSTCTL_TXFNUM_DALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/
/* Bits 11-29: Reserved */
#define OTG_GRSTCTL_DMAREQ (1 << 30) /* Bit 30: DMA request signal enabled */
#define OTG_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */
/* Bits 11-29: Reserved */
#define OTG_GRSTCTL_DMAREQ (1 << 30) /* Bit 30: DMA request signal enabled */
#define OTG_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */
/* Core interrupt and Interrupt mask registers */
@ -347,48 +354,48 @@
/* Receive status debug read/OTG status read and pop registers (host mode) */
#define OTG_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */
#define OTG_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */
#define OTG_GRXSTSH_CHNUM_MASK (15 << OTG_GRXSTSH_CHNUM_SHIFT)
#define OTG_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTG_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTG_GRXSTSH_BCNT_MASK (0x7ff << OTG_GRXSTSH_BCNT_SHIFT)
#define OTG_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTG_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTG_GRXSTSH_DPID_MASK (3 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_DATA0 (0 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_DATA2 (1 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_DATA1 (2 << OTG_GRXSTSH_DPID_SHIFT)
# define OTG_GRXSTSH_DPID_MDATA (3 << OTG_GRXSTSH_DPID_SHIFT)
#define OTG_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTG_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTG_GRXSTSH_PKTSTS_MASK (15 << OTG_GRXSTSH_PKTSTS_SHIFT)
# define OTG_GRXSTSH_PKTSTS_INRECVD (2 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */
# define OTG_GRXSTSH_PKTSTS_INDONE (3 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */
# define OTG_GRXSTSH_PKTSTS_DTOGERR (5 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */
# define OTG_GRXSTSH_PKTSTS_HALTED (7 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */
/* Bits 21-31: Reserved */
/* Bits 21-31: Reserved */
/* Receive status debug read/OTG status read and pop registers (device mode) */
#define OTG_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
#define OTG_GRXSTSD_EPNUM_MASK (15 << OTG_GRXSTSD_EPNUM_SHIFT)
#define OTG_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTG_GRXSTSD_BCNT_MASK (0x7ff << OTG_GRXSTSD_BCNT_SHIFT)
#define OTG_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTG_GRXSTSD_DPID_MASK (3 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA0 (0 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA2 (1 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA1 (2 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_MDATA (3 << OTG_GRXSTSD_DPID_SHIFT)
#define OTG_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTG_GRXSTSD_PKTSTS_MASK (15 << OTG_GRXSTSD_PKTSTS_SHIFT)
#define OTG_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */
#define OTG_GRXSTSD_EPNUM_MASK (15 << OTG_GRXSTSD_EPNUM_SHIFT)
#define OTG_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */
#define OTG_GRXSTSD_BCNT_MASK (0x7ff << OTG_GRXSTSD_BCNT_SHIFT)
#define OTG_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */
#define OTG_GRXSTSD_DPID_MASK (3 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA0 (0 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA2 (1 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_DATA1 (2 << OTG_GRXSTSD_DPID_SHIFT)
# define OTG_GRXSTSD_DPID_MDATA (3 << OTG_GRXSTSD_DPID_SHIFT)
#define OTG_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */
#define OTG_GRXSTSD_PKTSTS_MASK (15 << OTG_GRXSTSD_PKTSTS_SHIFT)
# define OTG_GRXSTSD_PKTSTS_OUTNAK (1 << OTG_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */
# define OTG_GRXSTSD_PKTSTS_OUTRECVD (2 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */
# define OTG_GRXSTSD_PKTSTS_OUTDONE (3 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */
# define OTG_GRXSTSD_PKTSTS_SETUPDONE (4 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */
# define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */
#define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-26: Reserved */
#define OTG_GRXSTSH_STSPHST (17) /* Bit 27: Status phase start */
/* Bits 28-31: Reserved */
#define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */
#define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT)
/* Bits 25-26: Reserved */
#define OTG_GRXSTSH_STSPHST (17) /* Bit 27: Status phase start */
/* Bits 28-31: Reserved */
/* Receive FIFO size register */
@ -414,25 +421,25 @@
/* Non-periodic transmit FIFO/queue status register */
#define OTG_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */
#define OTG_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */
#define OTG_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTG_HNPTXSTS_NPTXFSAV_SHIFT)
# define OTG_HNPTXSTS_NPTXFSAV_FULL (0 << OTG_HNPTXSTS_NPTXFSAV_SHIFT)
#define OTG_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */
#define OTG_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */
#define OTG_HNPTXSTS_NPTQXSAV_MASK (0xff << OTG_HNPTXSTS_NPTQXSAV_SHIFT)
# define OTG_HNPTXSTS_NPTQXSAV_FULL (0 << OTG_HNPTXSTS_NPTQXSAV_SHIFT)
#define OTG_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */
#define OTG_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */
#define OTG_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTG_HNPTXSTS_NPTXQTOP_SHIFT)
# define OTG_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTG_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */
# define OTG_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTG_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */
# define OTG_HNPTXSTS_TYPE_MASK (3 << OTG_HNPTXSTS_TYPE_SHIFT)
# define OTG_HNPTXSTS_TYPE_INOUT (0 << OTG_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */
# define OTG_HNPTXSTS_TYPE_ZLP (1 << OTG_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */
# define OTG_HNPTXSTS_TYPE_HALT (3 << OTG_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */
# define OTG_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTG_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTG_HNPTXSTS_CHNUM_MASK (15 << OTG_HNPTXSTS_CHNUM_SHIFT)
# define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HNPTXSTS_EPNUM_MASK (15 << OTG_HNPTXSTS_EPNUM_SHIFT)
/* Bit 31 Reserved */
/* Bit 31 Reserved */
/* General core configuration register */
@ -470,13 +477,14 @@
/* Host configuration register */
#define OTG_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */
#define OTG_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */
#define OTG_HCFG_FSLSPCS_MASK (3 << OTG_HCFG_FSLSPCS_SHIFT)
# define OTG_HCFG_FSLSPCS_FS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */
# define OTG_HCFG_FSLSPCS_LS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */
# define OTG_HCFG_FSLSPCS_LS6MHz (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */
#define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
/* Bits 31:3 Reserved */
#define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */
/* Bits 31:3 Reserved */
/* Host frame interval register */
#define OTG_HFIR_SHIFT (0) /* Bits 0-16: Frame interval */
@ -493,25 +501,25 @@
/* Host periodic transmit FIFO/queue status register */
#define OTG_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */
#define OTG_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */
#define OTG_HPTXSTS_PTXFSAVL_MASK (0xffff << OTG_HPTXSTS_PTXFSAVL_SHIFT)
# define OTG_HPTXSTS_PTXFSAVL_FULL (0 << OTG_HPTXSTS_PTXFSAVL_SHIFT)
#define OTG_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */
#define OTG_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */
#define OTG_HPTXSTS_PTXQSAV_MASK (0xff << OTG_HPTXSTS_PTXQSAV_SHIFT)
# define OTG_HPTXSTS_PTXQSAV_FULL (0 << OTG_HPTXSTS_PTXQSAV_SHIFT)
#define OTG_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */
#define OTG_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */
#define OTG_HPTXSTS_PTXQTOP_MASK (0xff << OTG_HPTXSTS_PTXQTOP_SHIFT)
# define OTG_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTG_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */
# define OTG_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */
# define OTG_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */
# define OTG_HPTXSTS_TYPE_MASK (3 << OTG_HPTXSTS_TYPE_SHIFT)
# define OTG_HPTXSTS_TYPE_INOUT (0 << OTG_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */
# define OTG_HPTXSTS_TYPE_ZLP (1 << OTG_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */
# define OTG_HPTXSTS_TYPE_HALT (3 << OTG_HPTXSTS_TYPE_SHIFT) /* Disable channel command */
# define OTG_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */
# define OTG_HPTXSTS_EPNUM_MASK (15 << OTG_HPTXSTS_EPNUM_SHIFT)
# define OTG_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTG_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */
# define OTG_HPTXSTS_CHNUM_MASK (15 << OTG_HPTXSTS_CHNUM_SHIFT)
# define OTG_HPTXSTS_ODD (1 << 31) /* Bit 31: Send in odd (vs even) frame */
# define OTG_HPTXSTS_ODD (1 << 31) /* Bit 31: Send in odd (vs even) frame */
/* Host all channels interrupt and all channels interrupt mask registers */
@ -519,22 +527,22 @@
/* Host port control and status register */
#define OTG_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
#define OTG_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
#define OTG_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
#define OTG_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
#define OTG_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
#define OTG_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
#define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
#define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
#define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
/* Bit 9: Reserved */
#define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
#define OTG_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */
#define OTG_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */
#define OTG_HPRT_PENA (1 << 2) /* Bit 2: Port enable */
#define OTG_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */
#define OTG_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */
#define OTG_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */
#define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */
#define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */
#define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */
/* Bit 9: Reserved */
#define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */
#define OTG_HPRT_PLSTS_MASK (3 << OTG_HPRT_PLSTS_SHIFT)
# define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
# define OTG_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */
#define OTG_HPRT_PPWR (1 << 12) /* Bit 12: Port power */
#define OTG_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */
# define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */
# define OTG_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */
#define OTG_HPRT_PPWR (1 << 12) /* Bit 12: Port power */
#define OTG_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */
#define OTG_HPRT_PTCTL_MASK (15 << OTG_HPRT_PTCTL_SHIFT)
# define OTG_HPRT_PTCTL_DISABLED (0 << OTG_HPRT_PTCTL_SHIFT) /* Test mode disabled */
# define OTG_HPRT_PTCTL_J (1 << OTG_HPRT_PTCTL_SHIFT) /* Test_J mode */
@ -542,37 +550,37 @@
# define OTG_HPRT_PTCTL_SE0_NAK (3 << OTG_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */
# define OTG_HPRT_PTCTL_PACKET (4 << OTG_HPRT_PTCTL_SHIFT) /* Test_Packet mode */
# define OTG_HPRT_PTCTL_FORCE (5 << OTG_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */
#define OTG_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */
#define OTG_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */
#define OTG_HPRT_PSPD_MASK (3 << OTG_HPRT_PSPD_SHIFT)
# define OTG_HPRT_PSPD_HS (0 << OTG_HPRT_PSPD_SHIFT) /* High speed */
# define OTG_HPRT_PSPD_FS (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */
# define OTG_HPRT_PSPD_LS (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */
/* Bits 19-31: Reserved */
/* Bits 19-31: Reserved */
/* Host channel-n characteristics register */
#define OTG_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_HCCHAR_MPSIZ_MASK (0x7ff << OTG_HCCHAR_MPSIZ_SHIFT)
#define OTG_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */
#define OTG_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */
#define OTG_HCCHAR_EPNUM_MASK (15 << OTG_HCCHAR_EPNUM_SHIFT)
#define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
#define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */
# define OTG_HCCHAR_EPDIR_OUT (0)
# define OTG_HCCHAR_EPDIR_IN OTG_HCCHAR_EPDIR
/* Bit 16 Reserved */
#define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
#define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
/* Bit 16 Reserved */
#define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */
#define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_HCCHAR_EPTYP_MASK (3 << OTG_HCCHAR_EPTYP_SHIFT)
# define OTG_HCCHAR_EPTYP_CTRL (0 << OTG_HCCHAR_EPTYP_SHIFT) /* Control */
# define OTG_HCCHAR_EPTYP_ISOC (1 << OTG_HCCHAR_EPTYP_SHIFT) /* Isochronous */
# define OTG_HCCHAR_EPTYP_BULK (2 << OTG_HCCHAR_EPTYP_SHIFT) /* Bulk */
# define OTG_HCCHAR_EPTYP_INTR (3 << OTG_HCCHAR_EPTYP_SHIFT) /* Interrupt */
#define OTG_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */
#define OTG_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */
#define OTG_HCCHAR_MCNT_MASK (3 << OTG_HCCHAR_MCNT_SHIFT)
#define OTG_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */
#define OTG_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */
#define OTG_HCCHAR_DAD_MASK (0x7f << OTG_HCCHAR_DAD_SHIFT)
#define OTG_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */
#define OTG_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */
#define OTG_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */
#define OTG_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */
#define OTG_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */
#define OTG_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */
/* TODO: OTG host channel-n split control register */
@ -604,46 +612,47 @@
# define OTG_HCTSIZ_DPID_DATA1 (2 << OTG_HCTSIZ_DPID_SHIFT)
# define OTG_HCTSIZ_DPID_MDATA (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */
# define OTG_HCTSIZ_PID_SETUP (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */
/* Bit 31: Reserved */
/* Bit 31: Reserved */
/* Device configuration register */
#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */
#define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT)
# define OTG_DCFG_DSPD_HS (0 << OTG_DCFG_DSPD_SHIFT) /* High speed */
# define OTG_DCFG_DSPD_FSHS (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using HS */
# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed using internal FS PHY */
#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
/* Bit 3: Reserved */
#define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */
# define OTG_DCFG_DSPD_HS (0 << OTG_DCFG_DSPD_SHIFT) /* High speed */
# define OTG_DCFG_DSPD_FSHS (1 << OTG_DCFG_DSPD_SHIFT) /* Full speed using HS */
# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed using internal FS PHY */
#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */
/* Bit 3: Reserved */
#define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */
#define OTG_DCFG_DAD_MASK (0x7f << OTG_DCFG_DAD_SHIFT)
#define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */
#define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */
#define OTG_DCFG_PFIVL_MASK (3 << OTG_DCFG_PFIVL_SHIFT)
# define OTG_DCFG_PFIVL_80PCT (0 << OTG_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */
# define OTG_DCFG_PFIVL_85PCT (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */
# define OTG_DCFG_PFIVL_90PCT (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */
# define OTG_DCFG_PFIVL_95PCT (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */
/* Bit 13: Reserved */
#define OTG_DCFG_XCVRDLY (1 << 14) /* Bit 14: Transceiver delay */
#define OTG_DCFG_ERRATIMY (1 << 15) /* Bit 15: Erratic error interrupt mask */
/* Bits 16-23: Reserved */
#define OTG_DCFG_PERSCHIVL_SHIFT (24) /* Bits 24-25: Periodic schedule interval */
/* Bit 13: Reserved */
#define OTG_DCFG_XCVRDLY (1 << 14) /* Bit 14: Transceiver delay */
#define OTG_DCFG_ERRATIMY (1 << 15) /* Bit 15: Erratic error interrupt mask */
/* Bits 16-23: Reserved */
#define OTG_DCFG_PERSCHIVL_SHIFT (24) /* Bits 24-25: Periodic schedule interval */
#define OTG_DCFG_PERSCHIVL_MASK (3 << OTG_DCFG_PERSCHIVL_SHIFT)
/* Bits 26-31: Reserved */
/* Bits 26-31: Reserved */
/* Device control register */
#define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */
#define OTG_TESTMODE_J (1) /* Test_J mode */
#define OTG_TESTMODE_K (2) /* Test_K mode */
#define OTG_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */
#define OTG_TESTMODE_PACKET (4) /* Test_Packet mode */
#define OTG_TESTMODE_FORCE (5) /* Test_Force_Enable */
#define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */
#define OTG_TESTMODE_J (1) /* Test_J mode */
#define OTG_TESTMODE_K (2) /* Test_K mode */
#define OTG_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */
#define OTG_TESTMODE_PACKET (4) /* Test_Packet mode */
#define OTG_TESTMODE_FORCE (5) /* Test_Force_Enable */
#define OTG_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */
#define OTG_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */
#define OTG_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */
#define OTG_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */
#define OTG_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */
#define OTG_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */
#define OTG_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */
#define OTG_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */
#define OTG_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */
#define OTG_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */
#define OTG_DCTL_TCTL_MASK (7 << OTG_DCTL_TCTL_SHIFT)
# define OTG_DCTL_TCTL_DISABLED (0 << OTG_DCTL_TCTL_SHIFT) /* Test mode disabled */
# define OTG_DCTL_TCTL_J (1 << OTG_DCTL_TCTL_SHIFT) /* Test_J mode */
@ -651,33 +660,34 @@
# define OTG_DCTL_TCTL_SE0_NAK (3 << OTG_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */
# define OTG_DCTL_TCTL_PACKET (4 << OTG_DCTL_TCTL_SHIFT) /* Test_Packet mode */
# define OTG_DCTL_TCTL_FORCE (5 << OTG_DCTL_TCTL_SHIFT) /* Test_Force_Enable */
#define OTG_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */
#define OTG_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */
#define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */
#define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */
#define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */
/* Bits 12-17: Reserved */
#define OTG_DCTL_DSBESLRJCT (1 << 18) /* Bit 18: Deep sleep BESL reject */
/* Bits 19-31: Reserved */
#define OTG_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */
#define OTG_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */
#define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */
#define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */
#define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */
/* Bits 12-17: Reserved */
#define OTG_DCTL_DSBESLRJCT (1 << 18) /* Bit 18: Deep sleep BESL reject */
/* Bits 19-31: Reserved */
/* Device status register */
#define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */
#define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */
#define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */
#define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */
#define OTG_DSTS_ENUMSPD_MASK (3 << OTG_DSTS_ENUMSPD_SHIFT)
# define OTG_DSTS_ENUMSPD_FS (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */
/* Bits 4-7: Reserved */
#define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */
#define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */
/* Bits 4-7: Reserved */
#define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */
#define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */
#define OTG_DSTS_SOFFN_MASK (0x3fff << OTG_DSTS_SOFFN_SHIFT)
#define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */
#define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */
#define OTG_DSTS_SOFFN_EVEN 0
#define OTG_DSTS_SOFFN_ODD OTG_DSTS_SOFFN0
/* Bits 23-31: Reserved */
#define OTG_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: Device line status */
/* Bits 23-31: Reserved */
#define OTG_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: Device line status */
#define OTG_DSTS_DEVLNSTS_MASK (3 << OTG_DSTS_DEVLNSTS_SHIFT)
# define OTG_DSTS_DEVLNSTS_DP (1 << OTG_DSTS_DEVLNSTS_SHIFT)
# define OTG_DSTS_DEVLNSTS_DM (2 << OTG_DSTS_DEVLNSTS_SHIFT)
/* Bits 24-31: Reserved */
/* Bits 24-31: Reserved */
/* Device IN endpoint common interrupt mask register */
@ -740,33 +750,33 @@
/* Device control IN endpoint n control register */
#define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DIEPCTL_MPSIZ_MASK (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved */
#define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
/* Bits 11-14: Reserved */
#define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */
# define OTG_DIEPCTL_EVEN (0)
# define OTG_DIEPCTL_ODD OTG_DIEPCTL_EONUM
# define OTG_DIEPCTL_DATA0 (0)
# define OTG_DIEPCTL_DATA1 OTG_DIEPCTL_EONUM
#define OTG_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DIEPCTL_EPTYP_MASK (3 << OTG_DIEPCTL_EPTYP_SHIFT)
# define OTG_DIEPCTL_EPTYP_CTRL (0 << OTG_DIEPCTL_EPTYP_SHIFT) /* Control */
# define OTG_DIEPCTL_EPTYP_ISOC (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTG_DIEPCTL_EPTYP_BULK (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTG_DIEPCTL_EPTYP_INTR (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */
/* Bit 20: Reserved */
#define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
/* Bit 20: Reserved */
#define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
#define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */
#define OTG_DIEPCTL_TXFNUM_MASK (15 << OTG_DIEPCTL_TXFNUM_SHIFT)
#define OTG_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTG_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */
#define OTG_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */
#define OTG_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
#define OTG_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTG_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */
#define OTG_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */
#define OTG_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device endpoint-n interrupt register */
@ -787,79 +797,81 @@
/* Device IN endpoint 0 transfer size register */
#define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
#define OTG_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT)
/* Bits 7-18: Reserved, must be kept at reset value */
#define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */
#define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */
#define OTG_DIEPTSIZ0_PKTCNT_MASK (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT)
/* Bits 21-31: Reserved, must be kept at reset value */
/* Device IN endpoint n transfer size register */
#define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */
#define OTG_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DIEPTSIZ_XFRSIZ_SHIFT)
#define OTG_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
#define OTG_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */
#define OTG_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT)
#define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */
#define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */
#define OTG_DIEPTSIZ_MCNT_MASK (3 << OTG_DIEPTSIZ_MCNT_SHIFT)
/* Bit 31: Reserved */
/* Bit 31: Reserved */
/* Device OUT endpoint TxFIFO status register */
#define OTG_DTXFSTS_MASK (0xffff)
/* Device OUT endpoint 0 control register */
#define OTG_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
#define OTG_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */
#define OTG_DOEPCTL0_MPSIZ_MASK (3 << OTG_DOEPCTL0_MPSIZ_SHIFT)
# define OTG_DOEPCTL0_MPSIZ_64 (0 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */
# define OTG_DOEPCTL0_MPSIZ_32 (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */
# define OTG_DOEPCTL0_MPSIZ_16 (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */
# define OTG_DOEPCTL0_MPSIZ_8 (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */
/* Bits 2-14: Reserved */
#define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved */
#define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
/* Bits 2-14: Reserved */
#define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
/* Bit 16: Reserved */
#define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DOEPCTL0_EPTYP_MASK (3 << OTG_DOEPCTL0_EPTYP_SHIFT)
# define OTG_DOEPCTL0_EPTYP_CTRL (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */
#define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved */
#define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved */
#define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
#define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved */
#define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */
/* Bits 28-29: Reserved */
#define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device OUT endpoint n control register */
#define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */
#define OTG_DOEPCTL_MPSIZ_MASK (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT)
/* Bits 11-14: Reserved */
#define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */
/* Bits 11-14: Reserved */
#define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */
#define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/bulk) */
# define OTG_DOEPCTL_DATA0 (0)
# define OTG_DOEPCTL_DATA1 OTG_DOEPCTL_DPID
#define OTG_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */
#define OTG_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */
# define OTG_DOEPCTL_EVEN (0)
# define OTG_DOEPCTL_ODD OTG_DOEPCTL_EONUM
#define OTG_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */
#define OTG_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */
#define OTG_DOEPCTL_EPTYP_MASK (3 << OTG_DOEPCTL_EPTYP_SHIFT)
# define OTG_DOEPCTL_EPTYP_CTRL (0 << OTG_DOEPCTL_EPTYP_SHIFT) /* Control */
# define OTG_DOEPCTL_EPTYP_ISOC (1 << OTG_DOEPCTL_EPTYP_SHIFT) /* Isochronous */
# define OTG_DOEPCTL_EPTYP_BULK (2 << OTG_DOEPCTL_EPTYP_SHIFT) /* Bulk */
# define OTG_DOEPCTL_EPTYP_INTR (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */
#define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved */
#define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTG_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */
#define OTG_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */
#define OTG_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */
#define OTG_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
#define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */
#define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */
/* Bits 22-25: Reserved */
#define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */
#define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */
#define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */
#define OTG_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */
#define OTG_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */
#define OTG_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */
#define OTG_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */
#define OTG_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */
/* Device endpoint-n interrupt register */
@ -877,6 +889,7 @@
#define OTG_DOEPINT_NAK (1 << 13) /* Bit 13: NAK interrupt mask */
#define OTG_DOEPINT_NYET (1 << 14) /* Bit 14: NYET interrupt mask */
/* Bits 15-31: Reserved */
/* Device OUT endpoint-0 transfer size register */
#define OTG_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */
@ -903,6 +916,7 @@
# define OTG_DOEPTSIZ_RXDPID_DATA1 (2 << OTG_DOEPTSIZ_RXDPID_SHIFT)
# define OTG_DOEPTSIZ_RXDPID_MDATA (3 << OTG_DOEPTSIZ_RXDPID_SHIFT)
/* Bit 31: Reserved */
/* Power and clock gating control register */
#define OTG_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */

4
arch/arm/src/stm32h7/hardware/stm32h7x3xx_dmamux.h
View File

@ -31,7 +31,7 @@
* Pre-processor Definitions
************************************************************************************/
/* DMAMUX1 mapping ****************************************************/
/* DMAMUX1 mapping ******************************************************************/
/* NOTE: DMAMUX1 channels 0 to 7 are connected to DMA1 channels 0 to 7.
* DMAMUX1 channels 8 to 15 are connected to DMA2 channels 0 to 7.
@ -154,7 +154,7 @@
#define DMAMUX1_ADC3 (115)
/* DMAMUX1 116-127: Reserved */
/* DMAMUX2 mapping ****************************************************/
/* DMAMUX2 mapping ******************************************************************/
/* NOTE: DMAMUX2 channels 0 to 7 are connected to BDMA channels 0 to 7 */

22
arch/arm/src/stm32h7/hardware/stm32h7x3xx_flash.h
View File

@ -114,7 +114,7 @@
/* Flash Access Control Register (ACR) Bank 1 or 2 */
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */
#define FLASH_ACR_LATENCY_SHIFT (0) /* Bits 0-3: Latency */
#define FLASH_ACR_LATENCY_MASK (15 << FLASH_ACR_LATENCY_SHIFT)
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 0000: Zero wait states */
@ -133,27 +133,29 @@
# define FLASH_ACR_LATENCY_13 (13 << FLASH_ACR_LATENCY_SHIFT) /* 1101: Thirteen wait states */
# define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */
# define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */
#define FLASH_ACR_WRHIGHFREQ_SHIFT (4) /* Bitd 4-5: Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_SHIFT (4) /* Bitd 4-5: Flash signal delay */
#define FLASH_ACR_WRHIGHFREQ_MASK (3 << FLASH_ACR_WRHIGHFREQ_SHIFT)
# define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT)
/* Flash Control Register (CR) Bank 1 or 2 (if different) */
#define FLASH_CR_LOCK (1 << 0) /* Bit 0: Lock */
#define FLASH_CR_PG (1 << 1) /* Bit 1: Programming */
#define FLASH_CR_SER (1 << 2) /* Bit 2: Sector erase */
#define FLASH_CR_BER (1 << 3) /* Bit 3: Bank erase */
#define FLASH_CR_PSIZE_SHIFT (4) /* Bits 4-5: Program size */
#define FLASH_CR_LOCK (1 << 0) /* Bit 0: Lock */
#define FLASH_CR_PG (1 << 1) /* Bit 1: Programming */
#define FLASH_CR_SER (1 << 2) /* Bit 2: Sector erase */
#define FLASH_CR_BER (1 << 3) /* Bit 3: Bank erase */
#define FLASH_CR_PSIZE_SHIFT (4) /* Bits 4-5: Program size */
#define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00: x8 */
# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01: x16 */
# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10: x32 */
# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11: x64 */
#define FLASH_CR_FW (1 << 6) /* Bit 6: Force write */
#define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */
#define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */
#define FLASH_CR_FW (1 << 6) /* Bit 6: Force write */
#define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */
#define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */
#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */
# define FLASH_CR_SNB(n) ((uint32_t)((n) & 0x7) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..7 */
/* Bits 11-13: Reserved */
#define FLASH_CR_SPSS2 (1 << 14) /* Bit 14: Bank1 Reserved, Bank 2 special sector selection bit */
#define FLASH_CR_CRCEN (1 << 15) /* Bit 15: CRC control enable */

4
arch/arm/src/stm32h7/stm32.h
View File

@ -32,10 +32,6 @@
#include "arm_internal.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Peripherals **********************************************************************/
#include "chip.h"

7
boards/arm/stm32/nucleo-f103rb/include/board.h
View File

@ -56,7 +56,9 @@
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
/* PLL source is HSE/1, PLL multipler is 9:
* PLL frequency is 8MHz (XTAL) x 9 = 72MHz
*/
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
@ -97,6 +99,7 @@
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* LED definitions **********************************************************/
/* The Nucleo F103RB board has three LEDs. Two of these are controlled by
* logic on the board and are not available for software control:
*
@ -150,6 +153,7 @@
#define LED_PANIC 1
/* Button definitions *******************************************************/
/* The Nucleo F103RB supports two buttons; only one button is controllable
* by software:
*
@ -166,6 +170,7 @@
/* Alternate function pin selections ****************************************/
/* DMA channels *************************************************************/
/* ADC */
#define ADC1_DMA_CHAN DMACHAN_ADC1 /* DMA1_CH1 */

2
boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h
View File

@ -32,6 +32,7 @@
****************************************************************************/
/* LED definitions **********************************************************/
/* The Nucleo F103RB board has three LEDs. Two of these are controlled by
* logic on the board and are not available for software control:
*
@ -55,6 +56,7 @@
#define LED_DRIVER_PATH "/dev/userleds"
/* Button definitions *******************************************************/
/* The Nucleo F103RB supports two buttons; only one button is controllable
* by software:
*

4
boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c
View File

@ -56,6 +56,7 @@
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#define ADC1_NCHANNELS 3
@ -174,6 +175,7 @@ int stm32_adc_setup(void)
if (!initialized)
{
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV1_NCHANNELS; i++)
@ -202,6 +204,7 @@ int stm32_adc_setup(void)
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)
@ -229,7 +232,6 @@ int stm32_adc_setup(void)
#endif
initialized = true;
}
return OK;

3
boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c
View File

@ -38,7 +38,8 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration *******************************************************************/
/* Configuration ************************************************************/
#define HAVE_PWM 1

35
boards/arm/stm32/nucleo-f207zg/include/board.h
View File

@ -60,10 +60,14 @@
*
* Formulae:
*
* VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63
* VCO output frequency = VCO input frequency × PLLN, 50 <= PLLN <= 432
* PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8
* USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15
* VCO input frequency =
* PLL input clock frequency / PLLM, 2 <= PLLM <= 63
* VCO output frequency =
* VCO input frequency × PLLN, 50 <= PLLN <= 432
* PLL output clock frequency =
* VCO frequency / PLLP, PLLP = 2, 4, 6, or 8
* USB OTG FS clock frequency =
* VCO frequency / PLLQ, 2 <= PLLQ <= 15
*
* We will configure like this
*
@ -123,11 +127,13 @@
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* LED definitions **********************************************************/
/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
* LED and LD3 a Red LED, that can be controlled by software. The following
* definitions assume the default Solder Bridges are installed.
/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
* in any way.
* The following definitions are used to access individual LEDs.
*/
@ -149,13 +155,14 @@
#define BOARD_LED3_BIT (1 << BOARD_LED3)
/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
* events as follows:
* include/board.h and src/stm32_leds.c. The LEDs are used to encode
* OS-related events as follows:
*
*
* SYMBOL Meaning LED state
* Red Green Blue
* ---------------------- -------------------------- ------ ------ ----*/
* ---------------------- -------------------------- ------ ------ ----
*/
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
@ -168,8 +175,10 @@
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
/* Button definitions *******************************************************/
/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is
* connected to GPIO PC13. A high value will be sensed when the button is depressed.
* connected to GPIO PC13. A high value will be sensed when the button is
* depressed.
*/
#define BUTTON_USER 0
@ -178,6 +187,7 @@
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* Alternate function pin selections ****************************************/
/* USART3 (Nucleo Virtual Console) */
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
@ -195,6 +205,7 @@
#define GPIO_TIM1_CH3NOUT GPIO_TIM1_CH3N_3 /* PE12 */
/* DMA channels *************************************************************/
/* ADC */
#define ADC1_DMA_CHAN DMAMAP_ADC1_1

20
boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h
View File

@ -32,19 +32,20 @@
****************************************************************************/
/* LED definitions **********************************************************/
/* LED
*
* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a
* Blue LED and LD3 a Red LED, that can be controlled by software. The following
* definitions assume the default Solder Bridges are installed.
* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*/
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN14)
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR |GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN14)
#define GPIO_LED_GREEN GPIO_LD1
#define GPIO_LED_BLUE GPIO_LD2
@ -53,6 +54,7 @@
#define LED_DRIVER_PATH "/dev/userleds"
/* Button definitions *******************************************************/
/* The Nucleo F207ZG supports two buttons; only one button is controllable
* by software:
*

3
boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c
View File

@ -58,6 +58,7 @@
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#define ADC1_NCHANNELS 3
@ -176,6 +177,7 @@ int stm32_adc_setup(void)
if (!initialized)
{
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV1_NCHANNELS; i++)
@ -203,6 +205,7 @@ int stm32_adc_setup(void)
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)

3
boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c
View File

@ -38,7 +38,8 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration *******************************************************************/
/* Configuration ************************************************************/
#define HAVE_PWM 1

3
boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c
View File

@ -38,7 +38,8 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration *******************************************************************/
/* Configuration ************************************************************/
#define HAVE_PWM 1

26
boards/arm/stm32/nucleo-f303ze/include/board.h
View File

@ -57,7 +57,9 @@
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
/* PLL source is HSE/1, PLL multipler is 9:
* PLL frequency is 8MHz (XTAL) x 9 = 72MHz
*/
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
@ -124,11 +126,13 @@
#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
/* LED definitions **********************************************************/
/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
* LED and LD3 a Red LED, that can be controlled by software. The following
* definitions assume the default Solder Bridges are installed.
/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
* in any way.
* The following definitions are used to access individual LEDs.
*/
@ -150,13 +154,14 @@
#define BOARD_LED3_BIT (1 << BOARD_LED3)
/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
* events as follows:
* include/board.h and src/stm32_leds.c. The LEDs are used to encode
* OS-related events as follows:
*
*
* SYMBOL Meaning LED state
* Red Green Blue
* ---------------------- -------------------------- ------ ------ ----*/
* ---------------------- -------------------------- ------ ------ ----
*/
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
@ -169,8 +174,10 @@
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
/* Button definitions *******************************************************/
/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is
* connected to GPIO PC13. A high value will be sensed when the button is depressed.
* connected to GPIO PC13. A high value will be sensed when the button is
* depressed.
*/
#define BUTTON_USER 0
@ -179,6 +186,7 @@
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* Alternate function pin selections ****************************************/
/* USART3 (Nucleo Virtual Console) */
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */

20
boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h
View File

@ -32,19 +32,20 @@
****************************************************************************/
/* LED definitions **********************************************************/
/* LED
*
* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a
* Blue LED and LD3 a Red LED, that can be controlled by software. The following
* definitions assume the default Solder Bridges are installed.
* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
* The following definitions assume the default Solder Bridges are installed.
*/
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
GPIO_PORTB | GPIO_PIN14)
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0)
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \
GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN14)
#define GPIO_LED_GREEN GPIO_LD1
#define GPIO_LED_BLUE GPIO_LD2
@ -53,6 +54,7 @@
#define LED_DRIVER_PATH "/dev/userleds"
/* Button definitions *******************************************************/
/* The Nucleo F303ZE supports two buttons; only one button is controllable
* by software:
*

3
boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c
View File

@ -58,6 +58,7 @@
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#define ADC1_NCHANNELS 3
@ -176,6 +177,7 @@ int stm32_adc_setup(void)
if (!initialized)
{
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV1_NCHANNELS; i++)
@ -203,6 +205,7 @@ int stm32_adc_setup(void)
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)

6
boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h
View File

@ -32,6 +32,7 @@
****************************************************************************/
/* LED definitions **********************************************************/
/* The Nucleo F334R8 board has three LEDs. Two of these are controlled by
* logic on the board and are not available for software control:
*
@ -55,6 +56,7 @@
#define LED_DRIVER_PATH "/dev/userleds"
/* Button definitions *******************************************************/
/* The Nucleo F334R8 supports two buttons; only one button is controllable
* by software:
*
@ -72,6 +74,7 @@
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
/* PWM definitions **********************************************************/
/* The Nucleo F334R8 has no real on-board PWM devices, but the board can be
* configured to output a pulse train using variously unused pins on the
* board for PWM output (see board.h for details of pins).
@ -114,7 +117,8 @@ void weak_function stm32_spidev_initialize(void);
* Configure the timer driver.
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* devpath - The full path to the timer device.
* This should be of the form /dev/timer0
* timer - The timer's number.
*
* Returned Value:

4
boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c
View File

@ -56,6 +56,7 @@
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#define ADC1_NCHANNELS 3
@ -174,6 +175,7 @@ int stm32_adc_setup(void)
if (!initialized)
{
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV1_NCHANNELS; i++)
@ -202,6 +204,7 @@ int stm32_adc_setup(void)
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)
@ -229,7 +232,6 @@ int stm32_adc_setup(void)
#endif
initialized = true;
}
return OK;

2
boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c
View File

@ -62,11 +62,9 @@
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
board_autoled_initialize();
#endif
}

2
boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c
View File

@ -66,7 +66,7 @@
int stm32_comp_setup(void)
{
static bool initialized = false;
struct comp_dev_s* comp = NULL;
struct comp_dev_s *comp = NULL;
int ret;
if (!initialized)

2
boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c
View File

@ -52,7 +52,7 @@
int stm32_hrtim_setup(void)
{
static bool initialized = false;
struct hrtim_dev_s* hrtim = NULL;
struct hrtim_dev_s *hrtim = NULL;
int ret;
if (!initialized)

2
boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c
View File

@ -50,7 +50,7 @@
int stm32_opamp_setup(void)
{
static bool initialized = false;
struct opamp_dev_s* opamp = NULL;
struct opamp_dev_s *opamp = NULL;
int ret;
if (!initialized)

25
boards/arm/stm32/nucleo-l152re/include/board.h
View File

@ -43,16 +43,19 @@
/* Clocking *****************************************************************/
/* Four different clock sources can be used to drive the system clock (SYSCLK):
/* Four different clock sources can be used to drive the system clock
* (SYSCLK):
*
* - HSI high-speed internal oscillator clock
* Generated from an internal 16 MHz RC oscillator
* - HSE high-speed external oscillator clock. 8 MHz from MCO output of ST-LINK.
* - HSE high-speed external oscillator clock. 8 MHz from MCO output of
* ST-LINK.
* - PLL clock
* - MSI multispeed internal oscillator clock
* The MSI clock signal is generated from an internal RC oscillator. Seven frequency
* ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
* 2.097 MHz (default value) and 4.194 MHz.
* The MSI clock signal is generated from an internal RC oscillator.
* Seven frequency ranges are available: 65.536 kHz, 131.072 kHz,
* 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value)
* and 4.194 MHz.
*
* The devices have the following two secondary clock sources
* - LSI low-speed internal RC clock
@ -82,13 +85,15 @@
* MHz frequency. This is required to provide a 48 MHz clock to the USB or
* SDIO (SDIOCLK or USBCLK = PLLVCO/2).
* SYSCLK
* The system clock is derived from the PLL VCO divided by the output division factor.
* The system clock is derived from the PLL VCO divided by the output
* division factor.
* Limitations:
* 96 MHz as PLLVCO when the product is in range 1 (1.8V),
* 48 MHz as PLLVCO when the product is in range 2 (1.5V),
* 24 MHz when the product is in range 3 (1.2V).
* Output division to avoid exceeding 32 MHz as SYSCLK.
* The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
* The minimum input clock frequency for PLL is 2 MHz (when using HSE as
* PLL source).
*/
#if 1
@ -104,8 +109,8 @@
#define STM32_PLL_FREQUENCY (6*STM32_HSI_FREQUENCY) /* PLL VCO Frequency is 96MHz */
#endif
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
* frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO
* output frequency (STM32_PLL_FREQUENCY divided by the PLLDIV value).
*/
#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
@ -132,6 +137,7 @@
/* TODO: Timers */
/* LED definitions **********************************************************/
/* The Nucleo L152RE board has three LEDs. Two of these are controlled by
* logic on the board and are not available for software control:
*
@ -185,6 +191,7 @@
#define LED_PANIC 1
/* Button definitions *******************************************************/
/* The Nucleo L152RE supports two buttons; only one button is controllable
* by software:
*

11
boards/arm/stm32/stm32f334-disco/include/board.h
View File

@ -56,7 +56,9 @@
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
#define STM32_LSE_FREQUENCY 32768 /* X2 on board */
/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
/* PLL source is HSE/1, PLL multipler is 9:
* PLL frequency is 8MHz (XTAL) x 9 = 72MHz
*/
#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
#define STM32_CFGR_PLLXTPRE 0
@ -137,8 +139,9 @@
#define BOARD_LED3_BIT (1 << BOARD_LED3)
#define BOARD_LED4_BIT (1 << BOARD_LED4)
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the
* stm32f334-disco. The following definitions describe how NuttX controls the LEDs:
/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on
* board the stm32f334-disco. The following definitions describe how NuttX
* controls the LEDs:
*/
#define LED_STARTED 0 /* LED1 */
@ -151,6 +154,7 @@
#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
/* Button definitions *******************************************************/
/* The STM32F334-DISCO supports two buttons; only one button is controllable
* by software:
*
@ -165,6 +169,7 @@
#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* Alternate function pin selections ****************************************/
/* CAN */
#define GPIO_CAN1_RX GPIO_CAN_RX_2

5
boards/arm/stm32/stm32f334-disco/src/stm32_adc.c
View File

@ -56,6 +56,7 @@
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#define ADC1_NCHANNELS 3
@ -174,6 +175,7 @@ int stm32_adc_setup(void)
if (!initialized)
{
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV1_NCHANNELS; i++)
@ -200,8 +202,8 @@ int stm32_adc_setup(void)
}
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)
@ -229,7 +231,6 @@ int stm32_adc_setup(void)
#endif
initialized = true;
}
return OK;

2
boards/arm/stm32/stm32f334-disco/src/stm32_boot.c
View File

@ -62,11 +62,9 @@
void stm32_boardinitialize(void)
{
#ifdef CONFIG_ARCH_LEDS
/* Configure on-board LEDs if LED support has been selected. */
board_autoled_initialize();
#endif
}

2
boards/arm/stm32/stm32f334-disco/src/stm32_comp.c
View File

@ -66,7 +66,7 @@
int stm32_comp_setup(void)
{
static bool initialized = false;
struct comp_dev_s* comp = NULL;
struct comp_dev_s *comp = NULL;
int ret;
if (!initialized)

2
boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c
View File

@ -52,7 +52,7 @@
int stm32_hrtim_setup(void)
{
static bool initialized = false;
struct hrtim_dev_s* hrtim = NULL;
struct hrtim_dev_s *hrtim = NULL;
int ret;
if (!initialized)

2
boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c
View File

@ -50,7 +50,7 @@
int stm32_opamp_setup(void)
{
static bool initialized = false;
struct opamp_dev_s* opamp = NULL;
struct opamp_dev_s *opamp = NULL;
int ret;
if (!initialized)

72
boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c
View File

@ -84,15 +84,15 @@
/* Maximum onboard LED current is 350mA */
#define LED_ABSOLUTE_CURRENT_LIMIT_mA 250
#define LED_ABSOLUTE_CURRENT_LIMIT 250 /* in mA */
#if (CONFIG_EXAMPLES_POWERLED_CURRENT_LIMIT > LED_ABSOLUTE_CURRENT_LIMIT_mA)
#if (CONFIG_EXAMPLES_POWERLED_CURRENT_LIMIT > LED_ABSOLUTE_CURRENT_LIMIT)
# error "Board LED maximum current is 250 mA"
#endif
/* Voltage reference for DAC */
/* Voltage reference for DAC (in mV) */
#define DAC_REF_VOLTAGE_mV 3300
#define DAC_REV_VOLTAGE 3300
/* DAC resolution */
@ -196,7 +196,8 @@ struct powerled_lower_dev_s g_powerled_lower;
static int powerled_shutdown(FAR struct powerled_dev_s *dev)
{
FAR struct powerled_s *powerled = (FAR struct powerled_s *)dev->priv;
FAR struct powerled_priv_s *priv = (struct powerled_priv_s *)powerled->priv;
FAR struct powerled_priv_s *priv =
(struct powerled_priv_s *)powerled->priv;
/* Stop powerled if running */
@ -265,20 +266,22 @@ static int powerled_setup(FAR struct powerled_dev_s *dev)
static int powerled_start(FAR struct powerled_dev_s *dev)
{
FAR struct powerled_lower_dev_s *lower = dev->lower;
FAR struct powerled_s *powerled = (FAR struct powerled_s *)dev->priv;
FAR struct powerled_s *powerled =
(FAR struct powerled_s *)dev->priv;
FAR struct hrtim_dev_s *hrtim = lower->hrtim;
FAR struct dac_dev_s *dac = lower->dac;
FAR struct powerled_priv_s *priv = (struct powerled_priv_s *)powerled->priv;
FAR struct powerled_priv_s *priv =
(struct powerled_priv_s *)powerled->priv;
uint16_t burst_cmp = 0;
uint16_t burst_per = 0;
uint16_t burst_pre = 0;
int current_av_mA = 0;
int current_max_mA;
int current_av = 0;
int current_max;
int i;
/* Set max current in mA */
current_max_mA = (int)(powerled->limits.current * 1000);
current_max = (int)(powerled->limits.current * 1000);
/* Stop HRTIM PWM */
@ -291,27 +294,28 @@ static int powerled_start(FAR struct powerled_dev_s *dev)
{
/* Average current set to max */
current_av_mA = (uint16_t)(current_max_mA);
current_av = (uint16_t)(current_max);
/* Dimming through burst mode IDLE state */
burst_pre = HRTIM_BURST_PRESCALER_1;
burst_per = 1000;
burst_cmp = (uint16_t)(((float)burst_per)*
(100.0-powerled->param.brightness)/100.0);
burst_cmp = (uint16_t)(((float)burst_per) *
(100.0 - powerled->param.brightness) / 100.0);
}
else if (powerled->opmode == POWERLED_OPMODE_FLASH)
{
/* Average current - brightness */
/* Flashing through burst mode IDLE state */
/* Maximum brightness is achieved when average LED current is equalt to
* LED current limit, and there is no IDLE state */
current_av_mA = (uint16_t)(powerled->param.brightness * current_max_mA
/ POWERLED_BRIGHTNESS_MAX);
* LED current limit, and there is no IDLE state
*/
current_av = (uint16_t)(powerled->param.brightness * current_max
/ POWERLED_BRIGHTNESS_MAX);
/* HRTIM clock = 144000000 Hz
* HRTIM burst prescaler = 32768,
@ -319,9 +323,10 @@ static int powerled_start(FAR struct powerled_dev_s *dev)
*/
burst_pre = HRTIM_BURST_PRESCALER_32768;
burst_per = (uint16_t)(((float)HRTIM_CLOCK/(1<<burst_pre))/
burst_per = (uint16_t)(((float)HRTIM_CLOCK / (1 << burst_pre)) /
powerled->param.frequency);
burst_cmp = (uint16_t)((float)burst_per*((100-powerled->param.duty)/100.0));
burst_cmp = (uint16_t)((float)burst_per *
((100 - powerled->param.duty) / 100.0));
}
/* Configure DAC buffer */
@ -330,7 +335,7 @@ static int powerled_start(FAR struct powerled_dev_s *dev)
{
/* TODO: add slope compensation */
priv->current_tab[i] = current_av_mA ;
priv->current_tab[i] = current_av ;
}
/* Convert current sense value thresholds for DAC */
@ -338,7 +343,7 @@ static int powerled_start(FAR struct powerled_dev_s *dev)
for (i = 0; i < CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE; i += 1)
{
priv->dacbuffer[i] =
priv->current_tab[i] * DAC_RESOLUTION / DAC_REF_VOLTAGE_mV;
priv->current_tab[i] * DAC_RESOLUTION / DAC_REV_VOLTAGE;
}
/* Write DAC buffer */
@ -399,8 +404,10 @@ static int powerled_stop(FAR struct powerled_dev_s *dev)
{
FAR struct powerled_lower_dev_s *lower = dev->lower;
FAR struct hrtim_dev_s *hrtim = lower->hrtim;
FAR struct powerled_s *powerled = (FAR struct powerled_s *)dev->priv;
FAR struct powerled_priv_s *priv = (struct powerled_priv_s *)powerled->priv;
FAR struct powerled_s *powerled =
(FAR struct powerled_s *)dev->priv;
FAR struct powerled_priv_s *priv =
(struct powerled_priv_s *)powerled->priv;
/* Disable output */
@ -474,9 +481,9 @@ static int powerled_limits_set(FAR struct powerled_dev_s *dev,
goto errout;
}
if (limits->current * 1000 > LED_ABSOLUTE_CURRENT_LIMIT_mA)
if (limits->current * 1000 > LED_ABSOLUTE_CURRENT_LIMIT)
{
limits->current = (float)LED_ABSOLUTE_CURRENT_LIMIT_mA/1000.0;
limits->current = (float)LED_ABSOLUTE_CURRENT_LIMIT / 1000.0;
pwrwarn("WARNING: "
"LED current limiit > LED absolute current limit."
" Set current limit to %d.\n",
@ -512,21 +519,24 @@ static int powerled_fault_set(FAR struct powerled_dev_s *dev, uint8_t fault)
return -1;
}
static int powerled_fault_get(FAR struct powerled_dev_s *dev, FAR uint8_t *fault)
static int powerled_fault_get(FAR struct powerled_dev_s *dev,
FAR uint8_t *fault)
{
/* Do nothing */
return -1;
}
static int powerled_fault_clean(FAR struct powerled_dev_s *dev, uint8_t fault)
static int powerled_fault_clean(FAR struct powerled_dev_s *dev,
uint8_t fault)
{
/* Do nothing */
return -1;
}
static int powerled_ioctl(FAR struct powerled_dev_s *dev, int cmd, unsigned long arg)
static int powerled_ioctl(FAR struct powerled_dev_s *dev, int cmd,
unsigned long arg)
{
/* Do nothing */
@ -578,7 +588,8 @@ int stm32_powerled_setup(void)
dac = stm32_dacinitialize(DAC_CURRENT_LIMIT);
if (dac == NULL)
{
pwrerr("ERROR: Failed to get DAC %d interface\n", DAC_CURRENT_LIMIT);
pwrerr("ERROR: Failed to get DAC %d interface\n",
DAC_CURRENT_LIMIT);
return -ENODEV;
}
@ -600,7 +611,8 @@ int stm32_powerled_setup(void)
lower->adc = NULL;
lower->opamp = NULL;
/* We do not need register character drivers for POWERLED lower peripherals.
/* We do not need register character drivers for POWERLED lower
* peripherals.
* All control should be done via POWERLED character driver.
*/

4
boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h
View File

@ -53,6 +53,7 @@
#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0)
/* PWM definitions **********************************************************/
/* The STM32F334-DISCO has no real on-board PWM devices, but the board can be
* configured to output a pulse train using variously unused pins on the
* board for PWM output (see board.h for details of pins).
@ -95,7 +96,8 @@ void weak_function stm32_spidev_initialize(void);
* Configure the timer driver.
*
* Input Parameters:
* devpath - The full path to the timer device. This should be of the form /dev/timer0
* devpath - The full path to the timer device.
* This should be of the form /dev/timer0
* timer - The timer's number.
*
* Returned Value:

3
boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c
View File

@ -58,6 +58,7 @@
#endif
/* The number of ADC channels in the conversion list */
/* TODO DMA */
#define ADC1_NCHANNELS 2
@ -170,6 +171,7 @@ int stm32_adc_setup(void)
if (!initialized)
{
/* DEV1 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV1_NCHANNELS; i++)
@ -197,6 +199,7 @@ int stm32_adc_setup(void)
#ifdef DEV2_PORT
/* DEV2 */
/* Configure the pins as analog inputs for the selected channels */
for (i = 0; i < DEV2_NCHANNELS; i++)

4
boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c
View File

@ -127,8 +127,8 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
#ifdef CONFIG_LPWAN_SX127X
case SPIDEV_LPWAN(0):
{
piinfo("SX127X device %s\n",
selected ? "asserted" : "de-asserted");
spiinfo("SX127X device %s\n",
selected ? "asserted" : "de-asserted");
/* Set the GPIO low to select and high to de-select */

3
boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c
View File

@ -165,7 +165,8 @@ static int sx127x_pa_select(bool enable)
if (enable == false)
{
ret = -EINVAL;
wlerr("Module supports only PA_BOOST pin, so PA_SELECT must be enabled!\n");
wlerr("Module supports only PA_BOOST pin, "
"so PA_SELECT must be enabled!\n");
}
return ret;

11
boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c
View File

@ -61,7 +61,7 @@
* CONFIG_BOARD_LATE_INITIALIZE=y :
* Called from board_late_initialize().
*
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y && CONFIG_NSH_ARCHINIT:
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
* Called from the NSH library
*
****************************************************************************/
@ -76,7 +76,8 @@ int stm32_bringup(void)
ret = userled_lower_initialize(LED_DRIVER_PATH);
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n",
ret);
return ret;
}
#endif
@ -125,7 +126,8 @@ int stm32_bringup(void)
ret = stm32_wlinitialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n",
ret);
}
#endif /* CONFIG_WL_NRF24L01 */
@ -133,7 +135,8 @@ int stm32_bringup(void)
ret = stm32_lpwaninitialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n", ret);
syslog(LOG_ERR, "ERROR: Failed to initialize wireless driver: %d\n",
ret);
}
#endif /* CONFIG_LPWAN_SX127X */

17
boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/****************************************************************************
* boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -18,7 +18,7 @@
*
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Included Files
****************************************************************************/
@ -33,7 +33,7 @@
#include <nucleo-h743zi.h>
#include <nuttx/sensors/lsm303agr.h>
/*****************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -41,15 +41,16 @@
# error "LSM303AGR driver requires CONFIG_STM32H7_I2C1 to be enabled"
#endif
/*****************************************************************************
/****************************************************************************
* Public Functions
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Name: stm32_lsm303agr_initialize
*
* Description:
* Initialize I2C-based LSM303AGR.
*
****************************************************************************/
int stm32_lsm303agr_initialize(char *devpath)
@ -66,10 +67,12 @@ int stm32_lsm303agr_initialize(char *devpath)
return -ENODEV;
}
ret = lsm303agr_sensor_register("/dev/lsm303agr0", i2c, LSM303AGRMAGNETO_ADDR);
ret = lsm303agr_sensor_register("/dev/lsm303agr0", i2c,
LSM303AGRMAGNETO_ADDR);
if (ret < 0)
{
snerr("ERROR: Failed to initialize LMS303AGR magneto driver %s\n", devpath);
snerr("ERROR: Failed to initialize LMS303AGR magneto driver %s\n",
devpath);
return -ENODEV;
}

17
boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/****************************************************************************
* boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -18,7 +18,7 @@
*
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Included Files
****************************************************************************/
@ -33,7 +33,7 @@
#include <nucleo-h743zi.h>
#include <nuttx/sensors/lsm6dsl.h>
/*****************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -41,15 +41,16 @@
# error "LSM6DSL driver requires CONFIG_STM32H7_I2C1 to be enabled"
#endif
/*****************************************************************************
/****************************************************************************
* Public Functions
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Name: stm32_lsm6dsl_initialize
*
* Description:
* Initialize I2C-based LSM6DSL.
*
****************************************************************************/
int stm32_lsm6dsl_initialize(char *devpath)
@ -70,12 +71,14 @@ int stm32_lsm6dsl_initialize(char *devpath)
return -ENODEV;
}
sninfo("INFO: Initializing LMS6DSL accelero-gyro sensor over I2C%d\n", ret);
sninfo("INFO: Initializing LMS6DSL accelero-gyro sensor over I2C%d\n",
ret);
ret = lsm6dsl_sensor_register(devpath, i2c, LSM6DSLACCEL_ADDR1);
if (ret < 0)
{
snerr("ERROR: Failed to initialize LMS6DSL accelero-gyro driver %s\n", devpath);
snerr("ERROR: Failed to initialize LMS6DSL accelero-gyro driver %s\n",
devpath);
return -ENODEV;
}

11
boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/****************************************************************************
* boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -18,7 +18,7 @@
*
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Included Files
****************************************************************************/
@ -33,7 +33,7 @@
#include <nucleo-h743zi.h>
#include <nuttx/sensors/lsm9ds1.h>
/*****************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@ -45,15 +45,16 @@
#define LSM9DS1ACC_DEVPATH "/dev/lsm9ds1acc0"
#define LSM9DS1GYR_DEVPATH "/dev/lsm9ds1gyr0"
/*****************************************************************************
/****************************************************************************
* Public Functions
****************************************************************************/
/*****************************************************************************
/****************************************************************************
* Name: stm32_lsm9ds1_initialize
*
* Description:
* Initialize I2C-based LSM9DS1.
*
****************************************************************************/
int stm32_lsm9ds1_initialize(void)