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Adding support of PIC32MX5xx/6xx/7xx families

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4034 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-10-10 16:52:14 +00:00
parent edcbdb6d61
commit 650ea59d79
20 changed files with 3013 additions and 1743 deletions
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2
arch/mips/include/mips32/cp0.h
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@ -2,7 +2,7 @@
* arch/mips/include/mips32/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

1386
arch/mips/include/pic32mx/chip.h Normal file
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6
arch/mips/include/pic32mx/cp0.h
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@ -2,7 +2,7 @@
* arch/mips/include/pic32mx/cp0.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -66,6 +66,10 @@
# define PIC32MX_CP0_CONFIG1 $16,1 /* Configuration register 1 */
# define PIC32MX_CP0_CONFIG2 $16,2 /* Configuration register 3 */
# define PIC32MX_CP0_CONFIG3 $16,3 /* Configuration register 3 */
# define PIC32MX_CP0_DEBUG $23,3 /* Debug control and exception status */
# define PIC32MX_CP0_DEPC $24,3 /* Program counter at last debug exception */
# define PIC32MX_CP0_ERREPC $30,3 /* Program counter at last error */
# define PIC32MX_CP0_DESAVE $31,3 /* Debug handler scratchpad register */
#endif
/* CP0 Registers ************************************************************/

129
arch/mips/include/pic32mx/irq.h
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@ -2,7 +2,7 @@
* arch/mips/include/pic32mx/irq.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -44,128 +44,19 @@
* Included Files
****************************************************************************/
#include <arch/pic32mx/chip.h>
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
# include <arch/pic32mx/irq_3xx4xx.h>
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# include <arch/pic32mx/irq_5xx6xx7xx.h>
#else
# error "Unknown PIC32MX family
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt vector numbers. These should be used to attach to interrupts
* and to change interrupt priorities.
*/
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
#define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
#define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
/* Vectors 40-43: Not used */
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB */
#define PIC32MX_IRQ_BAD 46 /* Not a real IRQ number */
#define NR_IRQS 46
/* Interrupt numbers. These should be used for enabling and disabling
* interrupt sources. Note that there are more interrupt sources than
* interrupt vectors and interrupt priorities. An offset of 128 is
* used so that there is no overlap with the IRQ numbers and to avoid
* errors due to misuse.
*/
#define PIC32MX_IRQSRC0_FIRST (128+0)
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 */
#define PIC32MX_IRQSRC_SPI1TX (128+24) /* Vector: 23, " " */
#define PIC32MX_IRQSRC_SPI1RX (128+25) /* Vector: 23, " " */
#define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 */
#define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, " " */
#define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, " " */
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 */
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " */
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " */
#define PIC32MX_IRQSRC0_LAST (128+31)
#define PIC32MX_IRQSRC1_FIRST (128+32)
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 */
#define PIC32MX_IRQSRC_SPI2TX (128+38) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_SPI2RX (128+39) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 */
#define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 */
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB */
#define PIC32MX_IRQSRC1_LAST (128+57)
/****************************************************************************
* Public Types
****************************************************************************/

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arch/mips/include/pic32mx/irq_3xx4xx.h Executable file
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/****************************************************************************
* arch/mips/include/pic32mx/irq_3xx4xx.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt vector numbers. These should be used to attach to interrupts
* and to change interrupt priorities.
*/
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
#define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
#define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
/* Vectors 40-43: Not used */
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB */
#define PIC32MX_IRQ_BAD 46 /* Not a real IRQ number */
#define NR_IRQS 46
/* Interrupt numbers. These should be used for enabling and disabling
* interrupt sources. Note that there are more interrupt sources than
* interrupt vectors and interrupt priorities. An offset of 128 is
* used so that there is no overlap with the IRQ numbers and to avoid
* errors due to misuse.
*/
#define PIC32MX_IRQSRC0_FIRST (128+0)
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 */
#define PIC32MX_IRQSRC_SPI1TX (128+24) /* Vector: 23, " " */
#define PIC32MX_IRQSRC_SPI1RX (128+25) /* Vector: 23, " " */
#define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 */
#define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, " " */
#define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, " " */
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 */
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " */
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " */
#define PIC32MX_IRQSRC0_LAST (128+31)
#define PIC32MX_IRQSRC1_FIRST (128+32)
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 */
#define PIC32MX_IRQSRC_SPI2TX (128+38) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_SPI2RX (128+39) /* Vector: 31, " " */
#define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 */
#define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, " " */
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 */
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " */
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB */
#define PIC32MX_IRQSRC1_LAST (128+57)
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC1_LAST
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_3XX4XX_H */

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arch/mips/include/pic32mx/irq_5xx6xx7xx.h Executable file
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/****************************************************************************
* arch/mips/include/pic32mx/irq_5xx6xx7xx.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
*/
#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
#define __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Interrupt vector numbers. These should be used to attach to interrupts
* and to change interrupt priorities.
*/
#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQ_SPI1 23 /* Vector: 23, SPI1 */
#define PIC32MX_IRQ_VEC24 24 /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQ_U1 24 /* Vector: 24, UART1 */
# define PIC32MX_IRQ_SPI3 24 /* Vector: 24, SPI3 */
# define PIC32MX_IRQ_I2C3 24 /* Vector: 24, I2C3 */
#define PIC32MX_IRQ_I2C1 25 /* Vector: 25, I2C1 */
#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQ_VEC31 31 /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQ_U3 31 /* Vector: 31, UART3 */
# define PIC32MX_IRQ_SPI2 31 /* Vector: 31, SPI2 */
# define PIC32MX_IRQ_I2C4 31 /* Vector: 31, I2C4 */
#define PIC32MX_IRQ_VEC31 32 /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQ_U2 32 /* Vector: 32, UART2 */
# define PIC32MX_IRQ_SPI4 32 /* Vector: 32, SPI4 */
# define PIC32MX_IRQ_I2C5 32 /* Vector: 32, I2C5 */
#define PIC32MX_IRQ_I2C2 33 /* Vector: 33, I2C2 */
#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQ_DMA4 40 /* Vector: 40, DMA Channel 3 */
#define PIC32MX_IRQ_DMA5 41 /* Vector: 41, DMA Channel 3 */
#define PIC32MX_IRQ_DMA6 42 /* Vector: 42, DMA Channel 3 */
#define PIC32MX_IRQ_DMA7 43 /* Vector: 43, DMA Channel 3 */
#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB Interrupt */
#define PIC32MX_IRQ_CAN1 46 /* Vector: 46, Control Area Network 1 */
#define PIC32MX_IRQ_CAN2 47 /* Vector: 47, Control Area Network 2 */
#define PIC32MX_IRQ_ETH 48 /* Vector: 48, Ethernet interrupt */
#define PIC32MX_IRQ_U4 49 /* Vector: 49, UART4 */
#define PIC32MX_IRQ_U6 50 /* Vector: 50, UART6 */
#define PIC32MX_IRQ_U5 51 /* Vector: 51, UART5 */
#define PIC32MX_IRQ_BAD 52 /* Not a real IRQ number */
#define NR_IRQS 52
/* Interrupt numbers. These should be used for enabling and disabling
* interrupt sources. Note that there are more interrupt sources than
* interrupt vectors and interrupt priorities. An offset of 128 is
* used so that there is no overlap with the IRQ numbers and to avoid
* errors due to misuse.
*/
#define PIC32MX_IRQSRC0_FIRST (128+0)
#define PIC32MX_IRQSRC_CT (128+0) /* Vector: 0, Core Timer Interrupt */
#define PIC32MX_IRQSRC_CS0 (128+1) /* Vector: 1, Core Software Interrupt 0 */
#define PIC32MX_IRQSRC_CS1 (128+2) /* Vector: 2, Core Software Interrupt 1 */
#define PIC32MX_IRQSRC_INT0 (128+3) /* Vector: 3, External Interrupt 0 */
#define PIC32MX_IRQSRC_T1 (128+4) /* Vector: 4, Timer 1 */
#define PIC32MX_IRQSRC_IC1 (128+5) /* Vector: 5, Input Capture 1 */
#define PIC32MX_IRQSRC_OC1 (128+6) /* Vector: 6, Output Compare 1 */
#define PIC32MX_IRQSRC_INT1 (128+7) /* Vector: 7, External Interrupt 1 */
#define PIC32MX_IRQSRC_T2 (128+8) /* Vector: 8, Timer 2 */
#define PIC32MX_IRQSRC_IC2 (128+9) /* Vector: 9, Input Capture 2 */
#define PIC32MX_IRQSRC_OC2 (128+10) /* Vector: 10, Output Compare 2 */
#define PIC32MX_IRQSRC_INT2 (128+11) /* Vector: 11, External Interrupt 2 */
#define PIC32MX_IRQSRC_T3 (128+12) /* Vector: 12, Timer 3 */
#define PIC32MX_IRQSRC_IC3 (128+13) /* Vector: 13, Input Capture 3 */
#define PIC32MX_IRQSRC_OC3 (128+14) /* Vector: 14, Output Compare 3 */
#define PIC32MX_IRQSRC_INT3 (128+15) /* Vector: 15, External Interrupt 3 */
#define PIC32MX_IRQSRC_T4 (128+16) /* Vector: 16, Timer 4 */
#define PIC32MX_IRQSRC_IC4 (128+17) /* Vector: 17, Input Capture 4 */
#define PIC32MX_IRQSRC_OC4 (128+18) /* Vector: 18, Output Compare 4 */
#define PIC32MX_IRQSRC_INT4 (128+19) /* Vector: 19, External Interrupt 4 */
#define PIC32MX_IRQSRC_T5 (128+20) /* Vector: 20, Timer 5 */
#define PIC32MX_IRQSRC_IC5 (128+21) /* Vector: 21, Input Capture 5 */
#define PIC32MX_IRQSRC_OC5 (128+22) /* Vector: 22, Output Compare 5 */
#define PIC32MX_IRQSRC_SPI1E (128+23) /* Vector: 23, SPI1 Fault */
#define PIC32MX_IRQSRC_SPI1TX (128+24) /* Vector: 23, " " Receive done */
#define PIC32MX_IRQSRC_SPI1RX (128+25) /* Vector: 23, " " Transfer done */
#define PIC32MX_IRQSRC_26 (128+26) /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQSRC_U1E (128+26) /* Vector: 24, UART1 Error */
# define PIC32MX_IRQSRC_SPI3E (128+26) /* Vector: 24, SPI3 Fault */
# define PIC32MX_IRQSRC_I2C3B (128+26) /* Vector: 24, I2C3 Bus collision event */
#define PIC32MX_IRQSRC_27 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQSRC_U1RX (128+27) /* Vector: 24, UART1 Receiver */
# define PIC32MX_IRQSRC_SPI3RX (128+27) /* Vector: 24, SPI3 Receive done */
# define PIC32MX_IRQSRC_I2C3S (128+27) /* Vector: 24, I2C3 Slave event */
#define PIC32MX_IRQSRC_28 (128+27) /* Vector: 24, UART1, SPI3, I2C3 */
# define PIC32MX_IRQSRC_U1TX (128+28) /* Vector: 24, UART1 Transmitter */
# define PIC32MX_IRQSRC_SPI3TX (128+28) /* Vector: 24, SPI3 Transfer done */
# define PIC32MX_IRQSRC_I2C3M (128+28) /* Vector: 24, I2C3 Master event */
#define PIC32MX_IRQSRC_I2C1B (128+29) /* Vector: 25, I2C1 Bus collision event*/
#define PIC32MX_IRQSRC_I2C1S (128+30) /* Vector: 25, " " Slave event */
#define PIC32MX_IRQSRC_I2C1M (128+31) /* Vector: 25, " " Master event */
#define PIC32MX_IRQSRC0_LAST (128+31)
#define PIC32MX_IRQSRC1_FIRST (128+32)
#define PIC32MX_IRQSRC_CN (128+32) /* Vector: 26, Input Change Interrupt */
#define PIC32MX_IRQSRC_AD1 (128+33) /* Vector: 27, ADC1 Convert Done */
#define PIC32MX_IRQSRC_PMP (128+34) /* Vector: 28, Parallel Master Port */
#define PIC32MX_IRQSRC_CMP1 (128+35) /* Vector: 29, Comparator Interrupt */
#define PIC32MX_IRQSRC_CMP2 (128+36) /* Vector: 30, Comparator Interrupt */
#define PIC32MX_IRQSRC_37 (128+37) /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQSRC_U3E (128+37) /* Vector: 31, UART3 Error */
# define PIC32MX_IRQSRC_SPI2E (128+37) /* Vector: 31, SPI2 Fault */
# define PIC32MX_IRQSRC_I2C4B (128+37) /* Vector: 31, I2C4 Bus collision event */
#define PIC32MX_IRQSRC_38 (128+38) /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQSRC_U3RX (128+38) /* Vector: 31, UART3 Receiver */
# define PIC32MX_IRQSRC_SPI2RX (128+38) /* Vector: 31, SPI2 Receive done */
# define PIC32MX_IRQSRC_I2C4S (128+38) /* Vector: 31, I2C4 Slave event */
#define PIC32MX_IRQSRC_39 (128+39) /* Vector: 31, UART3, SPI2, I2C4 */
# define PIC32MX_IRQSRC_U3TX (128+39) /* Vector: 31, UART3 Transmitter */
# define PIC32MX_IRQSRC_SPI2TX (128+39) /* Vector: 31, SPI2 Transfer done */
# define PIC32MX_IRQSRC_I2C4M (128+39) /* Vector: 31, I2C4 Master event */
#define PIC32MX_IRQSRC_40 (128+40) /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQSRC_U2E (128+40) /* Vector: 32, UART2 Error */
# define PIC32MX_IRQSRC_SPI4E (128+40) /* Vector: 32, SPI4 Fault */
# define PIC32MX_IRQSRC_I2C5B (128+40) /* Vector: 32, I2C5 Bus collision event */
#define PIC32MX_IRQSRC_41 (128+41) /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQSRC_U2RX (128+41) /* Vector: 32, UART2 Receiver */
# define PIC32MX_IRQSRC_SPI4RX (128+41) /* Vector: 32, SPI4 Receive done */
# define PIC32MX_IRQSRC_I2C5S (128+41) /* Vector: 32, I2C5 Slave event */
#define PIC32MX_IRQSRC_42 (128+42) /* Vector: 32, UART2, SPI4, I2C5 */
# define PIC32MX_IRQSRC_U2TX (128+42) /* Vector: 32, UART2 Transmitter */
# define PIC32MX_IRQSRC_SPI4TX (128+42) /* Vector: 32, SPI4 Transfer done */
# define PIC32MX_IRQSRC_I2C5M (128+42) /* Vector: 32, I2C5 Master event */
#define PIC32MX_IRQSRC_I2C2B (128+43) /* Vector: 33, I2C2 Bus collision event */
#define PIC32MX_IRQSRC_I2C2S (128+44) /* Vector: 33, " " Slave event */
#define PIC32MX_IRQSRC_I2C2M (128+45) /* Vector: 33, " " Master event */
#define PIC32MX_IRQSRC_FSCM (128+46) /* Vector: 34, Fail-Safe Clock Monitor */
#define PIC32MX_IRQSRC_RTCC (128+47) /* Vector: 35, Real-Time Clock and Calendar */
#define PIC32MX_IRQSRC_DMA0 (128+48) /* Vector: 36, DMA Channel 0 */
#define PIC32MX_IRQSRC_DMA1 (128+49) /* Vector: 37, DMA Channel 1 */
#define PIC32MX_IRQSRC_DMA2 (128+50) /* Vector: 38, DMA Channel 2 */
#define PIC32MX_IRQSRC_DMA3 (128+51) /* Vector: 39, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA4 (128+52) /* Vector: 40, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA5 (128+53) /* Vector: 41, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA6 (128+54) /* Vector: 42, DMA Channel 3 */
#define PIC32MX_IRQSRC_DMA7 (128+55) /* Vector: 43, DMA Channel 3 */
#define PIC32MX_IRQSRC_FCE (128+56) /* Vector: 44, Flash Control Event */
#define PIC32MX_IRQSRC_USB (128+57) /* Vector: 45, USB Interrupt */
#define PIC32MX_IRQSRC_CAN1 (128+58) /* Vector: 46, Control Area Network 1 */
#define PIC32MX_IRQSRC_CAN2 (128+59) /* Vector: 47, Control Area Network 2 */
#define PIC32MX_IRQSRC_ETH (128+60) /* Vector: 48, Ethernet interrupt */
#define PIC32MX_IRQSRC_IC1E (128+61) /* Vector: 5, Input capture 1 error */
#define PIC32MX_IRQSRC_IC2E (128+62) /* Vector: 9, Input capture 1 error */
#define PIC32MX_IRQSRC_IC3E (128+63) /* Vector: 13, Input capture 1 error */
#define PIC32MX_IRQSRC1_LAST (128+63)
#define PIC32MX_IRQSRC2_FIRST (128+64)
#define PIC32MX_IRQSRC_IC4E (128+64) /* Vector: 17, Input capture 1 error */
#define PIC32MX_IRQSRC_IC5E (128+65) /* Vector: 21, Input capture 1 error */
#define PIC32MX_IRQSRC_PMPE (128+66) /* Vector: 28, Parallel master port error */
#define PIC32MX_IRQSRC_U4E (128+67) /* Vector: 49, UART4 Error */
#define PIC32MX_IRQSRC_U4RX (128+68) /* Vector: 49, UART4 Receiver */
#define PIC32MX_IRQSRC_U4TX (128+69) /* Vector: 49, UART4 Transmitter */
#define PIC32MX_IRQSRC_U6E (128+70) /* Vector: 50, UART6 Error */
#define PIC32MX_IRQSRC_U6RX (128+71) /* Vector: 50, UART6 Receiver */
#define PIC32MX_IRQSRC_U6TX (128+72) /* Vector: 50, UART6 Transmitter */
#define PIC32MX_IRQSRC_U5E (128+73) /* Vector: 51, UART5 Error */
#define PIC32MX_IRQSRC_U5RX (128+74) /* Vector: 51, UART5 Receiver */
#define PIC32MX_IRQSRC_U5TX (128+75) /* Vector: 51, UART5 Transmitter */
#define PIC32MX_IRQSRC2_LAST (128+75)
#define PIC32MX_IRQSRC_FIRST PIC32MX_IRQSRC0_FIRST
#define PIC32MX_IRQSRC_LAST PIC32MX_IRQSRC2_LAST
/****************************************************************************
* Public Types
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Inline functions
****************************************************************************/
/****************************************************************************
* Public Variables
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_IRQ_5XX6XX7XX_H */

1314
arch/mips/src/pic32mx/chip.h
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File diff suppressed because it is too large Load Diff

2
arch/mips/src/pic32mx/pic32mx-bmx.h
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@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-bmx.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

76
arch/mips/src/pic32mx/pic32mx-config.h
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@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-config.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -500,34 +500,98 @@
/* UARTs ****************************************************************************/
/* Don't enable UARTs not supported by the chip. */
#if CHIP_NEUARTS < 1
#if CHIP_NUARTS < 1
# undef CONFIG_PIC32MX_UART1
# undef CONFIG_PIC32MX_UART2
#endif
#if CHIP_NEUARTS < 2
# undef CONFIG_PIC32MX_UART3
# undef CONFIG_PIC32MX_UART4
# undef CONFIG_PIC32MX_UART5
# undef CONFIG_PIC32MX_UART6
#elif CHIP_NUARTS < 2
# undef CONFIG_PIC32MX_UART2
# undef CONFIG_PIC32MX_UART3
# undef CONFIG_PIC32MX_UART4
# undef CONFIG_PIC32MX_UART5
# undef CONFIG_PIC32MX_UART6
#elif CHIP_NUARTS < 3
# undef CONFIG_PIC32MX_UART3
# undef CONFIG_PIC32MX_UART4
# undef CONFIG_PIC32MX_UART5
# undef CONFIG_PIC32MX_UART6
#elif CHIP_NUARTS < 4
# undef CONFIG_PIC32MX_UART4
# undef CONFIG_PIC32MX_UART5
# undef CONFIG_PIC32MX_UART6
#elif CHIP_NUARTS < 5
# undef CONFIG_PIC32MX_UART5
# undef CONFIG_PIC32MX_UART6
#elif CHIP_NUARTS < 6
# undef CONFIG_PIC32MX_UART6
#endif
/* Are any UARTs enabled? */
#undef HAVE_UART_DEVICE
#if defined(CONFIG_PIC32MX_UART1) || defined(CONFIG_PIC32MX_UART2)
#if defined(CONFIG_PIC32MX_UART1) || defined(CONFIG_PIC32MX_UART2) || \
defined(CONFIG_PIC32MX_UART4) || defined(CONFIG_PIC32MX_UART4) || \
defined(CONFIG_PIC32MX_UART5) || defined(CONFIG_PIC32MX_UART6)
# define HAVE_UART_DEVICE 1
#endif
/* Is there a serial console? There should be at most one defined. It
* could be on any UARTn, n=0,1
* could be on any UARTn, n=1,.. CHIP_NUARTS
*/
#if defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART1)
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART2)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART3)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART4)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART5)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_PIC32MX_UART6)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# define HAVE_SERIAL_CONSOLE 1
#else
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef CONFIG_UART4_SERIAL_CONSOLE
# undef CONFIG_UART5_SERIAL_CONSOLE
# undef CONFIG_UART6_SERIAL_CONSOLE
# undef HAVE_SERIAL_CONSOLE
#endif

191
arch/mips/src/pic32mx/pic32mx-i2c.h
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@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-i2c.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -42,6 +42,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
/************************************************************************************
@ -77,57 +78,145 @@
/* Register Addresses ***************************************************************/
#define PIC32MX_I2C1_CON (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET)
#define PIC32MX_I2C1_CONCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
#define PIC32MX_I2C1_CONSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
#define PIC32MX_I2C1_CONINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
#define PIC32MX_I2C1_STAT (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STAT_OFFSET)
#define PIC32MX_I2C1_STATCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
#define PIC32MX_I2C1_STATSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
#define PIC32MX_I2C1_STATINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
#define PIC32MX_I2C1_ADD (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADD_OFFSET)
#define PIC32MX_I2C1_ADDCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
#define PIC32MX_I2C1_ADDSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
#define PIC32MX_I2C1_ADDINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
#define PIC32MX_I2C1_MSK (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSK_OFFSET)
#define PIC32MX_I2C1_MSKCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
#define PIC32MX_I2C1_MSKSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
#define PIC32MX_I2C1_MSKINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
#define PIC32MX_I2C1_BRG (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRG_OFFSET)
#define PIC32MX_I2C1_BRGSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
#define PIC32MX_I2C1_BRGCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
#define PIC32MX_I2C1_BRGINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
#define PIC32MX_I2C1_TRN (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRN_OFFSET)
#define PIC32MX_I2C1_TRNCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
#define PIC32MX_I2C1_TRNSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
#define PIC32MX_I2C1_TRNINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
#define PIC32MX_I2C1_RCV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#if CHIP_NI2C > 0
# define PIC32MX_I2C1_CON (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CON_OFFSET)
# define PIC32MX_I2C1_CONCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
# define PIC32MX_I2C1_CONSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
# define PIC32MX_I2C1_CONINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
# define PIC32MX_I2C1_STAT (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STAT_OFFSET)
# define PIC32MX_I2C1_STATCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
# define PIC32MX_I2C1_STATSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
# define PIC32MX_I2C1_STATINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
# define PIC32MX_I2C1_ADD (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADD_OFFSET)
# define PIC32MX_I2C1_ADDCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
# define PIC32MX_I2C1_ADDSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
# define PIC32MX_I2C1_ADDINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
# define PIC32MX_I2C1_MSK (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSK_OFFSET)
# define PIC32MX_I2C1_MSKCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
# define PIC32MX_I2C1_MSKSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
# define PIC32MX_I2C1_MSKINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
# define PIC32MX_I2C1_BRG (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRG_OFFSET)
# define PIC32MX_I2C1_BRGSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
# define PIC32MX_I2C1_BRGCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
# define PIC32MX_I2C1_BRGINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
# define PIC32MX_I2C1_TRN (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRN_OFFSET)
# define PIC32MX_I2C1_TRNCLR (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
# define PIC32MX_I2C1_TRNSET (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
# define PIC32MX_I2C1_TRNINV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
# define PIC32MX_I2C1_RCV (PIC32MX_I2C1_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#endif
#define PIC32MX_I2C2_CON (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CON_OFFSET)
#define PIC32MX_I2C2_CONCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
#define PIC32MX_I2C2_CONSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
#define PIC32MX_I2C2_CONINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
#define PIC32MX_I2C2_STAT (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STAT_OFFSET)
#define PIC32MX_I2C2_STATCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
#define PIC32MX_I2C2_STATSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
#define PIC32MX_I2C2_STATINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
#define PIC32MX_I2C2_ADD (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADD_OFFSET)
#define PIC32MX_I2C2_ADDCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
#define PIC32MX_I2C2_ADDSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
#define PIC32MX_I2C2_ADDINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
#define PIC32MX_I2C2_MSK (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSK_OFFSET)
#define PIC32MX_I2C2_MSKCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
#define PIC32MX_I2C2_MSKSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
#define PIC32MX_I2C2_MSKINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
#define PIC32MX_I2C2_BRG (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRG_OFFSET)
#define PIC32MX_I2C2_BRGSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
#define PIC32MX_I2C2_BRGCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
#define PIC32MX_I2C2_BRGINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
#define PIC32MX_I2C2_TRN (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRN_OFFSET)
#define PIC32MX_I2C2_TRNCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
#define PIC32MX_I2C2_TRNSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
#define PIC32MX_I2C2_TRNINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
#define PIC32MX_I2C2_RCV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#if CHIP_NI2C > 1
# define PIC32MX_I2C2_CON (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CON_OFFSET)
# define PIC32MX_I2C2_CONCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
# define PIC32MX_I2C2_CONSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
# define PIC32MX_I2C2_CONINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
# define PIC32MX_I2C2_STAT (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STAT_OFFSET)
# define PIC32MX_I2C2_STATCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
# define PIC32MX_I2C2_STATSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
# define PIC32MX_I2C2_STATINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
# define PIC32MX_I2C2_ADD (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADD_OFFSET)
# define PIC32MX_I2C2_ADDCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
# define PIC32MX_I2C2_ADDSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
# define PIC32MX_I2C2_ADDINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
# define PIC32MX_I2C2_MSK (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSK_OFFSET)
# define PIC32MX_I2C2_MSKCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
# define PIC32MX_I2C2_MSKSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
# define PIC32MX_I2C2_MSKINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
# define PIC32MX_I2C2_BRG (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRG_OFFSET)
# define PIC32MX_I2C2_BRGSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
# define PIC32MX_I2C2_BRGCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
# define PIC32MX_I2C2_BRGINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
# define PIC32MX_I2C2_TRN (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRN_OFFSET)
# define PIC32MX_I2C2_TRNCLR (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
# define PIC32MX_I2C2_TRNSET (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
# define PIC32MX_I2C2_TRNINV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
# define PIC32MX_I2C2_RCV (PIC32MX_I2C2_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#endif
#if CHIP_NI2C > 2
# define PIC32MX_I2C3_CON (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CON_OFFSET)
# define PIC32MX_I2C3_CONCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
# define PIC32MX_I2C3_CONSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
# define PIC32MX_I2C3_CONINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
# define PIC32MX_I2C3_STAT (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STAT_OFFSET)
# define PIC32MX_I2C3_STATCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
# define PIC32MX_I2C3_STATSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
# define PIC32MX_I2C3_STATINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
# define PIC32MX_I2C3_ADD (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADD_OFFSET)
# define PIC32MX_I2C3_ADDCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
# define PIC32MX_I2C3_ADDSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
# define PIC32MX_I2C3_ADDINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
# define PIC32MX_I2C3_MSK (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSK_OFFSET)
# define PIC32MX_I2C3_MSKCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
# define PIC32MX_I2C3_MSKSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
# define PIC32MX_I2C3_MSKINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
# define PIC32MX_I2C3_BRG (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRG_OFFSET)
# define PIC32MX_I2C3_BRGSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
# define PIC32MX_I2C3_BRGCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
# define PIC32MX_I2C3_BRGINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
# define PIC32MX_I2C3_TRN (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRN_OFFSET)
# define PIC32MX_I2C3_TRNCLR (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
# define PIC32MX_I2C3_TRNSET (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
# define PIC32MX_I2C3_TRNINV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
# define PIC32MX_I2C3_RCV (PIC32MX_I2C3_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#endif
#if CHIP_NI2C > 3
# define PIC32MX_I2C4_CON (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CON_OFFSET)
# define PIC32MX_I2C4_CONCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
# define PIC32MX_I2C4_CONSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
# define PIC32MX_I2C4_CONINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
# define PIC32MX_I2C4_STAT (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STAT_OFFSET)
# define PIC32MX_I2C4_STATCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
# define PIC32MX_I2C4_STATSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
# define PIC32MX_I2C4_STATINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
# define PIC32MX_I2C4_ADD (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADD_OFFSET)
# define PIC32MX_I2C4_ADDCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
# define PIC32MX_I2C4_ADDSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
# define PIC32MX_I2C4_ADDINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
# define PIC32MX_I2C4_MSK (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSK_OFFSET)
# define PIC32MX_I2C4_MSKCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
# define PIC32MX_I2C4_MSKSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
# define PIC32MX_I2C4_MSKINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
# define PIC32MX_I2C4_BRG (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRG_OFFSET)
# define PIC32MX_I2C4_BRGSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
# define PIC32MX_I2C4_BRGCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
# define PIC32MX_I2C4_BRGINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
# define PIC32MX_I2C4_TRN (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRN_OFFSET)
# define PIC32MX_I2C4_TRNCLR (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
# define PIC32MX_I2C4_TRNSET (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
# define PIC32MX_I2C4_TRNINV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
# define PIC32MX_I2C4_RCV (PIC32MX_I2C4_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#endif
#if CHIP_NI2C > 4
# define PIC32MX_I2C5_CON (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CON_OFFSET)
# define PIC32MX_I2C5_CONCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONCLR_OFFSET)
# define PIC32MX_I2C5_CONSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONSET_OFFSET)
# define PIC32MX_I2C5_CONINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_CONINV_OFFSET)
# define PIC32MX_I2C5_STAT (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STAT_OFFSET)
# define PIC32MX_I2C5_STATCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATCLR_OFFSET)
# define PIC32MX_I2C5_STATSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATSET_OFFSET)
# define PIC32MX_I2C5_STATINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_STATINV_OFFSET)
# define PIC32MX_I2C5_ADD (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADD_OFFSET)
# define PIC32MX_I2C5_ADDCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDCLR_OFFSET)
# define PIC32MX_I2C5_ADDSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDSET_OFFSET)
# define PIC32MX_I2C5_ADDINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_ADDINV_OFFSET)
# define PIC32MX_I2C5_MSK (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSK_OFFSET)
# define PIC32MX_I2C5_MSKCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKCLR_OFFSET)
# define PIC32MX_I2C5_MSKSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKSET_OFFSET)
# define PIC32MX_I2C5_MSKINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_MSKINV_OFFSET)
# define PIC32MX_I2C5_BRG (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRG_OFFSET)
# define PIC32MX_I2C5_BRGSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGSET_OFFSET)
# define PIC32MX_I2C5_BRGCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGCLR_OFFSET)
# define PIC32MX_I2C5_BRGINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_BRGINV_OFFSET)
# define PIC32MX_I2C5_TRN (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRN_OFFSET)
# define PIC32MX_I2C5_TRNCLR (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNCLR_OFFSET)
# define PIC32MX_I2C5_TRNSET (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNSET_OFFSET)
# define PIC32MX_I2C5_TRNINV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_TRNINV_OFFSET)
# define PIC32MX_I2C5_RCV (PIC32MX_I2C5_K1BASE+PIC32MX_I2C_RCV_OFFSET)
#endif
/* Register Bit-Field Definitions ***************************************************/

32
arch/mips/src/pic32mx/pic32mx-ic.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-ic.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -52,11 +52,11 @@
************************************************************************************/
/* Register Offsets *****************************************************************/
#define PIC32MX_IC_CON_OFFSET 0x0000 /* Input Capture X Control Register */
#define PIC32MX_IC_CONCLR_OFFSET 0x0004 /* Input Capture X Control Set Register */
#define PIC32MX_IC_CONSET_OFFSET 0x0008 /* Input Capture X Control Clear Register */
#define PIC32MX_IC_CONINV_OFFSET 0x000c /* Input Capture X Control Invert Register */
#define PIC32MX_IC_BUF_OFFSET 0x0010 /* Input Capture X Buffer Register */
#define PIC32MX_IC_CON_OFFSET 0x0000 /* Input Capture X Control Register */
#define PIC32MX_IC_CONCLR_OFFSET 0x0004 /* Input Capture X Control Set Register */
#define PIC32MX_IC_CONSET_OFFSET 0x0008 /* Input Capture X Control Clear Register */
#define PIC32MX_IC_CONINV_OFFSET 0x000c /* Input Capture X Control Invert Register */
#define PIC32MX_IC_BUF_OFFSET 0x0010 /* Input Capture X Buffer Register */
/* Register Addresses ***************************************************************/
@ -108,16 +108,16 @@
/* Input Capture X Control Register */
#define IC_CON_ICI_SHIFT (0) /* Bits 0-2: Input Capture Mode Select */
#define IC_CON_ICM_MASK (7 << IC_CON_ICI_SHIFT)
# define IC_CON_ICM_DISABLE (0 << IC_CON_ICI_SHIFT) /* Capture disable mode */
# define IC_CON_ICM_EDGE (1 << IC_CON_ICI_SHIFT) /* Edge detect mode */
# define IC_CON_ICM_FALLING (2 << IC_CON_ICI_SHIFT) /* Every falling edge */
# define IC_CON_ICM_RISING (3 << IC_CON_ICI_SHIFT) /* Every rising edge */
# define IC_CON_ICM_4th (4 << IC_CON_ICI_SHIFT) /* Every fourth rising edge */
# define IC_CON_ICM_16th (5 << IC_CON_ICI_SHIFT) /* Every sixteenth rising edge */
# define IC_CON_ICM_TRIGGER (6 << IC_CON_ICI_SHIFT) /* Specified edge first and every edge thereafter */
# define IC_CON_ICM_INTERRUPT (7 << IC_CON_ICI_SHIFT) /* Interrupt-only mode */
#define IC_CON_ICM_SHIFT (0) /* Bits 0-2: Input Capture Mode Select */
#define IC_CON_ICM_MASK (7 << IC_CON_ICM_SHIFT)
# define IC_CON_ICM_DISABLE (0 << IC_CON_ICM_SHIFT) /* Capture disable mode */
# define IC_CON_ICM_EDGE (1 << IC_CON_ICM_SHIFT) /* Edge detect mode */
# define IC_CON_ICM_FALLING (2 << IC_CON_ICM_SHIFT) /* Every falling edge */
# define IC_CON_ICM_RISING (3 << IC_CON_ICM_SHIFT) /* Every rising edge */
# define IC_CON_ICM_4th (4 << IC_CON_ICM_SHIFT) /* Every fourth rising edge */
# define IC_CON_ICM_16th (5 << IC_CON_ICM_SHIFT) /* Every sixteenth rising edge */
# define IC_CON_ICM_TRIGGER (6 << IC_CON_ICM_SHIFT) /* Specified edge first and every edge thereafter */
# define IC_CON_ICM_INTERRUPT (7 << IC_CON_ICM_SHIFT) /* Interrupt-only mode */
#define IC_CON_ICBNE (1 << 3) /* Bit 3: Input Capture Buffer Not Empty Status */
#define IC_CON_ICOV (1 << 4) /* Bit 4: Input Capture */
#define IC_CON_ICI_SHIFT (5) /* Bits 5-6: Interrupt Control */

594
arch/mips/src/pic32mx/pic32mx-int.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-int.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -42,6 +42,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
/****************************************************************************
@ -73,6 +74,12 @@
#define PIC32MX_INT_IFS1CLR_OFFSET 0x0044 /* Interrupt flag status clear register 1 */
#define PIC32MX_INT_IFS1SET_OFFSET 0x0048 /* Interrupt flag status set register 1 */
#define PIC32MX_INT_IFS1INV_OFFSET 0x004c /* Interrupt flag status invert register 1 */
#define PIC32MX_INT_IFS2_OFFSET 0x0050 /* Interrupt flag status register 2 */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IFS2CLR_OFFSET 0x0054 /* Interrupt flag status clear register 2 */
# define PIC32MX_INT_IFS2SET_OFFSET 0x0058 /* Interrupt flag status set register 2 */
# define PIC32MX_INT_IFS2INV_OFFSET 0x005c /* Interrupt flag status invert register 2 */
#endif
#define PIC32MX_INT_IEC_OFFSET(n) (0x0060 + ((n) << 4))
#define PIC32MX_INT_IECCLR_OFFSET(n) (0x0064 + ((n) << 4))
#define PIC32MX_INT_IECSET_OFFSET(n) (0x0068 + ((n) << 4))
@ -85,6 +92,12 @@
#define PIC32MX_INT_IEC1CLR_OFFSET 0x0074 /* Interrupt enable control clear register 1 */
#define PIC32MX_INT_IEC1SET_OFFSET 0x0078 /* Interrupt enable control set register 1 */
#define PIC32MX_INT_IEC1INV_OFFSET 0x007c /* Interrupt enable control invert register 1 */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IEC2_OFFSET 0x0080 /* Interrupt enable control register 2 */
# define PIC32MX_INT_IEC2CLR_OFFSET 0x0084 /* Interrupt enable control clear register 2 */
# define PIC32MX_INT_IEC2SET_OFFSET 0x0088 /* Interrupt enable control set register 2 */
# define PIC32MX_INT_IEC2INV_OFFSET 0x008c /* Interrupt enable control invert register 2 */
#endif
#define PIC32MX_INT_IPC_OFFSET(n) (0x0090 + ((n) << 4))
#define PIC32MX_INT_IPCCLR_OFFSET(n) (0x0094 + ((n) << 4))
#define PIC32MX_INT_IPCSET_OFFSET(n) (0x0098 + ((n) << 4))
@ -129,10 +142,22 @@
#define PIC32MX_INT_IPC9CLR_OFFSET 0x0124 /* Interrupt priority control clear register 9 */
#define PIC32MX_INT_IPC9SET_OFFSET 0x0128 /* Interrupt priority control set register 9 */
#define PIC32MX_INT_IPC9INV_OFFSET 0x012c /* Interrupt priority control invert register 9 */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IPC10_OFFSET 0x0130 /* Interrupt priority control register 10 */
# define PIC32MX_INT_IPC10CLR_OFFSET 0x0134 /* Interrupt priority control clear register 10 */
# define PIC32MX_INT_IPC10SET_OFFSET 0x0138 /* Interrupt priority control set register 10 */
# define PIC32MX_INT_IPC10INV_OFFSET 0x013c /* Interrupt priority control invert register 10 */
#endif
#define PIC32MX_INT_IPC11_OFFSET 0x0140 /* Interrupt priority control register 11 */
#define PIC32MX_INT_IPC11CLR_OFFSET 0x0144 /* Interrupt priority control clear register 11 */
#define PIC32MX_INT_IPC11SET_OFFSET 0x0148 /* Interrupt priority control set register 11 */
#define PIC32MX_INT_IPC11INV_OFFSET 0x014c /* Interrupt priority control invert register 11 */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IPC12_OFFSET 0x0150 /* Interrupt priority control register 12 */
# define PIC32MX_INT_IPC12CLR_OFFSET 0x0154 /* Interrupt priority control clear register 12 */
# define PIC32MX_INT_IPC12SET_OFFSET 0x0158 /* Interrupt priority control set register 12 */
# define PIC32MX_INT_IPC12INV_OFFSET 0x015c /* Interrupt priority control invert register 12 */
#endif
/* Register Addresses *******************************************************/
@ -160,6 +185,12 @@
#define PIC32MX_INT_IFS1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1CLR_OFFSET)
#define PIC32MX_INT_IFS1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1SET_OFFSET)
#define PIC32MX_INT_IFS1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS1INV_OFFSET)
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IFS2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2_OFFSET)
# define PIC32MX_INT_IFS2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2CLR_OFFSET)
# define PIC32MX_INT_IFS2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2SET_OFFSET)
# define PIC32MX_INT_IFS2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IFS2INV_OFFSET)
#endif
#define PIC32MX_INT_IEC(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC_OFFSET(n))
#define PIC32MX_INT_IECCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECCLR_OFFSET(n))
#define PIC32MX_INT_IECSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IECSET_OFFSET(n))
@ -172,6 +203,12 @@
#define PIC32MX_INT_IEC1CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1CLR_OFFSET)
#define PIC32MX_INT_IEC1SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1SET_OFFSET)
#define PIC32MX_INT_IEC1INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC1INV_OFFSET)
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IEC2 (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2_OFFSET)
# define PIC32MX_INT_IEC2CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2CLR_OFFSET)
# define PIC32MX_INT_IEC2SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2SET_OFFSET)
# define PIC32MX_INT_IEC2INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IEC2INV_OFFSET)
#endif
#define PIC32MX_INT_IPC(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC_OFFSET(n))
#define PIC32MX_INT_IPCCLR(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCCLR_OFFSET(n))
#define PIC32MX_INT_IPCSET(n) (PIC32MX_INT_K1BASE+PIC32MX_INT_IPCSET_OFFSET(n))
@ -216,10 +253,22 @@
#define PIC32MX_INT_IPC9CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9CLR_OFFSET)
#define PIC32MX_INT_IPC9SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9SET_OFFSET)
#define PIC32MX_INT_IPC9INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC9INV_OFFSET)
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IPC10 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10_OFFSET)
# define PIC32MX_INT_IPC10CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10CLR_OFFSET)
# define PIC32MX_INT_IPC10SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10SET_OFFSET)
# define PIC32MX_INT_IPC10INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC10INV_OFFSET)
#endif
#define PIC32MX_INT_IPC11 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11_OFFSET)
#define PIC32MX_INT_IPC11CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11CLR_OFFSET)
#define PIC32MX_INT_IPC11SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11SET_OFFSET)
#define PIC32MX_INT_IPC11INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC11INV_OFFSET)
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define PIC32MX_INT_IPC12 (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12_OFFSET)
# define PIC32MX_INT_IPC12CLR (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12CLR_OFFSET)
# define PIC32MX_INT_IPC12SET (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12SET_OFFSET)
# define PIC32MX_INT_IPC12INV (PIC32MX_INT_K1BASE+PIC32MX_INT_IPC12INV_OFFSET)
#endif
/* Register Bit-Field Definitions *******************************************/
@ -257,63 +306,191 @@
/* Interrupt flag status register 0 and Interrupt enable control register 0 */
#define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */
#define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */
#define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */
#define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */
#define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */
#define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */
#define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */
#define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */
#define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */
#define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */
#define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */
#define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */
#define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */
#define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */
#define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */
#define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */
#define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */
#define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */
#define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */
#define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */
#define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */
#define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */
#define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */
#define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 */
#define INT_SPI1TX (1 << 24) /* Vector: 23, " " */
#define INT_SPI1RX (1 << 25) /* Vector: 23, " " */
#define INT_U1E (1 << 26) /* Vector: 24, UART1 */
#define INT_U1RX (1 << 27) /* Vector: 24, " " */
#define INT_U1TX (1 << 28) /* Vector: 24, " " */
#define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 */
#define INT_I2C1S (1 << 30) /* Vector: 25, " " */
#define INT_I2C1M (1 << 31) /* Vector: 25, " " */
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
# define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */
# define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */
# define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */
# define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */
# define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */
# define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */
# define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */
# define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */
# define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */
# define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */
# define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */
# define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */
# define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */
# define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */
# define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */
# define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */
# define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */
# define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */
# define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */
# define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */
# define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */
# define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */
# define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */
# define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 Error */
# define INT_SPI1TX (1 << 24) /* Vector: 23, " " Transfer done */
# define INT_SPI1RX (1 << 25) /* Vector: 23, " " Receive done */
# define INT_U1E (1 << 26) /* Vector: 24, UART1 Error */
# define INT_U1RX (1 << 27) /* Vector: 24, " " Receiver */
# define INT_U1TX (1 << 28) /* Vector: 24, " " Transmitter */
# define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 Bus collision event */
# define INT_I2C1S (1 << 30) /* Vector: 25, " " Slave event */
# define INT_I2C1M (1 << 31) /* Vector: 25, " " Master event */
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define INT_CT (1 << 0) /* Vector: 0, Core Timer Interrupt */
# define INT_CS0 (1 << 1) /* Vector: 1, Core Software Interrupt 0 */
# define INT_CS1 (1 << 2) /* Vector: 2, Core Software Interrupt 1 */
# define INT_INT0 (1 << 3) /* Vector: 3, External Interrupt 0 */
# define INT_T1 (1 << 4) /* Vector: 4, Timer 1 */
# define INT_IC1 (1 << 5) /* Vector: 5, Input Capture 1 */
# define INT_OC1 (1 << 6) /* Vector: 6, Output Compare 1 */
# define INT_INT1 (1 << 7) /* Vector: 7, External Interrupt 1 */
# define INT_T2 (1 << 8) /* Vector: 8, Timer 2 */
# define INT_IC2 (1 << 9) /* Vector: 9, Input Capture 2 */
# define INT_OC2 (1 << 10) /* Vector: 10, Output Compare 2 */
# define INT_INT2 (1 << 11) /* Vector: 11, External Interrupt 2 */
# define INT_T3 (1 << 12) /* Vector: 12, Timer 3 */
# define INT_IC3 (1 << 13) /* Vector: 13, Input Capture 3 */
# define INT_OC3 (1 << 14) /* Vector: 14, Output Compare 3 */
# define INT_INT3 (1 << 15) /* Vector: 15, External Interrupt 3 */
# define INT_T4 (1 << 16) /* Vector: 16, Timer 4 */
# define INT_IC4 (1 << 17) /* Vector: 17, Input Capture 4 */
# define INT_OC4 (1 << 18) /* Vector: 18, Output Compare 4 */
# define INT_INT4 (1 << 19) /* Vector: 19, External Interrupt 4 */
# define INT_T5 (1 << 20) /* Vector: 20, Timer 5 */
# define INT_IC5 (1 << 21) /* Vector: 21, Input Capture 5 */
# define INT_OC5 (1 << 22) /* Vector: 22, Output Compare 5 */
# define INT_SPI1E (1 << 23) /* Vector: 23, SPI1 Error */
# define INT_SPI1TX (1 << 24) /* Vector: 23, " " Transfer done */
# define INT_SPI1RX (1 << 25) /* Vector: 23, " " Receive done */
# define INT_26 (1 << 26) /* Vector: 24, UART1, SPI3, I2C3 */
# define INT_U1E (1 << 26) /* Vector: 24, UART1 Error */
# define INT_SPI3E (1 << 26) /* Vector: 24, SPI3 Fault */
# define INT_I2C3B (1 << 26) /* Vector: 24, I2C3 Bus collision event */
# define INT_27 (1 << 27) /* Vector: 24, UART1, SPI3, I2C3 */
# define INT_U1RX (1 << 27) /* Vector: 24, UART1 Receiver */
# define INT_SPI3RX (1 << 27) /* Vector: 24, SPI3 Receive done */
# define INT_I2C3S (1 << 27) /* Vector: 24, I2C3 Slave event */
# define INT_28 (1 << 28) /* Vector: 24, UART1, SPI3, I2C3 */
# define INT_U1TX (1 << 28) /* Vector: 24, UART1 Transmitter */
# define INT_SPI3TX (1 << 28) /* Vector: 24, SPI3 Transfer done */
# define INT_I2C3M (1 << 28) /* Vector: 24, I2C3 Master event */
# define INT_I2C1B (1 << 29) /* Vector: 25, I2C1 Bus collision event */
# define INT_I2C1S (1 << 30) /* Vector: 25, " " Slave event */
# define INT_I2C1M (1 << 31) /* Vector: 25, " " Master event */
#else
# error "Unknown PIC32MX family
#endif
/* Interrupt flag status register 1 and Interrupt enable control register 1 */
#define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */
#define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */
#define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */
#define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */
#define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */
#define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 */
#define INT_SPI2TX (1 << 6) /* Vector: 31, " " */
#define INT_SPI2RX (1 << 7) /* Vector: 31, " " */
#define INT_U2E (1 << 8) /* Vector: 32, UART2 */
#define INT_U2RX (1 << 9) /* Vector: 32, " " */
#define INT_U2TX (1 << 10) /* Vector: 32, " " */
#define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 */
#define INT_I2C2S (1 << 12) /* Vector: 33, " " */
#define INT_I2C2M (1 << 13) /* Vector: 33, " " */
#define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */
#define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */
#define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */
#define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */
#define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */
#define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */
#define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */
#define INT_USB (1 << 25) /* Vector: 45, USB */
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
# define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */
# define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */
# define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */
# define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */
# define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */
# define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 Error */
# define INT_SPI2TX (1 << 6) /* Vector: 31, " " Transfer done */
# define INT_SPI2RX (1 << 7) /* Vector: 31, " " Receive done*/
# define INT_U2E (1 << 8) /* Vector: 32, UART2 Error */
# define INT_U2RX (1 << 9) /* Vector: 32, " " Receiver */
# define INT_U2TX (1 << 10) /* Vector: 32, " " Transmitter */
# define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 Bus collision event */
# define INT_I2C2S (1 << 12) /* Vector: 33, " " Master event */
# define INT_I2C2M (1 << 13) /* Vector: 33, " " Slave event */
# define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */
# define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */
# define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */
# define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */
# define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */
# define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */
# define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */
# define INT_USB (1 << 25) /* Vector: 45, USB Interrupt */
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define INT_CN (1 << 0) /* Vector: 26, Input Change Interrupt */
# define INT_AD1 (1 << 1) /* Vector: 27, ADC1 Convert Done */
# define INT_PMP (1 << 2) /* Vector: 28, Parallel Master Port */
# define INT_CMP1 (1 << 3) /* Vector: 29, Comparator Interrupt */
# define INT_CMP2 (1 << 4) /* Vector: 30, Comparator Interrupt */
# define INT_37 (1 << 5) /* Vector: 31, UART3, SPI2, I2C4 */
# define INT_U3E (1 << 5) /* Vector: 31, UART3 Error */
# define INT_SPI2E (1 << 5) /* Vector: 31, SPI2 Fault */
# define INT_I2C4B (1 << 5) /* Vector: 31, I2C4 Bus collision event */
# define INT_38 (1 << 6) /* Vector: 31, UART3, SPI2, I2C4 */
# define INT_U3RX (1 << 6) /* Vector: 31, UART3 Receiver */
# define INT_SPI2RX (1 << 6) /* Vector: 31, SPI2 Receive done */
# define INT_I2C4S (1 << 6) /* Vector: 31, I2C4 Slave event */
# define INT_39 (1 << 7) /* Vector: 31, UART3, SPI2, I2C4 */
# define INT_U3TX (1 << 7) /* Vector: 31, UART3 Transmitter */
# define INT_SPI2TX (1 << 7) /* Vector: 31, SPI2 Transfer done */
# define INT_I2C4M (1 << 7) /* Vector: 31, I2C4 Master event */
# define INT_40 (1 << 8) /* Vector: 32, UART2, SPI4, I2C5 */
# define INT_U2E (1 << 8) /* Vector: 32, UART2 Error */
# define INT_SPI4E (1 << 8) /* Vector: 32, SPI4 Fault */
# define INT_I2C5B (1 << 8) /* Vector: 32, I2C5 Bus collision event */
# define INT_41 (1 << 9) /* Vector: 32, UART2, SPI4, I2C5 */
# define INT_U2RX (1 << 9) /* Vector: 32, UART2 Receiver */
# define INT_SPI4RX (1 << 9) /* Vector: 32, SPI4 Receive done */
# define INT_I2C5S (1 << 9) /* Vector: 32, I2C5 Slave event */
# define INT_42 (1 << 10) /* Vector: 32, UART2, SPI4, I2C5 */
# define INT_U2TX (1 << 10) /* Vector: 32, UART2 Transmitter */
# define INT_SPI4TX (1 << 10) /* Vector: 32, SPI4 Transfer done */
# define INT_I2C5M (1 << 10) /* Vector: 32, I2C5 Master event */
# define INT_I2C2B (1 << 11) /* Vector: 33, I2C2 Bus collision event */
# define INT_I2C2S (1 << 12) /* Vector: 33, " " Master event */
# define INT_I2C2M (1 << 13) /* Vector: 33, " " Slave event */
# define INT_FSCM (1 << 14) /* Vector: 34, Fail-Safe Clock Monitor */
# define INT_RTCC (1 << 15) /* Vector: 35, Real-Time Clock and Calendar */
# define INT_DMA0 (1 << 16) /* Vector: 36, DMA Channel 0 */
# define INT_DMA1 (1 << 17) /* Vector: 37, DMA Channel 1 */
# define INT_DMA2 (1 << 18) /* Vector: 38, DMA Channel 2 */
# define INT_DMA3 (1 << 19) /* Vector: 39, DMA Channel 3 */
# define INT_DMA4 (1 << 20) /* Vector: 40, DMA Channel 3 */
# define INT_DMA5 (1 << 21) /* Vector: 41, DMA Channel 3 */
# define INT_DMA6 (1 << 22) /* Vector: 42, DMA Channel 3 */
# define INT_DMA7 (1 << 23) /* Vector: 43, DMA Channel 3 */
# define INT_FCE (1 << 24) /* Vector: 44, Flash Control Event */
# define INT_USB (1 << 25) /* Vector: 45, USB Interrupt */
# define INT_CAN1 (1 << 26) /* Vector: 46, Control Area Network 1 */
# define INT_CAN2 (1 << 27) /* Vector: 47, Control Area Network 2 */
# define INT_ETH (1 << 28) /* Vector: 48, Ethernet interrupt */
# define INT_IC1E (1 << 29) /* Vector: 5, Input capture 1 error */
# define INT_IC2E (1 << 30) /* Vector: 9, Input capture 1 error */
# define INT_IC3E (1 << 31) /* Vector: 13, Input capture 1 error */
#else
# error "Unknown PIC32MX family
#endif
/* Interrupt flag status register 2 and Interrupt enable control register 2 */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define INT_IC4E (1 << 0) /* Vector: 17, Input capture 1 error */
# define INT_IC5E (1 << 1) /* Vector: 21, Input capture 1 error */
# define INT_PMPE (1 << 2) /* Vector: 28, Parallel master port error */
# define INT_U4E (1 << 3) /* Vector: 49, UART4 Error */
# define INT_U4RX (1 << 4) /* Vector: 49, UART4 Receiver */
# define INT_U4TX (1 << 5) /* Vector: 49, UART4 Transmitter */
# define INT_U6E (1 << 6) /* Vector: 50, UART6 Error */
# define INT_U6RX (1 << 7) /* Vector: 50, UART6 Receiver */
# define INT_U6TX (1 << 8) /* Vector: 50, UART6 Transmitter */
# define INT_U5E (1 << 9) /* Vector: 51, UART5 Error */
# define INT_U5RX (1 << 10) /* Vector: 51, UART5 Receiver */
# define INT_U5TX (1 << 11) /* Vector: 51, UART5 Transmitter */
#endif
/* Interrupt priority control register 0-11 */
@ -426,82 +603,245 @@
#define INT_IPC5_SPI1IP_SHIFT (26) /* Bits 26-28, Vector: 23, SPI1 */
#define INT_IPC5_SPI1IP_MASK (7 << INT_IPC5_SPI1IP_SHIFT)
#define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */
#define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
#define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */
#define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
#define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */
#define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT)
#define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */
#define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT)
#define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */
#define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT)
#define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */
#define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT)
#define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */
#define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT)
#define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */
#define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT)
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
#define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */
#define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT)
#define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */
#define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT)
#define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */
#define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT)
#define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */
#define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT)
#define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */
#define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT)
#define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */
#define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT)
#define INT_IPC7_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */
#define INT_IPC7_SPI2IS_MASK (3 << INT_IPC7_SPI2IS_SHIFT)
#define INT_IPC7_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */
#define INT_IPC7_SPI2IP_MASK (7 << INT_IPC7_SPI2IP_SHIFT)
# define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */
# define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
# define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */
# define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
# define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */
# define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT)
# define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */
# define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT)
# define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */
# define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT)
# define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */
# define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT)
# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */
# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT)
# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */
# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT)
#define INT_IPC8_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */
#define INT_IPC8_U2IS_MASK (3 << INT_IPC8_U2IS_SHIFT)
#define INT_IPC8_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */
#define INT_IPC8_U2IP_MASK (7 << INT_IPC8_U2IP_SHIFT)
#define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */
#define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT)
#define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */
#define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT)
#define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */
#define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT)
#define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */
#define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT)
#define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */
#define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT)
#define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */
#define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT)
# define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */
# define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT)
# define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */
# define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT)
# define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */
# define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT)
# define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */
# define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT)
# define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */
# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT)
# define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */
# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT)
# define INT_IPC7_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */
# define INT_IPC7_SPI2IS_MASK (3 << INT_IPC7_SPI2IS_SHIFT)
# define INT_IPC7_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */
# define INT_IPC7_SPI2IP_MASK (7 << INT_IPC7_SPI2IP_SHIFT)
#define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */
#define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
#define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */
#define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
#define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */
#define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
#define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */
#define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
#define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */
#define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
#define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */
#define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
#define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */
#define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
#define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */
#define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
# define INT_IPC8_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */
# define INT_IPC8_U2IS_MASK (3 << INT_IPC8_U2IS_SHIFT)
# define INT_IPC8_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */
# define INT_IPC8_U2IP_MASK (7 << INT_IPC8_U2IP_SHIFT)
# define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */
# define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT)
# define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */
# define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT)
# define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */
# define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT)
# define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */
# define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT)
# define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */
# define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT)
# define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */
# define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT)
#define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */
#define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
#define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */
#define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
#define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */
#define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT)
#define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */
#define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT)
# define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */
# define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
# define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */
# define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
# define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */
# define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
# define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */
# define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
# define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */
# define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
# define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */
# define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
# define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */
# define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
# define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */
# define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
# define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */
# define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
# define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */
# define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
# define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */
# define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT)
# define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */
# define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT)
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define INT_IPC6_VEC24IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1, SPI3, I2C3 */
# define INT_IPC6_VEC24IS_MASK (3 << INT_IPC6_INT26IS_SHIFT)
# define INT_IPC6_U1IS_SHIFT (0) /* Bits 0-1, Vector: 24, UART1 */
# define INT_IPC6_U1IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
# define INT_IPC6_SPI3IS_SHIFT (0) /* Bits 0-1, Vector: 24, SPI3 */
# define INT_IPC6_SPI3IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT)
# define INT_IPC6_I2C3IS_SHIFT (0) /* Bits 0-1, Vector: 24, I2C3 */
# define INT_IPC6_I2C3IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT)
# define INT_IPC6_VEC24IP_SHIFT (0) /* Bits 2-4, Vector: 24, UART1, SPI3, I2C3 */
# define INT_IPC6_VEC24IP_MASK (7 << INT_IPC6_INT26IP_SHIFT)
# define INT_IPC6_U1IP_SHIFT (2) /* Bits 2-4, Vector: 24, UART1 */
# define INT_IPC6_U1IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
# define INT_IPC6_SPI3IP_SHIFT (2) /* Bits 2-4, Vector: 24, SPI3 */
# define INT_IPC6_SPI3IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT)
# define INT_IPC6_I2C3IP_SHIFT (2) /* Bits 2-4, Vector: 24, I2C3 */
# define INT_IPC6_I2C3IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT)
# define INT_IPC6_I2C1IS_SHIFT (8) /* Bits 8-9, Vector: 25, I2C1 */
# define INT_IPC6_I2C1IS_MASK (3 << INT_IPC6_I2C1IS_SHIFT)
# define INT_IPC6_I2C1IP_SHIFT (10) /* Bits 10-12, Vector: 25, I2C1 */
# define INT_IPC6_I2C1IP_MASK (7 << INT_IPC6_I2C1IP_SHIFT)
# define INT_IPC6_CNIS_SHIFT (16) /* Bits 16-17, Vector: 26, Input Change Interrupt */
# define INT_IPC6_CNIS_MASK (3 << INT_IPC6_CNIS_SHIFT)
# define INT_IPC6_CNIP_SHIFT (18) /* Bits 18-20, Vector: 26, Input Change Interrupt */
# define INT_IPC6_CNIP_MASK (7 << INT_IPC6_CNIP_SHIFT)
# define INT_IPC6_AD1IS_SHIFT (24) /* Bits 24-25, Vector: 27, ADC1 Convert Done */
# define INT_IPC6_AD1IS_MASK (3 << INT_IPC6_AD1IS_SHIFT)
# define INT_IPC6_AD1IP_SHIFT (26) /* Bits 26-28, Vector: 27, ADC1 Convert Done */
# define INT_IPC6_AD1IP_MASK (7 << INT_IPC6_AD1IP_SHIFT)
# define INT_IPC7_PMPIS_SHIFT (0) /* Bits 0-1, Vector: 28, Parallel Master Port */
# define INT_IPC7_PMPIS_MASK (3 << INT_IPC7_PMPIS_SHIFT)
# define INT_IPC7_PMPIP_SHIFT (2) /* Bits 2-4, Vector: 28, Parallel Master Port */
# define INT_IPC7_PMPIP_MASK (7 << INT_IPC7_PMPIP_SHIFT)
# define INT_IPC7_CMP1IS_SHIFT (8) /* Bits 8-9, Vector: 29, Comparator Interrupt */
# define INT_IPC7_CMP1IS_MASK (3 << INT_IPC7_CMP1IS_SHIFT)
# define INT_IPC7_CMP1IP_SHIFT (10) /* Bits 10-12, Vector: 29, Comparator Interrupt */
# define INT_IPC7_CMP1IP_MASK (7 << INT_IPC7_CMP1IP_SHIFT)
# define INT_IPC7_CMP2IS_SHIFT (16) /* Bits 16-17, Vector: 30, Comparator Interrupt */
# define INT_IPC7_CMP2IS_MASK (3 << INT_IPC7_CMP2IS_SHIFT)
# define INT_IPC7_CMP2IP_SHIFT (18) /* Bits 18-20, Vector: 30, Comparator Interrupt */
# define INT_IPC7_CMP2IP_MASK (7 << INT_IPC7_CMP2IP_SHIFT)
# define INT_IPC6_VEC31IS_SHIFT (24) /* Bits 24-25, Vector: 31, UART3, SPI2, I2C4 */
# define INT_IPC6_VEC31IS_MASK (3 << INT_IPC6_INT26IS_SHIFT)
# define INT_IPC6_U3IS_SHIFT (24) /* Bits 24-25, Vector: 31, UART3 */
# define INT_IPC6_U3IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
# define INT_IPC6_SPI2IS_SHIFT (24) /* Bits 24-25, Vector: 31, SPI2 */
# define INT_IPC6_SPI2IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT)
# define INT_IPC6_I2C4IS_SHIFT (24) /* Bits 24-25, Vector: 31, I2C4 */
# define INT_IPC6_I2C4IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT)
# define INT_IPC6_VEC31IP_SHIFT (26) /* Bits 26-28, Vector: 31, UART3, SPI2, I2C4 */
# define INT_IPC6_VEC31IP_MASK (7 << INT_IPC6_INT26IP_SHIFT)
# define INT_IPC6_U3IP_SHIFT (26) /* Bits 26-28, Vector: 31, UART3 */
# define INT_IPC6_U3IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
# define INT_IPC6_SPI2IP_SHIFT (26) /* Bits 26-28, Vector: 31, SPI2 */
# define INT_IPC6_SPI2IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT)
# define INT_IPC6_I2C4IP_SHIFT (26) /* Bits 26-28, Vector: 31, I2C4 */
# define INT_IPC6_I2C4IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT)
# define INT_IPC6_VEC32IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2, SPI4, I2C5 */
# define INT_IPC6_VEC32IS_MASK (3 << INT_IPC6_INT26IS_SHIFT)
# define INT_IPC6_U2IS_SHIFT (0) /* Bits 0-1, Vector: 32, UART2 */
# define INT_IPC6_U2IS_MASK (3 << INT_IPC6_U1IS_SHIFT)
# define INT_IPC6_SPI4IS_SHIFT (0) /* Bits 0-1, Vector: 32, SPI4 */
# define INT_IPC6_SPI4IS_MASK (3 << INT_IPC6_SPI3IS_SHIFT)
# define INT_IPC6_I2C5IS_SHIFT (0) /* Bits 0-1, Vector: 32, I2C5 */
# define INT_IPC6_I2C5IS_MASK (3 << INT_IPC6_I2C3IS_SHIFT)
# define INT_IPC6_VEC32IP_SHIFT (0) /* Bits 2-4, Vector: 32, UART2, SPI4, I2C5 */
# define INT_IPC6_VEC32IP_MASK (7 << INT_IPC6_INT26IP_SHIFT)
# define INT_IPC6_U2IP_SHIFT (2) /* Bits 2-4, Vector: 32, UART2 */
# define INT_IPC6_U2IP_MASK (7 << INT_IPC6_U1IP_SHIFT)
# define INT_IPC6_SPI4IP_SHIFT (2) /* Bits 2-4, Vector: 32, SPI4 */
# define INT_IPC6_SPI4IP_MASK (7 << INT_IPC6_SPI3IP_SHIFT)
# define INT_IPC6_I2C5IP_SHIFT (2) /* Bits 2-4, Vector: 32, I2C5 */
# define INT_IPC6_I2C5IP_MASK (7 << INT_IPC6_I2C3IP_SHIFT)
# define INT_IPC8_I2C2IS_SHIFT (8) /* Bits 8-9, Vector: 33, I2C2 */
# define INT_IPC8_I2C2IS_MASK (3 << INT_IPC8_I2C2IS_SHIFT)
# define INT_IPC8_I2C2IP_SHIFT (10) /* Bits 10-12, Vector: 33, I2C2 */
# define INT_IPC8_I2C2IP_MASK (7 << INT_IPC8_I2C2IP_SHIFT)
# define INT_IPC8_FSCMIS_SHIFT (16) /* Bits 16-17, Vector: 34, Fail-Safe Clock Monitor */
# define INT_IPC8_FSCMIS_MASK (3 << INT_IPC8_FSCMIS_SHIFT)
# define INT_IPC8_FSCMIP_SHIFT (18) /* Bits 18-20, Vector: 34, Fail-Safe Clock Monitor */
# define INT_IPC8_FSCMIP_MASK (7 << INT_IPC8_FSCMIP_SHIFT)
# define INT_IPC8_RTCCIS_SHIFT (24) /* Bits 24-25, Vector: 35, Real-Time Clock and Calendar */
# define INT_IPC8_RTCCIS_MASK (3 << INT_IPC8_RTCCIS_SHIFT)
# define INT_IPC8_RTCCIP_SHIFT (26) /* Bits 26-28, Vector: 35, Real-Time Clock and Calendar */
# define INT_IPC8_RTCCIP_MASK (7 << INT_IPC8_RTCCIP_SHIFT)
# define INT_IPC9_DMA0IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 0 */
# define INT_IPC9_DMA0IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
# define INT_IPC9_DMA0IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 0 */
# define INT_IPC9_DMA0IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
# define INT_IPC9_DMA1IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 1 */
# define INT_IPC9_DMA1IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
# define INT_IPC9_DMA1IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 1 */
# define INT_IPC9_DMA1IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
# define INT_IPC9_DMA2IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 2 */
# define INT_IPC9_DMA2IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
# define INT_IPC9_DMA2IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 2 */
# define INT_IPC9_DMA2IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
# define INT_IPC9_DMA3IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 3 */
# define INT_IPC9_DMA3IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
# define INT_IPC9_DMA3IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 3 */
# define INT_IPC9_DMA3IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
# define INT_IPC10_DMA4IS_SHIFT (0) /* Bits 0-1, Vector: 36, DMA Channel 4 */
# define INT_IPC10_DMA4IS_MASK (3 << INT_IPC9_DMA0IS_SHIFT)
# define INT_IPC10_DMA4IP_SHIFT (2) /* Bits 2-4, Vector: 36, DMA Channel 4 */
# define INT_IPC10_DMA4IP_MASK (7 << INT_IPC9_DMA0IP_SHIFT)
# define INT_IPC10_DMA5IS_SHIFT (8) /* Bits 8-9, Vector: 37, DMA Channel 5 */
# define INT_IPC10_DMA5IS_MASK (3 << INT_IPC9_DMA1IS_SHIFT)
# define INT_IPC10_DMA5IP_SHIFT (10) /* Bits 10-12, Vector: 37, DMA Channel 5 */
# define INT_IPC10_DMA5IP_MASK (7 << INT_IPC9_DMA1IP_SHIFT)
# define INT_IPC10_DMA6IS_SHIFT (16) /* Bits 16-17, Vector: 38, DMA Channel 6 */
# define INT_IPC10_DMA6IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
# define INT_IPC10_DMA6IP_SHIFT (18) /* Bits 18-20, Vector: 38, DMA Channel 6 */
# define INT_IPC10_DMA6IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
# define INT_IPC10_DMA7IS_SHIFT (24) /* Bits 24-25, Vector: 39, DMA Channel 7 */
# define INT_IPC10_DMA7IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
# define INT_IPC10_DMA7IP_SHIFT (26) /* Bits 26-28, Vector: 39, DMA Channel 7 */
# define INT_IPC10_DMA7IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
# define INT_IPC11_FCEIS_SHIFT (0) /* Bits 0-1, Vector: 44, Flash Control Event */
# define INT_IPC11_FCEIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
# define INT_IPC11_FCEIP_SHIFT (2) /* Bits 2-4, Vector: 44, Flash Control Event */
# define INT_IPC11_FCEIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
# define INT_IPC11_USBIS_SHIFT (8) /* Bits 8-9, Vector: 45, USB */
# define INT_IPC11_USBIS_MASK (3 << INT_IPC11_USBIS_SHIFT)
# define INT_IPC11_USBIP_SHIFT (10) /* Bits 10-12, Vector: 45, USB */
# define INT_IPC11_USBIP_MASK (7 << INT_IPC11_USBIP_SHIFT)
# define INT_IPC11_CAN1IS_SHIFT (16) /* Bits 16-17, Vector: 46, Controller area network 1 */
# define INT_IPC11_CAN1IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
# define INT_IPC11_CAN1IP_SHIFT (18) /* Bits 18-20, Vector: 46, Controller area network 1 */
# define INT_IPC11_CAN1IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
# define INT_IPC11_CAN2IS_SHIFT (24) /* Bits 24-25, Vector: 47, Controller area network 2 */
# define INT_IPC11_CAN2IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
# define INT_IPC11_CAN2IP_SHIFT (26) /* Bits 26-28, Vector: 47, Controller area network 2 */
# define INT_IPC11_CAN2IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
# define INT_IPC12_ETHIS_SHIFT (0) /* Bits 0-1, Vector: 48, Ethernet interrupt */
# define INT_IPC12_ETHIS_MASK (3 << INT_IPC11_FCEIS_SHIFT)
# define INT_IPC12_ETHIP_SHIFT (2) /* Bits 2-4, Vector: 48, Ethernet interrupt */
# define INT_IPC12_ETHIP_MASK (7 << INT_IPC11_FCEIP_SHIFT)
# define INT_IPC12_U4IS_SHIFT (8) /* Bits 8-9, Vector: 49, UART4 */
# define INT_IPC12_U4IS_MASK (3 << INT_IPC11_USBIS_SHIFT)
# define INT_IPC12_U4IP_SHIFT (10) /* Bits 10-12, Vector: 49, UART4 */
# define INT_IPC12_U4IP_MASK (7 << INT_IPC11_USBIP_SHIFT)
# define INT_IPC12_U6IS_SHIFT (16) /* Bits 16-17, Vector: 50, UART6 */
# define INT_IPC12_U6IS_MASK (3 << INT_IPC9_DMA2IS_SHIFT)
# define INT_IPC12_U6IP_SHIFT (18) /* Bits 18-20, Vector: 50, UART6 */
# define INT_IPC12_U6IP_MASK (7 << INT_IPC9_DMA2IP_SHIFT)
# define INT_IPC12_U5IS_SHIFT (24) /* Bits 24-25, Vector: 51, UART5 */
# define INT_IPC12_U5IS_MASK (3 << INT_IPC9_DMA3IS_SHIFT)
# define INT_IPC12_U5IP_SHIFT (26) /* Bits 26-28, Vector: 51, UART5 */
# define INT_IPC12_U5IP_MASK (7 << INT_IPC9_DMA3IP_SHIFT)
#else
# error "Unknown PIC32MX family
#endif
/****************************************************************************
* Public Types

56
arch/mips/src/pic32mx/pic32mx-irq.c
View File

@ -97,6 +97,9 @@ void up_irqinitialize(void)
putreg32(0xffff, PIC32MX_INT_IEC0CLR);
putreg32(0xffff, PIC32MX_INT_IEC1CLR);
#ifdef PIC32MX_INT_IEC1CLR
putreg32(0xffff, PIC32MX_INT_IEC2CLR);
#endif
/* Set all interrupts to the default (middle) priority */
@ -163,8 +166,8 @@ void up_disable_irq(int irq)
/* Disable the interrupt by clearing the associated bit in the IEC register */
DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
if (irq >= PIC32MX_IRQSRC0_FIRST)
DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
if (irq >= PIC32MX_IRQSRC_FIRST)
{
if (irq <= PIC32MX_IRQSRC0_LAST)
{
@ -180,6 +183,15 @@ void up_disable_irq(int irq)
regaddr = PIC32MX_INT_IEC1CLR;
bitno -= PIC32MX_IRQSRC1_FIRST;
}
#ifdef PIC32MX_IRQSRC2_FIRST
else if (irq <= PIC32MX_IRQSRC2_LAST)
{
/* Use IEC2 */
regaddr = PIC32MX_INT_IEC2CLR;
bitno -= PIC32MX_IRQSRC2_FIRST;
}
#endif
else
{
/* Value out of range.. just ignore */
@ -208,8 +220,8 @@ void up_enable_irq(int irq)
/* Enable the interrupt by setting the associated bit in the IEC register */
DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
if (irq >= PIC32MX_IRQSRC0_FIRST)
DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
if (irq >= PIC32MX_IRQSRC_FIRST)
{
if (irq <= PIC32MX_IRQSRC0_LAST)
{
@ -225,6 +237,15 @@ void up_enable_irq(int irq)
regaddr = PIC32MX_INT_IEC1SET;
bitno -= PIC32MX_IRQSRC1_FIRST;
}
#ifdef PIC32MX_IRQSRC2_FIRST
else if (irq <= PIC32MX_IRQSRC2_LAST)
{
/* Use IEC2 */
regaddr = PIC32MX_INT_IEC2SET;
bitno -= PIC32MX_IRQSRC2_FIRST;
}
#endif
else
{
/* Value out of range.. just ignore */
@ -259,8 +280,8 @@ bool up_pending_irq(int irq)
* priority level otherwise recursive interrupts would occur.
*/
DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
if (irq >= PIC32MX_IRQSRC0_FIRST)
DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
if (irq >= PIC32MX_IRQSRC_FIRST)
{
if (irq <= PIC32MX_IRQSRC0_LAST)
{
@ -278,6 +299,16 @@ bool up_pending_irq(int irq)
iecaddr = PIC32MX_INT_IEC1;
bitno -= PIC32MX_IRQSRC1_FIRST;
}
#ifdef PIC32MX_IRQSRC2_FIRST
else if (irq <= PIC32MX_IRQSRC2_LAST)
{
/* Use IFS2 */
ifsaddr = PIC32MX_INT_IFS2;
iecaddr = PIC32MX_INT_IEC2;
bitno -= PIC32MX_IRQSRC2_FIRST;
}
#endif
else
{
/* Value out of range.. just ignore */
@ -315,8 +346,8 @@ void up_clrpend_irq(int irq)
* priority level otherwise recursive interrupts would occur.
*/
DEBUGASSERT(irq >= PIC32MX_IRQSRC0_FIRST && irq <= PIC32MX_IRQSRC1_LAST)
if (irq >= PIC32MX_IRQSRC0_FIRST)
DEBUGASSERT(irq >= PIC32MX_IRQSRC_FIRST && irq <= PIC32MX_IRQSRC_LAST)
if (irq >= PIC32MX_IRQSRC_FIRST)
{
if (irq <= PIC32MX_IRQSRC0_LAST)
{
@ -332,6 +363,15 @@ void up_clrpend_irq(int irq)
regaddr = PIC32MX_INT_IFS1CLR;
bitno -= PIC32MX_IRQSRC1_FIRST;
}
#ifdef PIC32MX_IRQSRC2_FIRST
else if (irq <= PIC32MX_IRQSRC2_LAST)
{
/* Use IFS2 */
regaddr = PIC32MX_INT_IFS2CLR;
bitno -= PIC32MX_IRQSRC2_FIRST;
}
#endif
else
{
/* Value out of range.. just ignore */

171
arch/mips/src/pic32mx/pic32mx-memorymap.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-memorymap.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -52,7 +52,7 @@
* PIC32MX5xx/6xx/7xx families.
*/
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) ||
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || \
defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
/* Physical Memory Map **************************************************************/
@ -75,6 +75,9 @@
# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE)
# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
#else
# error "Memory map unknown for this PIC32 chip"
#endif
/* Register Base Addresses **********************************************************/
@ -100,21 +103,21 @@
/* Input Capture 1-5 Register Base Addresses */
# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
/* Output Compare 1-5 Register Base Addresses */
# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1))
# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1))
# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
/* I2C 1-2 Register Base Addresses */
@ -212,7 +215,145 @@
# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# error "Missing definitions"
/* Watchdog Register Base Address */
# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000)
/* RTCC Register Base Address */
# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200)
/* Timer 1-5 Register Base Addresses */
# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1))
# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00)
# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00)
/* Input Capture 1-5 Register Base Addresses */
# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
/* Output Compare 1-5 Register Base Addresses */
# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1))
# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
/* I2C 1-5 Register Base Addresses */
# define PIC32MX_I2C3_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000)
# define PIC32MX_I2C4_K1BASE (PIC32MX_SFR_K1BASE + 0x00005100)
# define PIC32MX_I2C5_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200)
# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005300)
# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005400)
/* SPI 1-2 Register Base Addresses */
# define PIC32MX_SPI3_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800)
# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00)
# define PIC32MX_SPI4_K1BASE (PIC32MX_SFR_K1BASE + 0x00005c00)
/* UART 1-6 Register Base Addresses */
# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000)
# define PIC32MX_UART4_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200)
# define PIC32MX_UART3_K1BASE (PIC32MX_SFR_K1BASE + 0x00006400)
# define PIC32MX_UART6_K1BASE (PIC32MX_SFR_K1BASE + 0x00006600)
# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006800)
# define PIC32MX_UART5_K1BASE (PIC32MX_SFR_K1BASE + 0x00006a00)
/* Parallel Master Register Base Address */
# define PIC32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
/* ADC Register Base Addresses */
# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000)
/* Comparator Voltage Reference Register Base Addresses */
# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
/* Comparator Register Base Addresses */
# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
# define PIC32MX_CM1_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
# define PIC32MX_CM2_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a010)
/* Oscillator Control Register Base Addresses */
# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000)
/* Programming and Diagnostics Register Base Addresses */
# define PIC32MX_DDP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
/* FLASH Controller Register Base Addresses */
# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400)
/* Reset Control Register Base Address */
# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600)
/* Interrupt Register Base Address */
# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000)
/* Bus Matrix Register Base Address */
# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000)
/* DMA Register Base Address */
# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000)
# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n))
# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060)
# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120)
# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
/* Prefetch Cache Register Base Address */
# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
/* USB2 Register Base Addresses */
# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000)
/* Port Register Base Addresses */
# define PIC32MX_IOPORTA 0
# define PIC32MX_IOPORTB 1
# define PIC32MX_IOPORTC 2
# define PIC32MX_IOPORTD 3
# define PIC32MX_IOPORTE 4
# define PIC32MX_IOPORTF 5
# define PIC32MX_IOPORTG 6
# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n))
# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
# define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
# define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
# define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
# define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
#else
# error "Memory map unknown for this PIC32 chip"
#endif

2
arch/mips/src/pic32mx/pic32mx-oc.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-oc.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

156
arch/mips/src/pic32mx/pic32mx-spi.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-spi.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -42,6 +42,7 @@
#include <nuttx/config.h>
#include "chip.h"
#include "pic32mx-memorymap.h"
/****************************************************************************
@ -63,34 +64,81 @@
/* Register Addresses *******************************************************/
#define PIC32MX_SPI1_CON (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CON_OFFSET)
#define PIC32MX_SPI1_CONCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
#define PIC32MX_SPI1_CONSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
#define PIC32MX_SPI1_CONINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
#define PIC32MX_SPI1_STAT (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STAT_OFFSET)
#define PIC32MX_SPI1_STATSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
#define PIC32MX_SPI1_BUF (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BUF_OFFSET)
#define PIC32MX_SPI1_BRG (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRG_OFFSET)
#define PIC32MX_SPI1_BRGCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
#define PIC32MX_SPI1_BRGSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
#define PIC32MX_SPI1_BRGINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
#ifdef PIC32MX_SPI1_K1BASE
# define PIC32MX_SPI1_CON (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CON_OFFSET)
# define PIC32MX_SPI1_CONCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
# define PIC32MX_SPI1_CONSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
# define PIC32MX_SPI1_CONINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
# define PIC32MX_SPI1_STAT (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STAT_OFFSET)
# define PIC32MX_SPI1_STATSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
# define PIC32MX_SPI1_BUF (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BUF_OFFSET)
# define PIC32MX_SPI1_BRG (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRG_OFFSET)
# define PIC32MX_SPI1_BRGCLR (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
# define PIC32MX_SPI1_BRGSET (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
# define PIC32MX_SPI1_BRGINV (PIC32MX_SPI1_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
#endif
#define PIC32MX_SPI2_CON (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CON_OFFSET)
#define PIC32MX_SPI2_CONCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
#define PIC32MX_SPI2_CONSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
#define PIC32MX_SPI2_CONINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
#define PIC32MX_SPI2_STAT (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STAT_OFFSET)
#define PIC32MX_SPI2_STATSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
#define PIC32MX_SPI2_BUF (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BUF_OFFSET)
#define PIC32MX_SPI2_BRG (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRG_OFFSET)
#define PIC32MX_SPI2_BRGCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
#define PIC32MX_SPI2_BRGSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
#define PIC32MX_SPI2_BRGINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
#ifdef PIC32MX_SPI2_K1BASE
# define PIC32MX_SPI2_CON (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CON_OFFSET)
# define PIC32MX_SPI2_CONCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
# define PIC32MX_SPI2_CONSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
# define PIC32MX_SPI2_CONINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
# define PIC32MX_SPI2_STAT (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STAT_OFFSET)
# define PIC32MX_SPI2_STATSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
# define PIC32MX_SPI2_BUF (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BUF_OFFSET)
# define PIC32MX_SPI2_BRG (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRG_OFFSET)
# define PIC32MX_SPI2_BRGCLR (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
# define PIC32MX_SPI2_BRGSET (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
# define PIC32MX_SPI2_BRGINV (PIC32MX_SPI2_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
#endif
#ifdef PIC32MX_SPI3_K1BASE
# define PIC32MX_SPI3_CON (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CON_OFFSET)
# define PIC32MX_SPI3_CONCLR (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
# define PIC32MX_SPI3_CONSET (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
# define PIC32MX_SPI3_CONINV (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
# define PIC32MX_SPI3_STAT (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_STAT_OFFSET)
# define PIC32MX_SPI3_STATSET (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
# define PIC32MX_SPI3_BUF (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BUF_OFFSET)
# define PIC32MX_SPI3_BRG (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRG_OFFSET)
# define PIC32MX_SPI3_BRGCLR (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
# define PIC32MX_SPI3_BRGSET (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
# define PIC32MX_SPI3_BRGINV (PIC32MX_SPI3_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
#endif
#ifdef PIC32MX_SPI4_K1BASE
# define PIC32MX_SPI4_CON (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CON_OFFSET)
# define PIC32MX_SPI4_CONCLR (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CONCLR_OFFSET)
# define PIC32MX_SPI4_CONSET (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CONSET_OFFSET)
# define PIC32MX_SPI4_CONINV (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_CONINV_OFFSET)
# define PIC32MX_SPI4_STAT (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_STAT_OFFSET)
# define PIC32MX_SPI4_STATSET (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_STATSET_OFFSET)
# define PIC32MX_SPI4_BUF (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BUF_OFFSET)
# define PIC32MX_SPI4_BRG (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRG_OFFSET)
# define PIC32MX_SPI4_BRGCLR (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRGCLR_OFFSET)
# define PIC32MX_SPI4_BRGSET (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRGSET_OFFSET)
# define PIC32MX_SPI4_BRGINV (PIC32MX_SPI4_K1BASE+PIC32MX_SPI_BRGINV_OFFSET)
#endif
/* Register Bit-Field Definitions *******************************************/
/* SPI control register */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define SPI_CON_RTXISEL_SHIFT (0) /* Bits 0-1: SPI Receive Buffer Full Interrupt Mode */
# define SPI_CON_RTXISEL_MASK (3 << SPI_CON_RTXISEL_SHIFT)
# define SPI_CON_RTXISEL_EMPTY (0 << SPI_CON_RTXISEL_SHIFT) /* Buffer empty*/
# define SPI_CON_RTXISEL_NEMPTY (1 << SPI_CON_RTXISEL_SHIFT) /* Buffer not empty*/
# define SPI_CON_RTXISEL_HALF (2 << SPI_CON_RTXISEL_SHIFT) /* Buffer half full or more */
# define SPI_CON_RTXISEL_FULL (3 << SPI_CON_RTXISEL_SHIFT) /* Buffer full */
# define SPI_CON_STXISEL_SHIFT (2) /* Bits 2-3: SPI Transmit Buffer Empty Interrupt Mode */
# define SPI_CON_STXISEL_MASK (3 << SPI_CON_STXISEL_SHIFT)
# define SPI_CON_STXISEL_DONE (0 << SPI_CON_STXISEL_SHIFT) /* Buffer empty (and data shifted out) */
# define SPI_CON_STXISEL_EMPTY (1 << SPI_CON_STXISEL_SHIFT) /* Buffer empty */
# define SPI_CON_STXISEL_HALF (2 << SPI_CON_STXISEL_SHIFT) /* Buffer half empty or more */
# define SPI_CON_STXISEL_NFULL (3 << SPI_CON_STXISEL_SHIFT) /* Buffer not full */
#endif
/* Bit 4: Reserved */
#define SPI_CON_MSTEN (1 << 5) /* Bits 5: Master mode enable */
#define SPI_CON_CKP (1 << 6) /* Bits 6: Clock polarity select */
#define SPI_CON_SSEN (1 << 7) /* Bits 7: Slave select enable (slave mode) */
@ -108,42 +156,50 @@
#define SPI_CON_ON (1 << 15) /* Bits 15: SPI peripheral on */
#define SPI_CON_ENHBUF (1 << 16) /* Bits 16: Enhanced buffer enable */
#define SPI_CON_SPIFE (1 << 17) /* Bits 17: Frame sync pulse edge select */
#define SPI_CON_FRMCNT_SHIFT (24) /* Bits 24-26: Frame Sync Pulse Counter bits */
#define SPI_CON_FRMCNT_MASK (7 << SPI_CON_FRMCNT_SHIFT)
# define SPI_CON_FRMCNT_CHAR1 (0 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse each char */
# define SPI_CON_FRMCNT_CHAR2 (1 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 2 chars */
# define SPI_CON_FRMCNT_CHAR4 (2 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 4 chars */
# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
#define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
#define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
/* Bits 18-23: Reserved */
#if defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define SPI_CON_FRMCNT_SHIFT (24) /* Bits 24-26: Frame Sync Pulse Counter bits */
# define SPI_CON_FRMCNT_MASK (7 << SPI_CON_FRMCNT_SHIFT)
# define SPI_CON_FRMCNT_CHAR1 (0 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse each char */
# define SPI_CON_FRMCNT_CHAR2 (1 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 2 chars */
# define SPI_CON_FRMCNT_CHAR4 (2 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 4 chars */
# define SPI_CON_FRMCNT_CHAR8 (3 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 8 chars */
# define SPI_CON_FRMCNT_CHAR16 (4 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 16 chars */
# define SPI_CON_FRMCNT_CHAR32 (5 << SPI_CON_FRMCNT_SHIFT) /* Frame sync pulse every 32 chars */
# define SPI_CON_FRMSYPW (1 << 27) /* Bits 27: Frame sync pulse width */
# define SPI_CON_MSSEN (1 << 28) /* Bits 28: Master mode slave select enable */
#endif
#define SPI_CON_FRMPOL (1 << 29) /* Bits 29: Frame sync polarity */
#define SPI_CON_FRMSYNC (1 << 30) /* Bits 30: Frame sync pulse direction control on SSx pin */
#define SPI_CON_FRMEN (1 << 31) /* Bits 31: Framed SPI support */
/* SPI status register */
#define SPI_STAT_SPIRBF (1 << 0) /* Bits 0: SPI receive buffer full status */
#define SPI_STAT_SPITBF (1 << 1) /* Bits 1: SPI transmit buffer full status */
#define SPI_STAT_SPITBE (1 << 3) /* Bits 3: SPI transmit buffer empty status */
#define SPI_STAT_SPIRBE (1 << 5) /* Bits 5: RX FIFO Empty */
#define SPI_STAT_SPIROV (1 << 6) /* Bits 6: Receive overflow flag */
#define SPI_STAT_SRMT (1 << 7) /* Bits 6: Shift Register Empty */
#define SPI_STAT_SPITUR (1 << 6) /* Bits 8: Transmit under run */
#define SPI_STAT_SPIBUSY (1 << 11) /* Bits 11: SPI activity status */
#define SPI_STAT_TXBUFELM_SHIFT (16) /* Bits 16-20: Transmit Buffer Element Count bits */
#define SPI_STAT_TXBUFELM_MASK (31 << SPI_STAT_TXBUFELM_SHIFT)
#define SPI_STAT_RXBUFELM_SHIFT (24) /* Bits 24-28: Receive Buffer Element Count bits */
#define SPI_STAT_RXBUFELM_MASK (31 << SPI_STAT_RXBUFELM_SHIFT)
#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
# define SPI_STAT_SPIRBF (1 << 0) /* Bits 0: SPI receive buffer full status */
# define SPI_STAT_SPITBE (1 << 3) /* Bits 3: SPI transmit buffer empty status */
# define SPI_STAT_SPIROV (1 << 6) /* Bits 6: Receive overflow flag */
# define SPI_STAT_SPIBUSY (1 << 11) /* Bits 11: SPI activity status */
#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
# define SPI_STAT_SPIRBF (1 << 0) /* Bits 0: SPI receive buffer full status */
# define SPI_STAT_SPITBF (1 << 1) /* Bits 1: SPI transmit buffer full status */
# define SPI_STAT_SPITBE (1 << 3) /* Bits 3: SPI transmit buffer empty status */
# define SPI_STAT_SPIRBE (1 << 5) /* Bits 5: RX FIFO Empty */
# define SPI_STAT_SPIROV (1 << 6) /* Bits 6: Receive overflow flag */
# define SPI_STAT_SRMT (1 << 7) /* Bits 6: Shift Register Empty */
# define SPI_STAT_SPITUR (1 << 6) /* Bits 8: Transmit under run */
# define SPI_STAT_SPIBUSY (1 << 11) /* Bits 11: SPI activity status */
# define SPI_STAT_TXBUFELM_SHIFT (16) /* Bits 16-20: Transmit Buffer Element Count bits */
# define SPI_STAT_TXBUFELM_MASK (31 << SPI_STAT_TXBUFELM_SHIFT)
# define SPI_STAT_RXBUFELM_SHIFT (24) /* Bits 24-28: Receive Buffer Element Count bits */
# define SPI_STAT_RXBUFELM_MASK (31 << SPI_STAT_RXBUFELM_SHIFT)
#endif
/* SPI buffer register (May be 31-bits wide on some parts) */
/* SPI buffer register (32-bits wide) */
#define SPI_BUF_MASK 0x1ff
/* SPI baud rate register */
/* SPI baud rate register (This register holds 32-bits of data with other
* bit-fields
*/
#define SPI_BRG_MASK 0x1ff
/****************************************************************************
* Public Types

2
arch/mips/src/pic32mx/pic32mx-timer.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-timer.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

130
arch/mips/src/pic32mx/pic32mx-uart.h
View File

@ -2,7 +2,7 @@
* arch/mips/src/pic32mx/pic32mx-uart.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -67,35 +67,107 @@
/* Register Addresses ****************************************************************/
#define PIC32MX_UART1_MODE (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODE_OFFSET)
#define PIC32MX_UART1_MODECLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
#define PIC32MX_UART1_MODESET (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODESET_OFFSET)
#define PIC32MX_UART1_MODEINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
#define PIC32MX_UART1_STA (PIC32MX_UART1_K1BASE+PIC32MX_UART_STA_OFFSET)
#define PIC32MX_UART1_STACLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_STACLR_OFFSET)
#define PIC32MX_UART1_STASET (PIC32MX_UART1_K1BASE+PIC32MX_UART_STASET_OFFSET)
#define PIC32MX_UART1_STAINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_STAINV_OFFSET)
#define PIC32MX_UART1_TXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_TXREG_OFFSET)
#define PIC32MX_UART1_RXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_RXREG_OFFSET)
#define PIC32MX_UART1_BRG (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRG_OFFSET)
#define PIC32MX_UART1_BRGCLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
#define PIC32MX_UART1_BRGSET (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
#define PIC32MX_UART1_BRGINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#if CHIP_NUARTS > 0
# define PIC32MX_UART1_MODE (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODE_OFFSET)
# define PIC32MX_UART1_MODECLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
# define PIC32MX_UART1_MODESET (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODESET_OFFSET)
# define PIC32MX_UART1_MODEINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
# define PIC32MX_UART1_STA (PIC32MX_UART1_K1BASE+PIC32MX_UART_STA_OFFSET)
# define PIC32MX_UART1_STACLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_STACLR_OFFSET)
# define PIC32MX_UART1_STASET (PIC32MX_UART1_K1BASE+PIC32MX_UART_STASET_OFFSET)
# define PIC32MX_UART1_STAINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_STAINV_OFFSET)
# define PIC32MX_UART1_TXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_TXREG_OFFSET)
# define PIC32MX_UART1_RXREG (PIC32MX_UART1_K1BASE+PIC32MX_UART_RXREG_OFFSET)
# define PIC32MX_UART1_BRG (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRG_OFFSET)
# define PIC32MX_UART1_BRGCLR (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
# define PIC32MX_UART1_BRGSET (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
# define PIC32MX_UART1_BRGINV (PIC32MX_UART1_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
#define PIC32MX_UART2_MODE (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODE_OFFSET)
#define PIC32MX_UART2_MODECLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
#define PIC32MX_UART2_MODESET (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODESET_OFFSET)
#define PIC32MX_UART2_MODEINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
#define PIC32MX_UART2_STA (PIC32MX_UART2_K1BASE+PIC32MX_UART_STA_OFFSET)
#define PIC32MX_UART2_STACLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_STACLR_OFFSET)
#define PIC32MX_UART2_STASET (PIC32MX_UART2_K1BASE+PIC32MX_UART_STASET_OFFSET)
#define PIC32MX_UART2_STAINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_STAINV_OFFSET)
#define PIC32MX_UART2_TXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_TXREG_OFFSET)
#define PIC32MX_UART2_RXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_RXREG_OFFSET)
#define PIC32MX_UART2_BRG (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRG_OFFSET)
#define PIC32MX_UART2_BRGCLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
#define PIC32MX_UART2_BRGSET (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
#define PIC32MX_UART2_BRGINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#if CHIP_NUARTS > 1
# define PIC32MX_UART2_MODE (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODE_OFFSET)
# define PIC32MX_UART2_MODECLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
# define PIC32MX_UART2_MODESET (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODESET_OFFSET)
# define PIC32MX_UART2_MODEINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
# define PIC32MX_UART2_STA (PIC32MX_UART2_K1BASE+PIC32MX_UART_STA_OFFSET)
# define PIC32MX_UART2_STACLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_STACLR_OFFSET)
# define PIC32MX_UART2_STASET (PIC32MX_UART2_K1BASE+PIC32MX_UART_STASET_OFFSET)
# define PIC32MX_UART2_STAINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_STAINV_OFFSET)
# define PIC32MX_UART2_TXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_TXREG_OFFSET)
# define PIC32MX_UART2_RXREG (PIC32MX_UART2_K1BASE+PIC32MX_UART_RXREG_OFFSET)
# define PIC32MX_UART2_BRG (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRG_OFFSET)
# define PIC32MX_UART2_BRGCLR (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
# define PIC32MX_UART2_BRGSET (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
# define PIC32MX_UART2_BRGINV (PIC32MX_UART2_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
#if CHIP_NUARTS > 2
# define PIC32MX_UART3_MODE (PIC32MX_UART3_K1BASE+PIC32MX_UART_MODE_OFFSET)
# define PIC32MX_UART3_MODECLR (PIC32MX_UART3_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
# define PIC32MX_UART3_MODESET (PIC32MX_UART3_K1BASE+PIC32MX_UART_MODESET_OFFSET)
# define PIC32MX_UART3_MODEINV (PIC32MX_UART3_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
# define PIC32MX_UART3_STA (PIC32MX_UART3_K1BASE+PIC32MX_UART_STA_OFFSET)
# define PIC32MX_UART3_STACLR (PIC32MX_UART3_K1BASE+PIC32MX_UART_STACLR_OFFSET)
# define PIC32MX_UART3_STASET (PIC32MX_UART3_K1BASE+PIC32MX_UART_STASET_OFFSET)
# define PIC32MX_UART3_STAINV (PIC32MX_UART3_K1BASE+PIC32MX_UART_STAINV_OFFSET)
# define PIC32MX_UART3_TXREG (PIC32MX_UART3_K1BASE+PIC32MX_UART_TXREG_OFFSET)
# define PIC32MX_UART3_RXREG (PIC32MX_UART3_K1BASE+PIC32MX_UART_RXREG_OFFSET)
# define PIC32MX_UART3_BRG (PIC32MX_UART3_K1BASE+PIC32MX_UART_BRG_OFFSET)
# define PIC32MX_UART3_BRGCLR (PIC32MX_UART3_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
# define PIC32MX_UART3_BRGSET (PIC32MX_UART3_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
# define PIC32MX_UART3_BRGINV (PIC32MX_UART3_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
#if CHIP_NUARTS > 3
# define PIC32MX_UART4_MODE (PIC32MX_UART4_K1BASE+PIC32MX_UART_MODE_OFFSET)
# define PIC32MX_UART4_MODECLR (PIC32MX_UART4_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
# define PIC32MX_UART4_MODESET (PIC32MX_UART4_K1BASE+PIC32MX_UART_MODESET_OFFSET)
# define PIC32MX_UART4_MODEINV (PIC32MX_UART4_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
# define PIC32MX_UART4_STA (PIC32MX_UART4_K1BASE+PIC32MX_UART_STA_OFFSET)
# define PIC32MX_UART4_STACLR (PIC32MX_UART4_K1BASE+PIC32MX_UART_STACLR_OFFSET)
# define PIC32MX_UART4_STASET (PIC32MX_UART4_K1BASE+PIC32MX_UART_STASET_OFFSET)
# define PIC32MX_UART4_STAINV (PIC32MX_UART4_K1BASE+PIC32MX_UART_STAINV_OFFSET)
# define PIC32MX_UART4_TXREG (PIC32MX_UART4_K1BASE+PIC32MX_UART_TXREG_OFFSET)
# define PIC32MX_UART4_RXREG (PIC32MX_UART4_K1BASE+PIC32MX_UART_RXREG_OFFSET)
# define PIC32MX_UART4_BRG (PIC32MX_UART4_K1BASE+PIC32MX_UART_BRG_OFFSET)
# define PIC32MX_UART4_BRGCLR (PIC32MX_UART4_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
# define PIC32MX_UART4_BRGSET (PIC32MX_UART4_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
# define PIC32MX_UART4_BRGINV (PIC32MX_UART4_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
#if CHIP_NUARTS > 4
# define PIC32MX_UART5_MODE (PIC32MX_UART5_K1BASE+PIC32MX_UART_MODE_OFFSET)
# define PIC32MX_UART5_MODECLR (PIC32MX_UART5_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
# define PIC32MX_UART5_MODESET (PIC32MX_UART5_K1BASE+PIC32MX_UART_MODESET_OFFSET)
# define PIC32MX_UART5_MODEINV (PIC32MX_UART5_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
# define PIC32MX_UART5_STA (PIC32MX_UART5_K1BASE+PIC32MX_UART_STA_OFFSET)
# define PIC32MX_UART5_STACLR (PIC32MX_UART5_K1BASE+PIC32MX_UART_STACLR_OFFSET)
# define PIC32MX_UART5_STASET (PIC32MX_UART5_K1BASE+PIC32MX_UART_STASET_OFFSET)
# define PIC32MX_UART5_STAINV (PIC32MX_UART5_K1BASE+PIC32MX_UART_STAINV_OFFSET)
# define PIC32MX_UART5_TXREG (PIC32MX_UART5_K1BASE+PIC32MX_UART_TXREG_OFFSET)
# define PIC32MX_UART5_RXREG (PIC32MX_UART5_K1BASE+PIC32MX_UART_RXREG_OFFSET)
# define PIC32MX_UART5_BRG (PIC32MX_UART5_K1BASE+PIC32MX_UART_BRG_OFFSET)
# define PIC32MX_UART5_BRGCLR (PIC32MX_UART5_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
# define PIC32MX_UART5_BRGSET (PIC32MX_UART5_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
# define PIC32MX_UART5_BRGINV (PIC32MX_UART5_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
#if CHIP_NUARTS > 5
# define PIC32MX_UART6_MODE (PIC32MX_UART6_K1BASE+PIC32MX_UART_MODE_OFFSET)
# define PIC32MX_UART6_MODECLR (PIC32MX_UART6_K1BASE+PIC32MX_UART_MODECLR_OFFSET)
# define PIC32MX_UART6_MODESET (PIC32MX_UART6_K1BASE+PIC32MX_UART_MODESET_OFFSET)
# define PIC32MX_UART6_MODEINV (PIC32MX_UART6_K1BASE+PIC32MX_UART_MODEINV_OFFSET)
# define PIC32MX_UART6_STA (PIC32MX_UART6_K1BASE+PIC32MX_UART_STA_OFFSET)
# define PIC32MX_UART6_STACLR (PIC32MX_UART6_K1BASE+PIC32MX_UART_STACLR_OFFSET)
# define PIC32MX_UART6_STASET (PIC32MX_UART6_K1BASE+PIC32MX_UART_STASET_OFFSET)
# define PIC32MX_UART6_STAINV (PIC32MX_UART6_K1BASE+PIC32MX_UART_STAINV_OFFSET)
# define PIC32MX_UART6_TXREG (PIC32MX_UART6_K1BASE+PIC32MX_UART_TXREG_OFFSET)
# define PIC32MX_UART6_RXREG (PIC32MX_UART6_K1BASE+PIC32MX_UART_RXREG_OFFSET)
# define PIC32MX_UART6_BRG (PIC32MX_UART6_K1BASE+PIC32MX_UART_BRG_OFFSET)
# define PIC32MX_UART6_BRGCLR (PIC32MX_UART6_K1BASE+PIC32MX_UART_BRGCLR_OFFSET)
# define PIC32MX_UART6_BRGSET (PIC32MX_UART6_K1BASE+PIC32MX_UART_BRGSET_OFFSET)
# define PIC32MX_UART6_BRGINV (PIC32MX_UART6_K1BASE+PIC32MX_UART_BRGINV_OFFSET)
#endif
/* Register Bit-Field Definitions ****************************************************/

22
configs/pic32-starterkit/README.txt
View File

@ -48,6 +48,7 @@ Contents
========
PIC32MX795F512L Pin Out
MEB Connector
Toolchains
Loading NuttX with PICkit2
PIC32MX Configuration Options
@ -219,6 +220,9 @@ PIN CONFIGURATIONS SIGNAL NAME
76 OC2/RD1 OC1/RD1 User LED D6 (high illuminates)
J2 pin 44 (OC/PWM)
MEB Connector
=============
Toolchains
==========
@ -425,9 +429,16 @@ PIC32MX Configuration Options
CONFIG_PIC32MX_OC5 - Output Compare 5
CONFIG_PIC32MX_I2C1 - I2C 1
CONFIG_PIC32MX_I2C2 - I2C 2
CONFIG_PIC32MX_I2C3 - I2C 3
CONFIG_PIC32MX_I2C4 - I2C 4
CONFIG_PIC32MX_I2C5 - I2C 5
CONFIG_PIC32MX_SPI2 - SPI 2
CONFIG_PIC32MX_UART1 - UART 1
CONFIG_PIC32MX_UART2 - UART 2
CONFIG_PIC32MX_UART3 - UART 3
CONFIG_PIC32MX_UART4 - UART 4
CONFIG_PIC32MX_UART5 - UART 5
CONFIG_PIC32MX_UART6 - UART 6
CONFIG_PIC32MX_ADC - ADC 1
CONFIG_PIC32MX_PMP - Parallel Master Port
CONFIG_PIC32MX_CM1 - Comparator 1
@ -437,7 +448,9 @@ PIC32MX Configuration Options
CONFIG_PIC32MX_FLASH - FLASH
CONFIG_PIC32MX_USBDEV - USB device
CONFIG_PIC32MX_USBHOST - USB host
CONFIG_PIC32MX_CAN1 - Controller area network 1
CONFIG_PIC32MX_CAN2 - Controller area network 2
CONFIG_PIC32MX_ETHERNET - Ethernet
PIC32MX Configuration Settings
DEVCFG0:
@ -488,6 +501,9 @@ PIC32MX Configuration Options
CONFIG_PIC32MX_OC5PRIO - Output Compare 5
CONFIG_PIC32MX_I2C1PRIO - I2C 1
CONFIG_PIC32MX_I2C2PRIO - I2C 2
CONFIG_PIC32MX_I2C3PRIO - I2C 3
CONFIG_PIC32MX_I2C4PRIO - I2C 4
CONFIG_PIC32MX_I2C5PRIO - I2C 5
CONFIG_PIC32MX_SPI2PRIO - SPI 2
CONFIG_PIC32MX_UART1PRIO - UART 1
CONFIG_PIC32MX_UART2PRIO - UART 2
@ -502,6 +518,10 @@ PIC32MX Configuration Options
CONFIG_PIC32MX_DMA1PRIO - DMA Channel 1
CONFIG_PIC32MX_DMA2PRIO - DMA Channel 2
CONFIG_PIC32MX_DMA3PRIO - DMA Channel 3
CONFIG_PIC32MX_DMA4PRIO - DMA Channel 4
CONFIG_PIC32MX_DMA5PRIO - DMA Channel 5
CONFIG_PIC32MX_DMA6PRIO - DMA Channel 6
CONFIG_PIC32MX_DMA7PRIO - DMA Channel 7
CONFIG_PIC32MX_FCEPRIO - Flash Control Event
CONFIG_PIC32MX_USBPRIO - USB

8
configs/pic32-starterkit/ostest/ld.script
View File

@ -36,13 +36,13 @@
MEMORY
{
/* The PIC32MX440F512H has 512Kb of program FLASH at physical address
/* The PIC32MX795F512L has 512Kb of program FLASH at physical address
* 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000
*/
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
/* The PIC32MX440F512H has 12Kb of boot FLASH at physical address
/* The PIC32MX795F512L has 12Kb of boot FLASH at physical address
* 0x1fc00000. The initial reset vector is in KSEG1, but all other
* accesses are in KSEG0.
*
@ -76,12 +76,12 @@ MEMORY
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
kseg1_devcfg (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16
/* The PIC32MX440F512H has 32Kb of data memory at physical address
/* The PIC32MX795F512L has 128Kb of data memory at physical address
* 0x00000000. Since the PIC32MX has no data cache, this memory is
* always accessed through KSEG1.
*/
kseg1_datamem (w!x) : ORIGIN = 0xa0000000, LENGTH = 32K
kseg1_datamem (w!x) : ORIGIN = 0xa0000000, LENGTH = 128K
}
OUTPUT_FORMAT("elf32-tradlittlemips")