Add i2c driver for gd32f450 MCU
This commit is contained in:
GD32-MCU
Xiang Xiao
parent
3462061624
commit
659bd495b0
@ -1447,7 +1447,6 @@ config GD32F4_DAC1_DMA_BUFFER_SIZE
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endmenu # DAC Configuration
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config GD32F4_USART_RXDMA
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bool
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default n
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@ -2028,7 +2027,51 @@ endmenu # USART Configuration
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menu "I2C Configuration"
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depends on GD32F4_I2C
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endmenu
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config GD32F4_I2C_DYNTIMEO
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bool "Use dynamic timeouts"
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default n
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depends on GD32F4_I2C
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config GD32F4_I2C_DYNTIMEO_USECPERBYTE
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int "Timeout microseconds per Byte"
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default 500
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depends on GD32F4_I2C_DYNTIMEO
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config GD32F4_I2C_DYNTIMEO_STARTSTOP
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int "Timeout for Start/stop (milliseconds)"
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default 1000
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depends on GD32F4_I2C_DYNTIMEO
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config GD32F4_I2C_TIMEOSEC
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int "Timeout seconds"
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default 0
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depends on GD32F4_I2C
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config GD32F4_I2C_TIMEOMS
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int "Timeout milliseconds"
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default 500
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depends on GD32F4_I2C && !GD32F4_I2C_DYNTIMEO
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config GD32F4_I2C_TIMEOTICKS
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int "Timeout for Done and Stop (ticks)"
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default 500
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depends on GD32F4_I2C && !GD32F4_I2C_DYNTIMEO
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config GD32F4_I2C_DUTY16_9
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bool "Frequency with Tlow/Thigh = 16/9"
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default n
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depends on GD32F4_I2C
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config GD32F4_I2C_DMA
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bool "I2C DMA Support"
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default n
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depends on GD32F4_I2C && GD32F4_DMA0 && !I2C_POLLED
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---help---
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This option enables the DMA for I2C transfers.
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Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the
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I2C dma channel, else the default priority level is set to medium.
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endmenu # I2C Configuration
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config GD32F4_HAVE_RTC_COUNTER
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@ -55,3 +55,7 @@ endif
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ifeq ($(CONFIG_GD32F4_SPI),y)
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CHIP_CSRCS += gd32f4xx_spi.c
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endif
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ifeq ($(CONFIG_GD32F4_I2C),y)
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CHIP_CSRCS += gd32f4xx_i2c.c
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endif
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@ -45,6 +45,7 @@
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#include "gd32f4xx_fmc.h"
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#include "gd32f4xx_pmu.h"
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#include "gd32f4xx_spi.h"
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#include "gd32f4xx_i2c.h"
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#include "gd32f4xx_syscfg.h"
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#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_H */
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@ -714,21 +714,17 @@ void gd32_dma_singlemode_setup(struct gd32_dma_channel_s *dmachan,
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regval |= init_struct->direction;
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if (DMA_WIDTH_8BITS_SELECT == init_struct->periph_memory_width)
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if (DMA_WIDTH_32BITS_SELECT == init_struct->periph_memory_width)
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{
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regval |= DMA_MEMORY_WIDTH_8BIT;
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regval |= DMA_MEMORY_WIDTH_32BIT | DMA_PERIPH_WIDTH_32BIT;
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}
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else if (DMA_WIDTH_16BITS_SELECT == init_struct->periph_memory_width)
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{
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regval |= DMA_MEMORY_WIDTH_16BIT;
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}
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else if (DMA_WIDTH_32BITS_SELECT == init_struct->periph_memory_width)
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{
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regval |= DMA_MEMORY_WIDTH_32BIT;
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regval |= DMA_MEMORY_WIDTH_16BIT | DMA_PERIPH_WIDTH_16BIT;
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}
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else
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{
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regval |= DMA_MEMORY_WIDTH_8BIT;
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regval |= DMA_MEMORY_WIDTH_8BIT | DMA_PERIPH_WIDTH_8BIT;
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}
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if (DMA_PRIO_LOW_SELECT == init_struct->priority)
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2683
arch/arm/src/gd32f4/gd32f4xx_i2c.c
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2683
arch/arm/src/gd32f4/gd32f4xx_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
89
arch/arm/src/gd32f4/gd32f4xx_i2c.h
Normal file
89
arch/arm/src/gd32f4/gd32f4xx_i2c.h
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@ -0,0 +1,89 @@
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/****************************************************************************
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* arch/arm/src/gd32f4/gd32f4xx_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_I2C_H
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#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_I2C_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/i2c/i2c_master.h>
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#include "chip.h"
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#include "hardware/gd32f4xx_i2c.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* If a dynamic timeout is selected, then a non-negative, non-zero micro-
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* seconds per byte value must be provided as well.
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*/
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#ifdef CONFIG_GD32F4_I2C_DYNTIMEO
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# if CONFIG_GD32F4_I2C_DYNTIMEO_USECPERBYTE < 1
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# warning "Ignoring CONFIG_GD32F4_I2C_DYNTIMEO because of CONFIG_GD32F4_I2C_DYNTIMEO_USECPERBYTE"
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# undef CONFIG_GD32F4_I2C_DYNTIMEO
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# endif
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: gd32_i2cbus_initialize
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*
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* Description:
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* Initialize the selected I2C port. And return a unique instance of struct
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* struct i2c_master_s. This function may be called to obtain multiple
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* instances of the interface, each of which may be set up with a
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* different frequency and slave address.
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*
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* Input Parameters:
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* Port number (for hardware that has multiple I2C interfaces)
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*
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* Returned Value:
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* Valid I2C device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct i2c_master_s *gd32_i2cbus_initialize(int port);
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/****************************************************************************
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* Name: gd32_i2cbus_uninitialize
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*
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* Description:
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* De-initialize the selected I2C port, and power down the device.
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*
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* Input Parameters:
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* Device structure as returned by the gd32_i2cbus_initialize()
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*
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* Returned Value:
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* OK on success, ERROR when internal reference count mismatch or dev
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* points to invalid hardware device.
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*
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****************************************************************************/
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int gd32_i2cbus_uninitialize(struct i2c_master_s *dev);
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#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_I2C_H */
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189
arch/arm/src/gd32f4/hardware/gd32f4xx_i2c.h
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189
arch/arm/src/gd32f4/hardware/gd32f4xx_i2c.h
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@ -0,0 +1,189 @@
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/****************************************************************************
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* arch/arm/src/gd32f4/hardware/gd32f4xx_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_I2C_H
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#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_I2C_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* I2Cx(x=0,1,2,3,4,5) definitions */
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#define GD32_I2C0_BASE (GD32_I2C_BASE+0x00000000) /* I2C0 base address */
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#define GD32_I2C1_BASE (GD32_I2C_BASE+0x00000400) /* I2C1 base address */
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#define GD32_I2C2_BASE (GD32_I2C_BASE+0x00000800) /* I2C2 base address */
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/* Register Offsets *********************************************************/
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#define GD32_I2C_CTL0_OFFSET 0x0000 /* I2C control register 0 offset */
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#define GD32_I2C_CTL1_OFFSET 0x0004 /* I2C control register 1 offset */
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#define GD32_I2C_SADDR0_OFFSET 0x0008 /* I2C slave address register 0 offset */
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#define GD32_I2C_SADDR1_OFFSET 0x000C /* I2C slave address register 1 offset */
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#define GD32_I2C_DATA_OFFSET 0x0010 /* I2C transfer buffer register offset */
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#define GD32_I2C_STAT0_OFFSET 0x0014 /* I2C transfer status register 0 offset */
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#define GD32_I2C_STAT1_OFFSET 0x0018 /* I2C transfer status register 1 offset */
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#define GD32_I2C_CKCFG_OFFSET 0x001C /* I2C clock configure register offset */
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#define GD32_I2C_RT_OFFSET 0x0020 /* I2C rise time register offset */
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#define GD32_I2C_FCTL_OFFSET 0x0024 /* I2C filter control register offset */
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#define GD32_I2C_SAMCS_OFFSET 0x0080 /* I2C SAM control and status register offset */
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/* Register Addresses *******************************************************/
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#define GD32_I2C0 GD32_I2C0_BASE
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#define GD32_I2C1 GD32_I2C1_BASE
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#define GD32_I2C2 GD32_I2C2_BASE
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/* I2C registers definitions */
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#define GD32_I2C_CTL0(i2cx) ((i2cx)+GD32_I2C_CTL0_OFFSET) /* I2C control register 0 */
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#define GD32_I2C_CTL1(i2cx) ((i2cx)+GD32_I2C_CTL1_OFFSET) /* I2C control register 1 */
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#define GD32_I2C_SADDR0(i2cx) ((i2cx)+GD32_I2C_SADDR0_OFFSET) /* I2C slave address register 0 */
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#define GD32_I2C_SADDR1(i2cx) ((i2cx)+GD32_I2C_SADDR1_OFFSET) /* I2C slave address register 1 */
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#define GD32_I2C_DATA(i2cx) ((i2cx)+GD32_I2C_DATA_OFFSET) /* I2C transfer buffer register */
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#define GD32_I2C_STAT0(i2cx) ((i2cx)+GD32_I2C_STAT0_OFFSET) /* I2C transfer status register 0 */
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#define GD32_I2C_STAT1(i2cx) ((i2cx)+GD32_I2C_STAT1_OFFSET) /* I2C transfer status register 1 */
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#define GD32_I2C_CKCFG(i2cx) ((i2cx)+GD32_I2C_CKCFG_OFFSET) /* I2C clock configure register */
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#define GD32_I2C_RT(i2cx) ((i2cx)+GD32_I2C_RT_OFFSET) /* I2C rise time register */
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#define GD32_I2C_FCTL(i2cx) ((i2cx)+GD32_I2C_FCTL_OFFSET) /* I2C filter control register */
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#define GD32_I2C_SAMCS(i2cx) ((i2cx)+GD32_I2C_SAMCS_OFFSET) /* I2C SAM control and status register */
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/* Register Bitfield Definitions ********************************************/
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/* Control register 0 */
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#define I2C_CTL0_I2CEN (1 << 0) /* Bit 0: Peripheral enable */
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#define I2C_CTL0_SMBEN (1 << 1) /* Bit 1: SMBus mode */
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#define I2C_CTL0_SMBSEL (1 << 3) /* Bit 3: SMBus type */
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#define I2C_CTL0_ARPEN (1 << 4) /* Bit 4: ARP enable */
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#define I2C_CTL0_PECEN (1 << 5) /* Bit 5: PEC enable */
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#define I2C_CTL0_GCEN (1 << 6) /* Bit 6: General call enable */
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#define I2C_CTL0_SS (1 << 7) /* Bit 7: Clock stretching disable (Slave mode) */
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#define I2C_CTL0_START (1 << 8) /* Bit 8: Start generation */
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#define I2C_CTL0_STOP (1 << 9) /* Bit 9: Stop generation */
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#define I2C_CTL0_ACKEN (1 << 10) /* Bit 10: Acknowledge enable */
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#define I2C_CTL0_POAP (1 << 11) /* Bit 11: Acknowledge/PEC position (for data reception) */
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#define I2C_CTL0_PECTRANS (1 << 12) /* Bit 12: Packet error checking */
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#define I2C_CTL0_SALT (1 << 13) /* Bit 13: SMBus alert */
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#define I2C_CTL0_SRESET (1 << 15) /* Bit 15: Software reset */
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/* Control register 1 */
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#define I2C_CTL1_I2CCLK_SHIFT (0) /* Bits 5-0: Peripheral clock frequency */
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#define I2C_CTL1_I2CCLK_MASK (0x3f << I2C_CTL1_I2CCLK_SHIFT)
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#define I2C_CTL1_I2CCLK(n) ((n) << I2C_CTL1_I2CCLK_SHIFT)
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#define I2C_CTL1_ERRIE (1 << 8) /* Bit 8: Error interrupt enable */
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#define I2C_CTL1_EVIE (1 << 9) /* Bit 9: Event interrupt enable */
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#define I2C_CTL1_BUFIE (1 << 10) /* Bit 10: Buffer interrupt enable */
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#define I2C_CTL1_DMAON (1 << 11) /* Bit 11: DMA requests enable */
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#define I2C_CTL1_DMALST (1 << 12) /* Bit 12: DMA last transfer */
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#define I2C_CTL1_INTS_MASK (I2C_CTL1_ERRIE|I2C_CTL1_EVIE|I2C_CTL1_BUFIE)
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/* Slave address register 0 */
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#define I2C_SADDR0_ADDRESS0 (1 << 0) /* Bit 0: Bit 0 of 10-bit address */
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#define I2C_SADDR0_ADDRESS_SHIFT (1) /* Bits 7-1: 7-bit address or bits 7:1 of a 10-bit address */
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#define I2C_SADDR0_ADDRESS_MASK (0x7f << I2C_SADDR0_ADDRESS_SHIFT)
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#define I2C_SADDR0_ADDRESS_H_SHIFT (8) /* Bits 9-8: Highest two bits of a 10-bit address */
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#define I2C_SADDR0_ADDRESS_H_MASK (0x3 << I2C_SADDR0_ADDRESS_H_SHIFT)
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#define I2C_SADDR0_ADDFORMAT (1 << 15) /* Bit 15: Address mode for the I2C slave */
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/* Slave address register 1 */
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#define I2C_SADDR1_DUADEN (1 << 0) /* Bit 0: Dual-Address mode enable */
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#define I2C_SADDR1_ADDRESS2_SHIFT (1) /* Bits 7-1: Second I2C address for the slave in dual-address mode */
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#define I2C_SADDR1_ADDRESS2_MASK (0x7f << I2C_SADDR1_ADDRESS2_SHIFT)
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/* Transfer data register */
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#define I2C_DATA_TRB_SHIFT (0) /* Bits 7-0: 8-bit data register */
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#define I2C_DATA_TRB_MASK (0x00ff << I2C_DATA_TRB_SHIFT)
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/* Transfer status register 0 */
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#define I2C_STAT0_SBSEND (1 << 0) /* Bit 0: Start bit (master mode) */
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#define I2C_STAT0_ADDSEND (1 << 1) /* Bit 1: Address sent (master mode)/matched (slave mode) */
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#define I2C_STAT0_BTC (1 << 2) /* Bit 2: Byte transfer finished */
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#define I2C_STAT0_ADD10SEND (1 << 3) /* Bit 3: 10-bit header sent (master mode) */
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#define I2C_STAT0_STPDET (1 << 4) /* Bit 4: Stop detection (slave mode) */
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#define I2C_STAT0_RBNE (1 << 6) /* Bit 6: Data register not empty (receivers) */
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#define I2C_STAT0_TBE (1 << 7) /* Bit 7: Data register empty (transmitters) */
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#define I2C_STAT0_BERR (1 << 8) /* Bit 8: bus error */
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#define I2C_STAT0_LOSTARB (1 << 9) /* Bit 9: Arbitration lost (master mode) */
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#define I2C_STAT0_AERR (1 << 10) /* Bit 10: Acknowledge failure */
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#define I2C_STAT0_OUERR (1 << 11) /* Bit 11: Overrun/underrun */
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#define I2C_STAT0_PECERR (1 << 12) /* Bit 12: PEC error in reception */
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#define I2C_STAT0_SMBTO (1 << 14) /* Bit 14: Timeout signal in SMBus mode */
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#define I2C_STAT0_SMBALT (1 << 15) /* Bit 15: SMBus alert status */
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#define I2C_STAT0_ERROR_MASK (I2C_STAT0_BERR|I2C_STAT0_LOSTARB|I2C_STAT0_AERR|I2C_STAT0_OUERR|\
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I2C_STAT0_PECERR|I2C_STAT0_SMBTO|I2C_STAT0_SMBALT)
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/* Transfer status register 1 */
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#define I2C_STAT1_MASTER (1 << 0) /* Bit 0: Master/slave */
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#define I2C_STAT1_I2CBSY (1 << 1) /* Bit 1: Bus busy */
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#define I2C_STAT1_TR (1 << 2) /* Bit 2: Transmitter/receiver */
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#define I2C_STAT1_RXGC (1 << 4) /* Bit 4: General call address (slave mode) */
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#define I2C_STAT1_DEFSMB (1 << 5) /* Bit 5: SMBus device default address (slave mode) */
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#define I2C_STAT1_HSTSMB (1 << 6) /* Bit 6: SMBus host header (slave mode) */
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#define I2C_STAT1_DUMODF (1 << 7) /* Bit 7: Dual flag (slave mode) */
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#define I2C_STAT1_PECV_SHIFT (8) /* Bits 15-8: Packet error checking value */
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#define I2C_STAT1_PECV_MASK (0xff << I2C_STAT1_PECV_SHIFT)
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/* Clock configure register */
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#define I2C_CKCFG_CLKC_SHIFT (0) /* Bits 11-0: Clock control register in fast/standard mode (master mode) */
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#define I2C_CKCFG_CLKC_MASK (0x0fff << I2C_CKCFG_CLKC_SHIFT)
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#define I2C_CKCFG_DTCY (1 << 14) /* Bit 14: Fast mode duty Cycle */
|
||||
#define I2C_CKCFG_FAST (1 << 15) /* Bit 15: I2C speed selection in master mode */
|
||||
|
||||
/* Rise time register */
|
||||
|
||||
#define I2C_RT_RISETIME_SHIFT (0) /* Bits 5-0: Maximum rise time in fast/standard mode (master mode) */
|
||||
#define I2C_RT_RISETIME_MASK (0x3f << I2C_RT_RISETIME_SHIFT)
|
||||
|
||||
/* Filter control register */
|
||||
|
||||
#define I2C_FCTL_DF_SHIFT (0) /* Bit 3-0: Digital noise filter */
|
||||
#define I2C_FCTL_DFMASK (0xf << )I2C_FCTL_DF_SHIFT
|
||||
#define I2C_FCTL_AFD (4) /* Bit 4: Aanalog noise filter disable */
|
||||
|
||||
/* SAM control and status register */
|
||||
|
||||
#define I2C_SAMCS_SAMEN (0) /* Bit 0: SAM_V interface enable */
|
||||
#define I2C_SAMCS_STOEN (1) /* Bit 1: SAM_V interface timeout detect enable */
|
||||
#define I2C_SAMCS_TFFIE (4) /* Bit 4: Txframe fall interrupt enable */
|
||||
#define I2C_SAMCS_TFRIE (5) /* Bit 5: Txframe rise interrupt enable */
|
||||
#define I2C_SAMCS_RFFIE (6) /* Bit 6: Rxframe fall interrupt enable */
|
||||
#define I2C_SAMCS_RFRIE (7) /* Bit 7: Rxframe rise interrupt enable */
|
||||
#define I2C_SAMCS_TXF (8) /* Bit 8: Level of txframe signal */
|
||||
#define I2C_SAMCS_RXF (9) /* Bit 9: Level of rxframe signal */
|
||||
#define I2C_SAMCS_TFF (12) /* Bit 12: Txframe fall flag */
|
||||
#define I2C_SAMCS_TFR (13) /* Bit 13: Txframe rise flag */
|
||||
#define I2C_SAMCS_RFF (14) /* Bit 14: Rxframe fall flag */
|
||||
#define I2C_SAMCS_RFR (15) /* Bit 15: Rxframe rise flag */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_I2C_H */
|
||||
@ -87,7 +87,7 @@ config GD32F4_120MHZ
|
||||
endchoice # CPU Frequency
|
||||
|
||||
|
||||
config GD32F4_GD25_BLOCKMOUNT
|
||||
config GD32F450ZK_EVAL_GD25_BLOCKMOUNT
|
||||
bool "GD25 serial FLASH auto-mount"
|
||||
default n
|
||||
depends on GD32F4_SPI5 && MTD_GD25
|
||||
@ -96,18 +96,18 @@ config GD32F4_GD25_BLOCKMOUNT
|
||||
|
||||
choice
|
||||
prompt "GD25 SPI FLASH configuration"
|
||||
default GD32F4_GD25_NXFFS
|
||||
depends on GD32F4_GD25_BLOCKMOUNT
|
||||
default GD32F450ZK_EVAL_GD25_NXFFS
|
||||
depends on GD32F450ZK_EVAL_GD25_BLOCKMOUNT
|
||||
|
||||
config GD32F4_GD25_FTL
|
||||
config GD32F450ZK_EVAL_GD25_FTL
|
||||
bool "Create GD25 SPI FLASH block driver"
|
||||
---help---
|
||||
Create the MTD driver for the GD25 and "wrap" the GD25 as a standard
|
||||
block driver that could then, for example, be mounted using FAT or
|
||||
any other file system. Any file system may be used, but there will
|
||||
any other file system. Any file system may be used, but there will
|
||||
be no wear-leveling.
|
||||
|
||||
config GD32F4_GD25_NXFFS
|
||||
config GD32F450ZK_EVAL_GD25_NXFFS
|
||||
bool "Create GD25 serial FLASH NXFFS file system"
|
||||
depends on FS_NXFFS
|
||||
---help---
|
||||
@ -117,5 +117,20 @@ config GD32F4_GD25_NXFFS
|
||||
|
||||
endchoice # GD25 serial FLASH configuration
|
||||
|
||||
config GD32F450ZK_EVAL_AT24_TEST
|
||||
bool "I2C0 EEPROM AT2402 write and read test"
|
||||
default n
|
||||
depends on NSH_ARCHINIT && GD32F4_I2C0 && MTD_AT24XX
|
||||
---help---
|
||||
Automatically initialize and test the AT24 I2C EEPROM driver when
|
||||
NSH starts. After test the I2C0 will be released.
|
||||
|
||||
config AT24XX_MTD_BLOCKSIZE
|
||||
int "AT24xx MTD block size"
|
||||
default 8
|
||||
depends on GD32F450ZK_EVAL_AT24_TEST
|
||||
---help---
|
||||
The block size must be an even multiple of the pages.
|
||||
The page size of AT2402 on the board is 8 Byte.
|
||||
|
||||
endif # ARCH_BOARD_GD32F450ZK_EVAL
|
||||
|
||||
@ -29,11 +29,11 @@ CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_FS_TMPFS=y
|
||||
CONFIG_GD25_SPIFREQUENCY=4000000
|
||||
CONFIG_GD32F450ZK_EVAL_GD25_BLOCKMOUNT=y
|
||||
CONFIG_GD32F4_168MHZ=y
|
||||
CONFIG_GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
|
||||
CONFIG_GD32F4_ENETMAC=y
|
||||
CONFIG_GD32F4_FLASH_CONFIG_K=y
|
||||
CONFIG_GD32F4_GD25_BLOCKMOUNT=y
|
||||
CONFIG_GD32F4_PHY_SR=16
|
||||
CONFIG_GD32F4_PHY_SR_100FD=0x0004
|
||||
CONFIG_GD32F4_PHY_SR_100HD=0x0000
|
||||
|
||||
@ -0,0 +1,63 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_ARCH_FPU is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="gd32f450zk-eval"
|
||||
CONFIG_ARCH_BOARD_GD32F450ZK_EVAL=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="gd32f4"
|
||||
CONFIG_ARCH_CHIP_GD32F450ZK=y
|
||||
CONFIG_ARCH_CHIP_GD32F4=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=256
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_AT24XX_SIZE=2
|
||||
CONFIG_BOARD_LOOPSPERMSEC=16717
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_CUSTOMOPT=y
|
||||
CONFIG_DEBUG_ERROR=y
|
||||
CONFIG_DEBUG_FEATURES=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_IRQ=y
|
||||
CONFIG_DEBUG_LEDS=y
|
||||
CONFIG_DEBUG_OPTLEVEL="-O0"
|
||||
CONFIG_DEBUG_SCHED=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_DEBUG_WARN=y
|
||||
CONFIG_FS_NXFFS=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_GD32F450ZK_EVAL_AT24_TEST=y
|
||||
CONFIG_GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
|
||||
CONFIG_GD32F4_FLASH_CONFIG_K=y
|
||||
CONFIG_GD32F4_I2C0=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_I2C_DRIVER=y
|
||||
CONFIG_I2C_POLLED=y
|
||||
CONFIG_I2C_RESET=y
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_INTELHEX_BINARY=y
|
||||
CONFIG_MM_REGIONS=2
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_AT24XX=y
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_NXFFS_PACKTHRESHOLD=8
|
||||
CONFIG_RAM_SIZE=114688
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_START_DAY=6
|
||||
CONFIG_START_MONTH=12
|
||||
CONFIG_START_YEAR=2011
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_USART0_SERIAL_CONSOLE=y
|
||||
@ -25,11 +25,11 @@ CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_FS_TMPFS=y
|
||||
CONFIG_GD25_SPIFREQUENCY=4000000
|
||||
CONFIG_GD32F450ZK_EVAL_GD25_BLOCKMOUNT=y
|
||||
CONFIG_GD32F4_168MHZ=y
|
||||
CONFIG_GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y
|
||||
CONFIG_GD32F4_ENETMAC=y
|
||||
CONFIG_GD32F4_FLASH_CONFIG_K=y
|
||||
CONFIG_GD32F4_GD25_BLOCKMOUNT=y
|
||||
CONFIG_GD32F4_PHY_SR=16
|
||||
CONFIG_GD32F4_PHY_SR_100FD=0x0004
|
||||
CONFIG_GD32F4_PHY_SR_100HD=0x0000
|
||||
|
||||
@ -283,6 +283,16 @@ typedef enum
|
||||
# define GPIO_USART3_TX GPIO_USART3_TX_3
|
||||
#endif
|
||||
|
||||
/* I2C0 gpios:
|
||||
*
|
||||
* PB6 I2C0_SCL
|
||||
* PB7 I2C0_SDA
|
||||
*
|
||||
*/
|
||||
|
||||
#define GPIO_I2C0_SCL GPIO_I2C0_SCL_1
|
||||
#define GPIO_I2C0_SDA GPIO_I2C0_SDA_1
|
||||
|
||||
/* SPI flash
|
||||
*
|
||||
* PG12 SPI5_MISO
|
||||
|
||||
@ -53,4 +53,8 @@ ifeq ($(CONFIG_MTD_GD25),y)
|
||||
CSRCS += gd32f4xx_gd25.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MTD_AT24XX), y)
|
||||
CSRCS += gd32f4xx_at24.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/boards/Board.mk
|
||||
|
||||
@ -101,6 +101,41 @@
|
||||
|
||||
#define HAVE_GD25 1
|
||||
|
||||
#if !defined(CONFIG_MTD_GD25) || !defined(CONFIG_GD32F4_SPI5)
|
||||
# undef HAVE_GD25
|
||||
#endif
|
||||
|
||||
/* Can't support AT24 features if mountpoints are disabled or if we were not
|
||||
* asked to mount the AT25 part
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_DISABLE_MOUNTPOINT) || \
|
||||
!defined(CONFIG_GD32F450ZK_EVAL_GD25_BLOCKMOUNT)
|
||||
# undef HAVE_GD25
|
||||
#endif
|
||||
|
||||
#define HAVE_AT24 1
|
||||
|
||||
/* AT24 Serial EEPROM
|
||||
*
|
||||
* A AT24C02C Serial EEPPROM was used for tested I2C0.
|
||||
*/
|
||||
|
||||
#define AT24_BUS 0
|
||||
#define AT24_MINOR 0
|
||||
|
||||
#if !defined(CONFIG_MTD_AT24XX) || !defined(CONFIG_GD32F4_I2C0)
|
||||
# undef HAVE_AT24
|
||||
#endif
|
||||
|
||||
/* Can't support AT24 features if mountpoints are disabled or if we were not
|
||||
* asked to mount the AT25 part
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_GD32F450ZK_EVAL_AT24_TEST
|
||||
# undef HAVE_AT24
|
||||
#endif
|
||||
|
||||
/* GPIO pins used by the GPIO Subsystem */
|
||||
|
||||
#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */
|
||||
@ -144,6 +179,18 @@ void gd32_spidev_initialize(void);
|
||||
int gd32_gd25_automount(int minor);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gd32_at24_wr_test
|
||||
*
|
||||
* Description:
|
||||
* Write and read the AT24 serial EEPROM test.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_AT24
|
||||
int gd32_at24_wr_test(int minor);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gd32_gpio_initialize
|
||||
*
|
||||
|
||||
@ -138,7 +138,7 @@ int board_app_initialize(uintptr_t arg)
|
||||
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_MTD_GD25
|
||||
# ifdef HAVE_GD25
|
||||
|
||||
ret = gd32_gd25_automount(0);
|
||||
if (ret < 0)
|
||||
@ -149,7 +149,18 @@ int board_app_initialize(uintptr_t arg)
|
||||
|
||||
# endif
|
||||
|
||||
#endif
|
||||
# ifdef HAVE_AT24
|
||||
|
||||
ret = gd32_at24_wr_test(AT24_MINOR);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \
|
||||
%d\n", ret);
|
||||
}
|
||||
|
||||
# endif
|
||||
|
||||
#endif /* CONFIG_FS_NXFFS */
|
||||
|
||||
#ifdef CONFIG_DEV_GPIO
|
||||
/* Register the GPIO driver */
|
||||
|
||||
155
boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_at24.c
Normal file
155
boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_at24.c
Normal file
@ -0,0 +1,155 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_at24.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/mtd/mtd.h>
|
||||
#include <nuttx/kmalloc.h>
|
||||
|
||||
#include "gd32f4xx.h"
|
||||
#include "gd32f450z_eval.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gd32_at24_wr_test
|
||||
*
|
||||
* Description:
|
||||
* Write and read the AT24 serial EEPROM test.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_AT24
|
||||
|
||||
#define BUFFSIZE 16
|
||||
#define START_BLOCK 0
|
||||
|
||||
#if BUFFSIZE>=CONFIG_AT24XX_MTD_BLOCKSIZE
|
||||
# define NBLOCK (BUFFSIZE/CONFIG_AT24XX_MTD_BLOCKSIZE)
|
||||
#else
|
||||
# error "BUFFSIZE should bigger than CONFIG_AT24XX_MTD_BLOCKSIZE"
|
||||
#endif
|
||||
|
||||
const uint8_t write_buf[BUFFSIZE] =
|
||||
{
|
||||
0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
|
||||
0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf
|
||||
};
|
||||
|
||||
int gd32_at24_wr_test(int minor)
|
||||
{
|
||||
struct i2c_master_s *i2c;
|
||||
struct mtd_dev_s *at24;
|
||||
static bool initialized = false;
|
||||
int ret;
|
||||
ssize_t nblocks;
|
||||
uint8_t *read_buf;
|
||||
|
||||
/* Have we already initialized? */
|
||||
|
||||
if (!initialized)
|
||||
{
|
||||
/* No.. Get the I2C port driver */
|
||||
|
||||
finfo("Initialize TWI%d\n", AT24_BUS);
|
||||
i2c = gd32_i2cbus_initialize(AT24_BUS);
|
||||
if (!i2c)
|
||||
{
|
||||
ferr("ERROR: Failed to initialize TWI%d\n", AT24_BUS);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Now bind the I2C interface to the AT24 I2C EEPROM driver */
|
||||
|
||||
finfo("Bind the AT24 EEPROM driver to TWI%d\n", AT24_BUS);
|
||||
at24 = at24c_initialize(i2c);
|
||||
if (!at24)
|
||||
{
|
||||
ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n",
|
||||
AT24_BUS);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Now we are initializeed */
|
||||
|
||||
initialized = true;
|
||||
}
|
||||
|
||||
/* Write start block is START_BLOCK, number of block is 2 */
|
||||
|
||||
nblocks = at24->bwrite(at24, START_BLOCK, NBLOCK, write_buf);
|
||||
if (nblocks < NBLOCK)
|
||||
{
|
||||
ferr("ERROR: AT24 write failed: %zd\n", nblocks);
|
||||
gd32_i2cbus_uninitialize(i2c);
|
||||
return (int)nblocks;
|
||||
}
|
||||
|
||||
read_buf = (uint8_t *)kmm_malloc(BUFFSIZE);
|
||||
|
||||
/* Read the data write before */
|
||||
|
||||
nblocks = at24->bread(at24, START_BLOCK, NBLOCK, read_buf);
|
||||
if (nblocks < NBLOCK)
|
||||
{
|
||||
ferr("ERROR: AT24 read failed: %zd\n", nblocks);
|
||||
gd32_i2cbus_uninitialize(i2c);
|
||||
return (int)nblocks;
|
||||
}
|
||||
|
||||
if (memcmp(read_buf, write_buf, BUFFSIZE) != 0)
|
||||
{
|
||||
ferr("ERROR: Read buffer does not match write buffer\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Release the I2C instance.
|
||||
* REVISIT: Need an interface to release the AT24 instance too
|
||||
*/
|
||||
|
||||
ret = gd32_i2cbus_uninitialize(i2c);
|
||||
if (ret < 0)
|
||||
{
|
||||
ferr("ERROR: Failed to release the I2C interface: %d\n", ret);
|
||||
}
|
||||
|
||||
syslog(LOG_INFO, "INFO: I2C EEPROM write and read success: \
|
||||
%d\n", ret);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* HAVE_AT24 */
|
||||
@ -87,7 +87,7 @@ int gd32_gd25_automount(int minor)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_GD32F4_GD25_FTL)
|
||||
#if defined(CONFIG_GD32F450ZK_EVAL_GD25_FTL)
|
||||
/* And finally, use the FTL layer to wrap the MTD driver as a block
|
||||
* driver at /dev/mtdblockN, where N=minor device number.
|
||||
*/
|
||||
@ -100,7 +100,7 @@ int gd32_gd25_automount(int minor)
|
||||
return ret;
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_GD32F4_GD25_NXFFS)
|
||||
#elif defined(CONFIG_GD32F450ZK_EVAL_GD25_NXFFS)
|
||||
/* Initialize to provide NXFFS on the MTD interface */
|
||||
|
||||
ret = nxffs_initialize(mtd);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user