PIC32MZ: Add error exception handling and interrupt decode logic
This commit is contained in:
Gregory Nutt
parent
6798e67177
commit
65d762f902
@ -64,6 +64,7 @@ endif
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# Required PIC32MZ files
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CHIP_ASRCS =
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CHIP_CSRCS = pic32mz-lowinit.c pic32mz-irq.c pic32mz-timerisr.c
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CHIP_CSRCS = pic32mz-lowinit.c pic32mz-exception.c pic32mz-decodeirq.c
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CHIP_CSRCS += pic32mz-irq.c pic32mz-timerisr.c
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# Configuration-dependent PIC32MZ files
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199
arch/mips/src/pic32mz/pic32mz-decodeirq.c
Normal file
199
arch/mips/src/pic32mz/pic32mz-decodeirq.c
Normal file
@ -0,0 +1,199 @@
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/****************************************************************************
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* arch/mips/src/pic32mz/pic32mz-decodeirq.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <debug.h>
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#include <stdint.h>
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#include <assert.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip/pic32mz-int.h"
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#include "group/group.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: pic32mz_decodeirq
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*
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* Description:
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* Called from assembly language logic when an interrupt exception occurs.
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* This function decodes and dispatches the interrupt.
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*
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****************************************************************************/
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uint32_t *pic32mz_decodeirq(uint32_t *regs)
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{
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#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
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uint32_t *savestate;
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#endif
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uint32_t regval;
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int irq;
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/* If the board supports LEDs, turn on an LED now to indicate that we are
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* processing an interrupt.
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*/
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board_led_on(LED_INIRQ);
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/* Save the current value of current_regs (to support nested interrupt
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* handling). Then set current_regs to regs, indicating that this is
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* the interrupted context that is being processed now.
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*/
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#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
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savestate = (uint32_t*)current_regs;
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#else
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DEBUGASSERT(current_regs == NULL);
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#endif
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current_regs = regs;
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/* Loop while there are pending interrupts with priority greater than zero */
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for (;;)
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{
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/* Read the INTSTAT register. This register contains both the priority
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* and the interrupt vector number.
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*/
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regval = getreg32(PIC32MZ_INT_INTSTAT);
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if ((regval & INT_INTSTAT_SRIPL_MASK) == 0)
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{
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/* Break out of the loop when the priority is zero meaning that
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* there are no further pending interrupts.
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*/
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break;
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}
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/* Get the vector number. The IRQ numbers have been arranged so that
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* vector numbers and NuttX IRQ numbers are the same value.
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*/
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irq = ((regval) & INT_INTSTAT_SIRQ_MASK) >> INT_INTSTAT_SIRQ_SHIFT;
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/* Deliver the IRQ */
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irq_dispatch(irq, regs);
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}
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/* If a context switch occurred while processing the interrupt then
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* current_regs may have change value. If we return any value different
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* from the input regs, then the lower level will know that a context
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* switch occurred during interrupt processing.
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*/
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regs = (uint32_t*)current_regs;
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#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV)
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/* Check for a context switch. If a context switch occurred, then
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* current_regs will have a different value than it did on entry. If an
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* interrupt level context switch has occurred, then restore the floating
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* point state and the establish the correct address environment before
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* returning from the interrupt.
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*/
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if (regs != current_regs)
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{
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#ifdef CONFIG_ARCH_FPU
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/* Restore floating point registers */
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up_restorefpu((uint32_t*)current_regs);
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#endif
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#ifdef CONFIG_ARCH_ADDRENV
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/* Make sure that the address environment for the previously
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* running task is closed down gracefully (data caches dump,
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* MMU flushed) and set up the address environment for the new
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* thread at the head of the ready-to-run list.
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*/
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(void)group_addrenv(NULL);
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#endif
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}
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#endif
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#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
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/* Restore the previous value of current_regs. NULL would indicate that
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* we are no longer in an interrupt handler. It will be non-NULL if we
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* are returning from a nested interrupt.
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*
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* REVISIT: There are task switching issues! You should not enable
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* nested interrupts unless you are ready to deal with the complexities
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* of fixing nested context switching. The logic here is insufficient.
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*/
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current_regs = savestate;
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if (current_regs == NULL)
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{
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board_led_off(LED_INIRQ);
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}
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#else
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current_regs = NULL;
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board_led_off(LED_INIRQ);
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#endif
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return regs;
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}
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198
arch/mips/src/pic32mz/pic32mz-exception.c
Normal file
198
arch/mips/src/pic32mz/pic32mz-exception.c
Normal file
@ -0,0 +1,198 @@
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/****************************************************************************
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* arch/mips/src/pic32mz/pic32mz-exception.c
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include <arch/pic32mz/cp0.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "chip/pic32mz-int.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Name: pic32mz_exception
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*
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* Description:
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* Called from assembly language logic on all other exceptions.
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*
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************************************************************************************/
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uint32_t *pic32mz_exception(uint32_t *regs)
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{
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#ifdef CONFIG_DEBUG
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uint32_t cause;
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uint32_t epc;
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#endif
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/* If the board supports LEDs, turn on an LED now to indicate that we are
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* processing an interrupt.
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*/
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board_led_on(LED_INIRQ);
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#ifdef CONFIG_DEBUG
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/* Get the cause of the exception from the CAUSE register */
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asm volatile("\tmfc0 %0,$13,0\n" : "=r"(cause));
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asm volatile("\tmfc0 %0,$14,0\n" : "=r"(epc));
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#ifdef CONFIG_DEBUG_VERBOSE
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switch (cause & CP0_CAUSE_EXCCODE_MASK)
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{
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case CP0_CAUSE_EXCCODE_INT: /* Interrupt */
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llvdbg("EXCEPTION: Interrupt"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_TLBL: /* TLB exception (load or instruction fetch) */
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llvdbg("EXCEPTION: TLB exception (load or instruction fetch)"
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" CAUSE: %08x EPC:%08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_TLBS: /* TLB exception (store) */
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llvdbg("EXCEPTION: TLB exception (store)"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_ADEL: /* Address error exception (load or instruction fetch) */
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llvdbg("EXCEPTION: Address error exception (load or instruction fetch)"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_ADES: /* Address error exception (store) */
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llvdbg("EXCEPTION: Address error exception (store)"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_IBE: /* Bus error exception (instruction fetch) */
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llvdbg("EXCEPTION: Bus error exception (instruction fetch)"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_DBE: /* Bus error exception (data reference: load or store) */
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llvdbg("EXCEPTION: Bus error exception (data reference: load or store)"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_SYS: /* Syscall exception */
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llvdbg("EXCEPTION: Syscall exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_BP: /* Breakpoint exception */
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llvdbg("EXCEPTION: Breakpoint exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_RI: /* Reserved instruction exception */
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llvdbg("EXCEPTION: Reserved instruction exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_CPU: /* Coprocessor Unusable exception */
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llvdbg("EXCEPTION: Coprocessor Unusable exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_OV: /* Arithmetic Overflow exception */
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llvdbg("EXCEPTION: Arithmetic Overflow exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_TR: /* Trap exception */
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llvdbg("EXCEPTION: Trap exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_FPE: /* Floating point exception */
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llvdbg("EXCEPTION: Floating point exception"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_C2E: /* Precise Coprocessor 2 exceptions */
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llvdbg("EXCEPTION: Precise Coprocessor 2 exceptions"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_MDMX: /* MDMX Unusable (MIPS64) */
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llvdbg("EXCEPTION: MDMX Unusable (MIPS64)"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_WATCH: /* WatchHi/WatchLo address */
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llvdbg("EXCEPTION: WatchHi/WatchLo address"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_MCHECK: /* Machine check */
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llvdbg("EXCEPTION: Machine check"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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case CP0_CAUSE_EXCCODE_CACHEERR: /* Cache error */
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llvdbg("EXCEPTION: Cache error"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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default:
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llvdbg("EXCEPTION: Unknown"
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" CAUSE: %08x EPC: %08x\n", cause, epc);
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break;
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}
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#else
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lldbg("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc);
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#endif
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#endif
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/* Crash with currents_regs set so that we can dump the register contents. */
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current_regs = regs;
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PANIC();
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return regs; /* Won't get here */
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}
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