configs/metro-m4: Fix Metro M4 compile and link. This rippled back to more changes in arch/arm/src/samd5e5, like the sercom logic was not in the compile! Also a great opporunity to improve some naming.
This commit is contained in:
Gregory Nutt
parent
41666dafa8
commit
65e102ee6b
@ -88,7 +88,8 @@ endif
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CHIP_ASRCS =
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CHIP_CSRCS = sam_clockconfig.c sam_cmcc.c sam_gclk.c sam_irq.c
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CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_start.c sam_usart.c
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CHIP_CSRCS += sam_lowputc.c sam_port.c sam_serial.c sam_sercom.c sam_start.c
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CHIP_CSRCS += sam_usart.c
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# Configuration-dependent SAMD5x/E5x files
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@ -732,7 +732,7 @@ static void sam_dfll_configure(const struct sam_dfll_config_s *config)
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{
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/* Configure the GCLK channel */
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sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk);
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sam_gclk_chan_enable(GCLK_CHAN_OSCCTRL_DFLL, config->gclk, true);
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}
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/* Setup the DFLLMUL register */
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@ -936,7 +936,7 @@ static void sam_dpll_gclkchannel(uint8_t chan,
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{
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/* Yes.. configure the GCLK channel */
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sam_gclk_chan_enable(chan, config->gclk);
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sam_gclk_chan_enable(chan, config->gclk, true);
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}
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}
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@ -209,13 +209,14 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
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* Input Parameters:
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* channel - Index of the GCLK channel to be enabled
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* srcgen - The GCLK source generator index
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* wrlock - True: set writelock
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen)
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void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock)
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{
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irqstate_t flags;
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uint32_t regaddr;
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@ -235,14 +236,23 @@ void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen)
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regval = GCLK_PCHCTRL_GEN(srcgen);
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putreg32(regval, regaddr);
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/* Enable the peripheral channel */
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/* Enable the peripheral channel, setting the writelock if so requested. */
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regval |= GCLK_PCHCTRL_CHEN;
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if (wrlock)
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{
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regval |= GCLK_PCHCTRL_WRTLOCK;
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}
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putreg32(regval, regaddr);
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/* Wait for clock synchronization */
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while ((getreg32(regaddr) &GCLK_PCHCTRL_CHEN) == 0);
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while ((getreg32(regaddr) &GCLK_PCHCTRL_CHEN) == 0)
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{
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}
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leave_critical_section(flags);
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}
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@ -116,13 +116,14 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config);
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* Input Parameters:
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* channel - Index of the GCLK channel to be enabled
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* srcgen - The GCLK source generator index
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* wrlock - True: set writelock
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen);
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void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock);
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/****************************************************************************
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* Name: sam_gclk_chan_disable
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@ -1142,7 +1142,6 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
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irqstate_t flags;
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uint32_t regval;
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uint32_t ctrla = 0;
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int channel;
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i2cinfo("I2C%d Initializing\n", priv->attr->i2c);
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@ -1154,10 +1153,6 @@ static void i2c_hw_initialize(struct sam_i2c_dev_s *priv, uint32_t frequency)
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/* Configure the GCLKs for the SERCOM module */
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sercom_coreclk_configure(priv->attr->sercom, priv->attr->coregen, false);
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channel = priv->attr->sercom + GCLK_CHAN_SERCOM0_CORE;
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sam_gclk_chan_enable(channel, priv->attr->coregen);
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sercom_slowclk_configure(priv->attr->sercom, priv->attr->slowgen);
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/* Check if module is enabled */
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@ -1243,12 +1238,12 @@ static void i2c_pad_configure(struct sam_i2c_dev_s *priv)
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if (priv->attr->pad0 != 0)
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{
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sam_configport(priv->attr->pad0);
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sam_portconfig(priv->attr->pad0);
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}
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if (priv->attr->pad1 != 0)
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{
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sam_configport(priv->attr->pad1);
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sam_portconfig(priv->attr->pad1);
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}
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}
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@ -251,22 +251,22 @@ sam_pad_configure(const struct sam_usart_config_s * const config)
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if (config->pad0 != 0)
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{
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sam_configport(config->pad0);
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sam_portconfig(config->pad0);
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}
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if (config->pad1 != 0)
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{
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sam_configport(config->pad1);
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sam_portconfig(config->pad1);
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}
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if (config->pad2 != 0)
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{
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sam_configport(config->pad2);
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sam_portconfig(config->pad2);
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}
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if (config->pad3 != 0)
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{
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sam_configport(config->pad3);
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sam_portconfig(config->pad3);
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}
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}
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#endif
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@ -284,7 +284,6 @@ sam_pad_configure(const struct sam_usart_config_s * const config)
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#ifdef SAMD5E5_HAVE_USART
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int sam_usart_internal(const struct sam_usart_config_s * const config)
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{
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int channel;
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int ret;
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/* Enable clocking to the SERCOM module */
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@ -294,10 +293,6 @@ int sam_usart_internal(const struct sam_usart_config_s * const config)
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/* Configure the GCLKs for the SERCOM module */
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sercom_coreclk_configure(config->sercom, config->coregen, false);
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channel = config->sercom + GCLK_CHAN_SERCOM0_CORE;
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sam_gclk_chan_enable(channel, config->coregen);
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sercom_slowclk_configure(config->sercom, config->slowgen);
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/* Set USART configuration according to the board configuration */
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@ -445,14 +445,14 @@ static inline void sam_configreset(uintptr_t base, port_pinset_t pinset)
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****************************************************************************/
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/****************************************************************************
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* Name: sam_configport
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* Name: sam_portconfig
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*
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* Description:
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* Configure a PORT pin based on bit-encoded description of the pin.
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*
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****************************************************************************/
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int sam_configport(port_pinset_t pinset)
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int sam_portconfig(port_pinset_t pinset)
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{
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uintptr_t base = sam_portbase(pinset);
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irqstate_t flags;
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@ -55,7 +55,7 @@
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* Pre-processor Declarations
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****************************************************************************/
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/* Bit-encoded input to sam_configport() */
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/* Bit-encoded input to sam_portconfig() */
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/* 24-bit Encoding. This could be compacted into 16-bits by making the bit usage
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* mode specific. However, by giving each bit field a unique position, we handle
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@ -344,7 +344,7 @@ extern "C"
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****************************************************************************/
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/****************************************************************************
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* Name: sam_configport
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* Name: sam_portconfig
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*
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* Description:
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* Configure a PORT pin based on bit-encoded description of the pin.
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@ -354,7 +354,7 @@ extern "C"
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*
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****************************************************************************/
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int sam_configport(port_pinset_t pinset);
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int sam_portconfig(port_pinset_t pinset);
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/****************************************************************************
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* Name: sam_portwrite
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@ -47,30 +47,20 @@
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#include "sam_config.h"
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#include "sam_pm.h"
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#include "chip.h"
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#include "chip/sam_pm.h"
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#include "sam_gclk.h"
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#include "sam_sercom.h"
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#include <arch/board/board.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#undef HAVE_SERCOM0_4
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#if defined(CONFIG_SAMD5E5_SERCOM0) || defined(CONFIG_SAMD5E5_SERCOM1) || \
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defined(CONFIG_SAMD5E5_SERCOM2) || defined(CONFIG_SAMD5E5_SERCOM3) || \
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defined(CONFIG_SAMD5E5_SERCOM4)
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# define HAVE_SERCOM0_4
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#endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static bool g_slowclk_configured = false;
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#ifdef CONFIG_DEBUG_ASSERTIONS
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static uint8_t g_slowclk_gclkgen = 0xff;
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static uint8_t g_slowgen = 0xff;
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#endif
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static const uint8_t g_corclk_channel[SAMD5E5_NSERCOM] =
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@ -174,46 +164,16 @@ void sercom_enable(int sercom)
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*
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****************************************************************************/
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void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock)
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void sercom_coreclk_configure(int sercom, int coregen, bool wrlock)
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{
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uint16_t regval;
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uint8_t gclkcore;
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uint8_t corechan;
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DEBUGASSERT((unsigned)sercom < SAMD5E5_NSERCOM);
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/* Set up the SERCOMn_GCLK_ID_CORE clock */
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gclkcore = g_corclk_channel[sercom];
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regval = ((uint16_t)gclkcore << GCLK_CLKCTRL_ID_SHIFT);
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/* Select and disable the SERCOMn_GCLK_ID_CORE generic clock */
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Wait for clock to become disabled */
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while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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/* Select the SERCOMn_GCLK_ID_CORE source clock generator */
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regval |= (uint16_t)gclkgen << GCLK_CLKCTRL_GEN_SHIFT;
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/* Write the new configuration */
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Enable the SERCOMn_GCLK_ID_CORE generic clock, optionally locking
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* further writes to this GCLK.
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*/
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regval |= GCLK_CLKCTRL_CLKEN;
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if (wrlock)
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{
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regval |= GCLK_CLKCTRL_WRTLOCK;
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}
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putreg16(regval, SAM_GCLK_CLKCTRL);
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corechan = g_corclk_channel[sercom];
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sam_gclk_chan_enable(corechan, coregen, wrlock);
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}
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/****************************************************************************
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@ -230,7 +190,7 @@ void sercom_coreclk_configure(int sercom, int gclkgen, bool wrlock)
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*
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****************************************************************************/
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void sercom_slowclk_configure(int sercom, int gclkgen)
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void sercom_slowclk_configure(int sercom, int slowgen)
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{
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DEBUGASSERT((unsigned)sercom < SAMD5E5_NSERCOM);
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@ -242,7 +202,7 @@ void sercom_slowclk_configure(int sercom, int gclkgen)
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* of SERCOM modules and, hence, only need to configured once.
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*/
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sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, gclkgen);
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sam_gclk_chan_enable(GCLK_CHAN_SERCOMn_SLOW, slowgen, true);
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/* The slow clock is now configured and should not be re=configured
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* again.
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@ -250,7 +210,7 @@ void sercom_slowclk_configure(int sercom, int gclkgen)
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g_slowclk_configured = true;
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#ifdef CONFIG_DEBUG_ASSERTIONS
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g_slowclk_gclkgen = (uint8_t)gclkgen;
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g_slowgen = (uint8_t)slowgen;
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#endif
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}
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@ -261,7 +221,7 @@ void sercom_slowclk_configure(int sercom, int gclkgen)
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else
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{
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DEBUGASSERT((int)g_slowclk_gclkgen == gclkgen);
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DEBUGASSERT((int)g_slowgen == slowgen);
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}
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#endif
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}
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@ -1506,22 +1506,22 @@ static void spi_pad_configure(struct sam_spidev_s *priv)
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if (priv->pad0 != 0)
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{
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sam_configport(priv->pad0);
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sam_portconfig(priv->pad0);
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}
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if (priv->pad1 != 0)
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{
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sam_configport(priv->pad1);
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sam_portconfig(priv->pad1);
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}
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if (priv->pad2 != 0)
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{
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sam_configport(priv->pad2);
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sam_portconfig(priv->pad2);
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}
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if (priv->pad3 != 0)
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{
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sam_configport(priv->pad3);
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sam_portconfig(priv->pad3);
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}
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}
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@ -1576,10 +1576,6 @@ struct spi_dev_s *sam_spibus_initialize(int port)
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struct sam_spidev_s *priv;
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irqstate_t flags;
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uint32_t regval;
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int channel;
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#if 0 /* Not used */
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int ret;
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#endif
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/* Get the port state structure */
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@ -1663,10 +1659,6 @@ struct spi_dev_s *sam_spibus_initialize(int port)
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/* Configure the GCLKs for the SERCOM module */
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sercom_coreclk_configure(priv->sercom, priv->coregen, false);
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channel = priv->sercom + GCLK_CHAN_SERCOM0_CORE;
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sam_gclk_chan_enable(channel, priv->coregen);
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sercom_slowclk_configure(priv->sercom, priv->slowgen);
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/* Set the SERCOM in SPI master mode (no address) */
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@ -80,6 +80,7 @@
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#include "up_arch.h"
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#include "up_internal.h"
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#include "sam_port.h"
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#include "metro-m4.h"
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#include <arch/board/board.h>
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@ -206,7 +207,7 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain,
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void board_autoled_initialize(void)
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{
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(void)sam_configport(PORT_RED_LED);
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(void)sam_portconfig(PORT_RED_LED);
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}
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/****************************************************************************
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@ -52,7 +52,7 @@
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****************************************************************************/
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/****************************************************************************
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* Name: sam_boardinitialize
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* Name: sam_board_initialize
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*
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* Description:
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* All SAMD5/E5 architectures must provide the following entry point.
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@ -62,7 +62,7 @@
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*
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****************************************************************************/
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void sam_boardinitialize(void)
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void sam_board_initialize(void)
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{
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#ifdef CONFIG_ARCH_LEDS
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/* Configure on-board LEDs if LED support has been selected. */
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@ -60,6 +60,7 @@
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#include <nuttx/power/pm.h>
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#include "up_arch.h"
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#include "sam_port.h"
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#include "metro-m4.h"
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@ -188,7 +189,7 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain,
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void board_userled_initialize(void)
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{
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(void)sam_configport(PORT_STATUS_LED);
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(void)sam_portconfig(PORT_STATUS_LED);
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}
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/****************************************************************************
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