In at45db_bwrite, the buffer is not increased when writing more than 1 page. Sourceforge bug #34
This commit is contained in:
Gregory Nutt
parent
c4978f7ef0
commit
6626f62b08
@ -2,7 +2,7 @@
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* drivers/mtd/at45db.c
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* Driver for SPI-based AT45DB161D (16Mbit)
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*
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* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2010-2011, 2013-2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -210,14 +210,14 @@ struct at45db_dev_s
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/* Lock and per-transaction configuration */
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static void at45db_lock(struct at45db_dev_s *priv);
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static inline void at45db_unlock(struct at45db_dev_s *priv);
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static void at45db_lock(FAR struct at45db_dev_s *priv);
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static inline void at45db_unlock(FAR struct at45db_dev_s *priv);
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/* Power management */
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#ifdef CONFIG_AT45DB_PWRSAVE
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static void at45db_pwrdown(struct at45db_dev_s *priv);
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static void at45db_resume(struct at45db_dev_s *priv);
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static void at45db_pwrdown(FAR struct at45db_dev_s *priv);
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static void at45db_resume(FAR struct at45db_dev_s *priv);
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#else
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# define at45db_pwrdown(priv)
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# define at45db_resume(priv)
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@ -225,23 +225,23 @@ static void at45db_resume(struct at45db_dev_s *priv);
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/* Low-level AT45DB Helpers */
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static inline int at45db_rdid(struct at45db_dev_s *priv);
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static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv);
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static uint8_t at45db_waitbusy(struct at45db_dev_s *priv);
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static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t offset);
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static inline int at32db_chiperase(struct at45db_dev_s *priv);
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static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *buffer,
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off_t offset);
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static inline int at45db_rdid(FAR struct at45db_dev_s *priv);
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static inline uint8_t at45db_rdsr(FAR struct at45db_dev_s *priv);
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static uint8_t at45db_waitbusy(FAR struct at45db_dev_s *priv);
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static inline void at45db_pgerase(FAR struct at45db_dev_s *priv, off_t offset);
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static inline int at32db_chiperase(FAR struct at45db_dev_s *priv);
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static inline void at45db_pgwrite(FAR struct at45db_dev_s *priv,
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FAR const uint8_t *buffer, off_t offset);
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/* MTD driver methods */
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static int at45db_erase(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks);
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static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock,
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size_t nblocks, FAR uint8_t *buf);
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size_t nblocks, FAR uint8_t *buf);
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static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock,
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size_t nblocks, FAR const uint8_t *buf);
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size_t nblocks, FAR const uint8_t *buf);
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static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbytes,
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FAR uint8_t *buffer);
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FAR uint8_t *buffer);
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static int at45db_ioctl(FAR struct mtd_dev_s *mtd, int cmd, unsigned long arg);
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/************************************************************************************
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@ -266,21 +266,21 @@ static const uint8_t g_binpgsize[BINPGSIZE_SIZE] = {0x3d, 0x2a, 0x80, 0xa6};
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* Name: at45db_lock
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************************************************************************************/
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static void at45db_lock(struct at45db_dev_s *priv)
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static void at45db_lock(FAR struct at45db_dev_s *priv)
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{
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/* On SPI busses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the busses for a sequence of
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* transfers. The bus should be locked before the chip is selected.
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/* On SPI buses where there are multiple devices, it will be necessary to lock SPI
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* to have exclusive access to the buses for a sequence of transfers. The bus
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& should be locked before the chip is selected.
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*
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* This is a blocking call and will not return until we have exclusiv access to
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* the SPI buss. We will retain that exclusive access until the bus is unlocked.
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* This is a blocking call and will not return until we have exclusive access to
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* the SPI bus. We will retain that exclusive access until the bus is unlocked.
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*/
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(void)SPI_LOCK(priv->spi, true);
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/* After locking the SPI bus, the we also need call the setfrequency, setbits, and
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* setmode methods to make sure that the SPI is properly configured for the device.
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* If the SPI buss is being shared, then it may have been left in an incompatible
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* If the SPI bus is being shared, then it may have been left in an incompatible
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* state.
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*/
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@ -293,7 +293,7 @@ static void at45db_lock(struct at45db_dev_s *priv)
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* Name: at45db_unlock
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************************************************************************************/
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static inline void at45db_unlock(struct at45db_dev_s *priv)
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static inline void at45db_unlock(FAR struct at45db_dev_s *priv)
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{
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(void)SPI_LOCK(priv->spi, false);
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}
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@ -303,7 +303,7 @@ static inline void at45db_unlock(struct at45db_dev_s *priv)
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************************************************************************************/
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#ifdef CONFIG_AT45DB_PWRSAVE
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static void at45db_pwrdown(struct at45db_dev_s *priv)
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static void at45db_pwrdown(FAR struct at45db_dev_s *priv)
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{
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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SPI_SEND(priv->spi, AT45DB_PWRDOWN);
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@ -316,7 +316,7 @@ static void at45db_pwrdown(struct at45db_dev_s *priv)
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************************************************************************************/
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#ifdef CONFIG_AT45DB_PWRSAVE
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static void at45db_resume(struct at45db_dev_s *priv)
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static void at45db_resume(FAR struct at45db_dev_s *priv)
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{
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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SPI_SEND(priv->spi, AT45DB_RESUME);
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@ -329,15 +329,15 @@ static void at45db_resume(struct at45db_dev_s *priv)
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* Name: at45db_rdid
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************************************************************************************/
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static inline int at45db_rdid(struct at45db_dev_s *priv)
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static inline int at45db_rdid(FAR struct at45db_dev_s *priv)
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{
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uint8_t capacity;
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uint8_t devid[3];
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fvdbg("priv: %p\n", priv);
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/* Configure the bus, and select this FLASH part. (The caller should alread have
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* loced the bus for exclusive access)
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/* Configure the bus, and select this FLASH part. (The caller should already have
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* locked the bus for exclusive access)
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*/
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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@ -427,7 +427,7 @@ static inline int at45db_rdid(struct at45db_dev_s *priv)
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* Name: at45db_rdsr
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************************************************************************************/
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static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv)
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static inline uint8_t at45db_rdsr(FAR struct at45db_dev_s *priv)
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{
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uint8_t retval;
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@ -442,18 +442,19 @@ static inline uint8_t at45db_rdsr(struct at45db_dev_s *priv)
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* Name: at45db_waitbusy
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************************************************************************************/
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static uint8_t at45db_waitbusy(struct at45db_dev_s *priv)
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static uint8_t at45db_waitbusy(FAR struct at45db_dev_s *priv)
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{
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uint8_t sr;
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/* Poll the device, waiting for it to report that it is ready */
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do
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{
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up_udelay(10);
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sr = (uint8_t)at45db_rdsr(priv);
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}
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{
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up_udelay(10);
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sr = (uint8_t)at45db_rdsr(priv);
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}
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while ((sr & AT45DB_SR_RDY) == 0);
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return sr;
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}
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@ -461,7 +462,7 @@ static uint8_t at45db_waitbusy(struct at45db_dev_s *priv)
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* Name: at45db_pgerase
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************************************************************************************/
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static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
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static inline void at45db_pgerase(FAR struct at45db_dev_s *priv, off_t sector)
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{
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uint8_t erasecmd[4];
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off_t offset = sector << priv->pageshift;
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@ -470,9 +471,9 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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* to wait as long between transactions (other processing can occur while the
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* chip is busy) but means that the chip must stay powered and that we must check
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* if the chip is still busy on each entry point.
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*/
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#ifdef CONFIG_AT45DB_PREWAIT
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@ -480,15 +481,15 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
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#endif
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/* "The Page Erase command can be used to individually erase any page in the main
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* memory array allowing the Buffer to Main Memory Page Program to be utilized at a
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* later time. ... To perform a page erase in the binary page size ..., the
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* opcode 81H must be loaded into the device, followed by three address bytes
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* ... When a low-to-high transition occurs on the CS pin, the part will erase the
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* selected page (the erased state is a logical 1). ... the status register and the
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* RDY/BUSY pin will indicate that the part is busy."
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* memory array allowing the Buffer to Main Memory Page Program to be utilized
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* at a later time. ... To perform a page erase in the binary page size ...,
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* the opcode 81H must be loaded into the device, followed by three address
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* bytes ... When a low-to-high transition occurs on the CS pin, the part will
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* erase the selected page (the erased state is a logical 1). ... the status
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* register and the RDY/BUSY pin will indicate that the part is busy."
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*/
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erasecmd[0] = AT45DB_PGERASE; /* Page erase command */
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erasecmd[0] = AT45DB_PGERASE; /* Page erase command */
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erasecmd[1] = (offset >> 16) & 0xff; /* 24-bit offset MS bytes */
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erasecmd[2] = (offset >> 8) & 0xff; /* 24-bit offset middle bytes */
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erasecmd[3] = offset & 0xff; /* 24-bit offset LS bytes */
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@ -513,15 +514,15 @@ static inline void at45db_pgerase(struct at45db_dev_s *priv, off_t sector)
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* Name: at32db_chiperase
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************************************************************************************/
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static inline int at32db_chiperase(struct at45db_dev_s *priv)
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static inline int at32db_chiperase(FAR struct at45db_dev_s *priv)
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{
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fvdbg("priv: %p\n", priv);
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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* to wait as long between transactions (other processing can occur while the
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* chip is busy) but means that the chip must stay powered and that we must check
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* if the chip is still busy on each entry point.
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*/
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#ifdef CONFIG_AT45DB_PREWAIT
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@ -530,10 +531,11 @@ static inline int at32db_chiperase(struct at45db_dev_s *priv)
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/* "The entire main memory can be erased at one time by using the Chip Erase
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* command. To execute the Chip Erase command, a 4-byte command sequence C7H, 94H,
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* 80H and 9AH must be clocked into the device. ... After the last bit of the opcode
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* sequence has been clocked in, the CS pin can be deasserted to start the erase
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* process. ... the Status Register will indicate that the device is busy. The Chip
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* Erase command will not affect sectors that are protected or locked down...
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* 80H and 9AH must be clocked into the device. ... After the last bit of the
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* opcode sequence has been clocked in, the CS pin can be deasserted to start the
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* erase process. ... the Status Register will indicate that the device is busy.
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* The Chip Erase command will not affect sectors that are protected or locked
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* down...
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*/
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SPI_SELECT(priv->spi, SPIDEV_FLASH, true);
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@ -554,8 +556,8 @@ static inline int at32db_chiperase(struct at45db_dev_s *priv)
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* Name: at45db_pgwrite
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************************************************************************************/
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static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *buffer,
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off_t page)
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static inline void at45db_pgwrite(FAR struct at45db_dev_s *priv,
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FAR const uint8_t *buffer, off_t page)
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{
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uint8_t wrcmd [4];
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off_t offset = page << priv->pageshift;
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@ -571,9 +573,9 @@ static inline void at45db_pgwrite(struct at45db_dev_s *priv, FAR const uint8_t *
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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* to wait as long between transactions (other processing can occur while the
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* chip is busy) but means that the chip must stay powered and that we must check
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* if the chip is still busy on each entry point.
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*/
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#ifdef CONFIG_AT45DB_PREWAIT
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@ -632,19 +634,21 @@ static int at45db_erase(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblo
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* Name: at45db_bread
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************************************************************************************/
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static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks,
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FAR uint8_t *buffer)
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static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock,
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size_t nblocks, FAR uint8_t *buffer)
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{
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FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
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ssize_t nbytes;
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/* On this device, we can handle the block read just like the byte-oriented read */
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nbytes = at45db_read(mtd, startblock << priv->pageshift, nblocks << priv->pageshift, buffer);
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nbytes = at45db_read(mtd, startblock << priv->pageshift,
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nblocks << priv->pageshift, buffer);
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if (nbytes > 0)
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{
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return nbytes >> priv->pageshift;
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}
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return nbytes;
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}
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@ -652,8 +656,8 @@ static ssize_t at45db_bread(FAR struct mtd_dev_s *mtd, off_t startblock, size_t
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* Name: at45db_bwrite
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************************************************************************************/
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static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock, size_t nblocks,
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FAR const uint8_t *buffer)
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static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock,
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size_t nblocks, FAR const uint8_t *buffer)
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{
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FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
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size_t pgsleft = nblocks;
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@ -673,6 +677,7 @@ static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock, size_t
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{
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at45db_pgwrite(priv, buffer, startblock);
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startblock++;
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buffer += (1 << priv->pageshift);
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}
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at45db_pwrdown(priv);
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@ -686,7 +691,7 @@ static ssize_t at45db_bwrite(FAR struct mtd_dev_s *mtd, off_t startblock, size_t
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************************************************************************************/
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static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbytes,
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FAR uint8_t *buffer)
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FAR uint8_t *buffer)
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{
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FAR struct at45db_dev_s *priv = (FAR struct at45db_dev_s *)mtd;
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uint8_t rdcmd [5];
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@ -710,9 +715,9 @@ static ssize_t at45db_read(FAR struct mtd_dev_s *mtd, off_t offset, size_t nbyte
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/* Higher performance write logic: We leave the chip busy after write and erase
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* operations. This improves write and erase performance because we do not have
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* to wait as long between transactions (other processing can occur while the chip
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* is busy) but means that the chip must stay powered and that we must check if
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* the chip is still busy on each entry point.
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* to wait as long between transactions (other processing can occur while the
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* chip is busy) but means that the chip must stay powered and that we must check
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* if the chip is still busy on each entry point.
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*/
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#ifdef CONFIG_AT45DB_PREWAIT
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@ -820,11 +825,11 @@ FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *spi)
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fvdbg("spi: %p\n", spi);
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/* Allocate a state structure (we allocate the structure instead of using
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* a fixed, static allocation so that we can handle multiple FLASH devices.
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* The current implementation would handle only one FLASH part per SPI
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* device (only because of the SPIDEV_FLASH definition) and so would have
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* to be extended to handle multiple FLASH parts on the same SPI bus.
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/* Allocate a state structure (we allocate the structure instead of using a fixed,
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* static allocation so that we can handle multiple FLASH devices. The current
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* implementation would handle only one FLASH part per SPI device (only because
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* of the SPIDEV_FLASH definition) and so would have to be extended to handle
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* multiple FLASH parts on the same SPI bus.
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*/
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priv = (FAR struct at45db_dev_s *)kmm_zalloc(sizeof(struct at45db_dev_s));
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@ -865,7 +870,9 @@ FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *spi)
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sr = at45db_waitbusy(priv);
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/* Check if the device is configured as 256, 512 or 1024 bytes-per-page device */
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/* Check if the device is configured as 256, 512 or 1024 bytes-per-page
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* device.
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*/
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if ((sr & AT45DB_SR_PGSIZE) == 0)
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{
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@ -895,10 +902,10 @@ FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *spi)
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fvdbg("Return %p\n", priv);
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return (FAR struct mtd_dev_s *)priv;
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||||
|
||||
/* On any failure, we need free memory allocations and release the lock that
|
||||
* we hold on the SPI bus. On failures, assume that we cannot talk to the
|
||||
* device to do any more.
|
||||
*/
|
||||
/* On any failure, we need free memory allocations and release the lock that
|
||||
* we hold on the SPI bus. On failures, assume that we cannot talk to the
|
||||
* device to do any more.
|
||||
*/
|
||||
|
||||
errout:
|
||||
at45db_unlock(priv);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user