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armv7/v8:Fix configuration csselr default configuration error.

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Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
This commit is contained in:
chenrun1 2023-05-26 19:18:34 +08:00 committed by Xiang Xiao
parent 22d1059c97
commit 665a140b21
2 changed files with 4 additions and 4 deletions
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4
arch/arm/src/armv7-m/nvic.h
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@ -679,8 +679,8 @@
/* Cache Size Selection Register (Cortex-M7) */
#define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */
# define NVIC_CSSELR_IND_ICACHE (0 << 0) /* 0=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (1 << 0) /* 1=Data Cache */
# define NVIC_CSSELR_IND_ICACHE (1 << 0) /* 0=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (0 << 0) /* 1=Data Cache */
#define NVIC_CSSELR_LEVEL_SHIFT (1) /* Bit 1-3: Selects cache level */
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)

4
arch/arm/src/armv8-m/nvic.h
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@ -778,8 +778,8 @@
/* Cache Size Selection Register */
#define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */
# define NVIC_CSSELR_IND_ICACHE (0 << 0) /* 0=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (1 << 0) /* 1=Data Cache */
# define NVIC_CSSELR_IND_ICACHE (1 << 0) /* 0=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (0 << 0) /* 1=Data Cache */
#define NVIC_CSSELR_LEVEL_SHIFT (1) /* Bit 1-3: Selects cache level */
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)