diff --git a/arch/Kconfig b/arch/Kconfig index 71049ff51b..92bdb83429 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -134,7 +134,7 @@ config CUSTOM_STACK bool default n -config ADDRENV +config ARCH_HAVE_ADDRENV bool default n @@ -154,6 +154,14 @@ config ARCH_HAVE_EXTCLK bool default n +config ARCH_ADDRENV + bool "Address environments" + default n + depends on ARCH_HAVE_ADDRENV + ---help--- + Support per-task address environments using the MMU... i.e., support + "processes" + menuconfig PAGING bool "On-demand paging" default n diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f93bb037f0..a874fdce3d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -18,7 +18,7 @@ config ARCH_CHIP_A1X select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_SDRAM select BOOT_RUNFROMSDRAM - select ADDRENV if EXPERIMENTAL + select ARCH_HAVE_ADDRENV if EXPERIMENTAL ---help--- Allwinner A1X family: A10, A10S (A12), A13 (ARM Cortex-A8) @@ -136,7 +136,7 @@ config ARCH_CHIP_SAMA5 select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_I2CRESET select ARCH_HAVE_TICKLESS - select ADDRENV if EXPERIMENTAL + select ARCH_HAVE_ADDRENV if EXPERIMENTAL ---help--- Atmel SAMA5 (ARM Cortex-A5) diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs index c437a0c27a..4c3755352b 100644 --- a/arch/arm/src/a1x/Make.defs +++ b/arch/arm/src/a1x/Make.defs @@ -82,7 +82,7 @@ CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c CMN_CSRCS += arm_va2pte.c endif -ifeq ($(CONFIG_ADDRENV),y) +ifeq ($(CONFIG_ARCH_ADDRENV),y) CMN_CSRCS += arm_addrenv.c endif diff --git a/arch/arm/src/armv7-a/arm_addrenv.c b/arch/arm/src/armv7-a/arm_addrenv.c index 0813ed7ef2..335ab205a0 100644 --- a/arch/arm/src/armv7-a/arm_addrenv.c +++ b/arch/arm/src/armv7-a/arm_addrenv.c @@ -38,7 +38,7 @@ * Low-level interfaces used in binfmt/ to instantiate tasks with address * environments. These interfaces all operate on type group_addrenv_t which * is an abstract representation of a task group's address environment and - * must be defined in arch/arch.h if CONFIG_ADDRENV is defined. + * must be defined in arch/arch.h if CONFIG_ARCH_ADDRENV is defined. * * up_addrenv_create - Create an address environment * up_addrenv_destroy - Destroy an address environment. @@ -72,7 +72,7 @@ #include #include -#ifdef CONFIG_ADDRENV +#ifdef CONFIG_ARCH_ADDRENV /**************************************************************************** * Pre-processor Definitions @@ -295,4 +295,4 @@ int up_addrenv_detach(FAR struct task_group_s *group, FAR struct tcb_s *tcb) return -ENOSYS; } -#endif /* CONFIG_ADDRENV */ +#endif /* CONFIG_ARCH_ADDRENV */ diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs index 222aa1c925..c588864c24 100644 --- a/arch/arm/src/sama5/Make.defs +++ b/arch/arm/src/sama5/Make.defs @@ -84,7 +84,7 @@ CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c CMN_CSRCS += arm_va2pte.c endif -ifeq ($(CONFIG_ADDRENV),y) +ifeq ($(CONFIG_ARCH_ADDRENV),y) CMN_CSRCS += arm_addrenv.c endif diff --git a/arch/z80/Kconfig b/arch/z80/Kconfig index f1a9b5ce62..ef2793b870 100644 --- a/arch/z80/Kconfig +++ b/arch/z80/Kconfig @@ -18,9 +18,6 @@ config ARCH_CHIP_Z8018006VSG bool "Z8018006VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z80180 @@ -28,9 +25,6 @@ config ARCH_CHIP_Z8018010VSG bool "Z8018010VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z80180 @@ -38,9 +32,6 @@ config ARCH_CHIP_Z8018008VSG bool "Z8018008VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z80180 @@ -48,9 +39,6 @@ config ARCH_CHIP_Z8018010FSG bool "Z8018010FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin QFP (11 pins N/C) Z80180 @@ -58,9 +46,6 @@ config ARCH_CHIP_Z8018008VEG bool "Z8018008VEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z80180 @@ -68,9 +53,6 @@ config ARCH_CHIP_Z8018006VEG bool "Z8018006VEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z80180 @@ -78,9 +60,6 @@ config ARCH_CHIP_Z8018006PSG bool "Z8018006PSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 64-pin DIP 6 MHz 5V Z80180 @@ -88,9 +67,6 @@ config ARCH_CHIP_Z8018008FSG bool "Z8018008FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin QFP (11 pins N/C) 8MHz 5V Z80180 @@ -98,9 +74,6 @@ config ARCH_CHIP_Z8018010PSG bool "Z8018010PSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 64-pin DIP 10MHz 5V Z80180 @@ -108,9 +81,6 @@ config ARCH_CHIP_Z8018006PEG bool "Z8018006PEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 64-pin DIP 6MHz 5V Z80180 @@ -118,9 +88,6 @@ config ARCH_CHIP_Z8018010VEG bool "Z8018010VEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- 68-pin PLCC 10MHz 5V Z80180 @@ -128,9 +95,6 @@ config ARCH_CHIP_Z8018010PEG bool "Z8018010PEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 64-pin DIP 10MHz 5V Z80180 @@ -138,9 +102,6 @@ config ARCH_CHIP_Z8018008PSG bool "Z8018008PSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 64-pin DIP 8MHz 5V Z80180 @@ -148,9 +109,6 @@ config ARCH_CHIP_Z8018006FSG bool "Z8018006FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin QFP (11 pins N/C) 6MHz 5V Z80180 @@ -158,41 +116,26 @@ config ARCH_CHIP_Z8018000XSO bool "Z8018000XSO" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8018010FEG bool "Z8018010FEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8018000WSO bool "Z8018000WSO" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8018008PEG bool "Z8018008PEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8018110FEG bool "Z8018110FEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80181 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin QFP Z80181 @@ -200,9 +143,6 @@ config ARCH_CHIP_Z8018233FSG bool "Z8018233FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- 100-pin QFP Z80182 @@ -210,9 +150,6 @@ config ARCH_CHIP_Z8018220AEG bool "Z8018220AEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin LQFP 20MHz 5V Z80182 @@ -220,9 +157,6 @@ config ARCH_CHIP_Z8018216FSG bool "Z8018216FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin QFP 16MHz 5V Z80182 @@ -230,9 +164,6 @@ config ARCH_CHIP_Z8018216ASG bool "Z8018216ASG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin LQFP Z80182 @@ -240,9 +171,6 @@ config ARCH_CHIP_Z8018233ASG bool "Z8018233ASG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin LQFP 33MHz 5V Z80182 @@ -250,9 +178,6 @@ config ARCH_CHIP_Z8019520FSG bool "Z8019520FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80195 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin QFP 20MHz 5V Z80195 @@ -260,9 +185,6 @@ config ARCH_CHIP_Z8019533FSG bool "Z8019533FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z80195 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin QFP 33MHz 5V Z80195 @@ -270,9 +192,6 @@ config ARCH_CHIP_Z8L18020VSG bool "Z8L18020VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8L180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pinn PLCC Z8L180 @@ -280,9 +199,6 @@ config ARCH_CHIP_Z8L18020FSG bool "Z8L18020FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8L180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin GFP 20MHz 3.3V Z8L180 @@ -290,17 +206,11 @@ config ARCH_CHIP_Z8L18020PSG bool "Z8L18020PSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8L180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8L18220ASG bool "Z8L18220ASG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8L182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 100-pin LQFP Z8L182 @@ -308,9 +218,6 @@ config ARCH_CHIP_Z8L18220FSG bool "Z8L18220FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8L182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- 100-pin QFP 20MHz 3.3V Z8L182 @@ -318,17 +225,11 @@ config ARCH_CHIP_Z8L18220AEG bool "Z8L18220AEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8L182 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8S18020VSG bool "Z8S18020VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z8S180 @@ -336,9 +237,6 @@ config ARCH_CHIP_Z8S18020VSG1960 bool "Z8S18020VSG1960" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z8S180 @@ -346,9 +244,6 @@ config ARCH_CHIP_Z8S18033VSG bool "Z8S18033VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z8S180 @@ -356,9 +251,6 @@ config ARCH_CHIP_Z8S18010FSG bool "Z8S18010FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- 80-pin QFP Z8S180 @@ -366,9 +258,6 @@ config ARCH_CHIP_Z8S18010VEG bool "Z8S18010VEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z8S180 @@ -376,9 +265,6 @@ config ARCH_CHIP_Z8S18020VEG bool "Z8S18020VEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z8S180 @@ -386,9 +272,6 @@ config ARCH_CHIP_Z8S18010VSG bool "Z8S18010VSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC Z8S180 @@ -396,9 +279,6 @@ config ARCH_CHIP_Z8S18020PSG bool "Z8S18020PSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- 64-pin DIP 10Mhz 5V Z8S180 @@ -406,9 +286,6 @@ config ARCH_CHIP_Z8S18033FSG bool "Z8S18033FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin QFP 33MHz 5V Z8S180 @@ -416,9 +293,6 @@ config ARCH_CHIP_Z8S18033FEG bool "Z8S18033FEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin QFP 33MHz 5V Z8S180 @@ -426,9 +300,6 @@ config ARCH_CHIP_Z8S18020FSG bool "Z8S18020FSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 80-pin QFP 20MHz 5V Z8S180 @@ -436,9 +307,6 @@ config ARCH_CHIP_Z8S18033VEG bool "Z8S18033VEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 68-pin PLCC 33MHz 5V Z8S180 @@ -446,9 +314,6 @@ config ARCH_CHIP_Z8S18010PSG bool "Z8S18010PSG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT ---help--- Z180: 64-pin DIP 10MHz 5V Z8S180 @@ -456,25 +321,16 @@ config ARCH_CHIP_Z8S18020FEG bool "Z8S18020FEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8S18010PEG bool "Z8S18010PEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8S18010FEG bool "Z8S18010FEG" select ARCH_CHIP_Z180 select ARCH_CHIP_Z8S180 - select ARCH_NOINTC - select ADDRENV - select HAVE_LOWSERIALINIT config ARCH_CHIP_Z8F6403 bool "Z8F6403" @@ -522,6 +378,10 @@ config ARCH_CHIP_Z8F640X config ARCH_CHIP_Z180 bool + select ARCH_NOINTC + select ARCH_HAVE_ADDRENV + select ARCH_ADDRENV + select HAVE_LOWSERIALINIT config ARCH_CHIP_Z80180 bool diff --git a/arch/z80/include/z180/arch.h b/arch/z80/include/z180/arch.h index 72306b9309..85422fdca2 100644 --- a/arch/z80/include/z180/arch.h +++ b/arch/z80/include/z180/arch.h @@ -64,7 +64,7 @@ * of the base address are implicitly zero (hence the 4KB boundary alignment). */ -#ifdef CONFIG_ADDRENV +#ifdef CONFIG_ARCH_ADDRENV typedef uint8_t hw_addrenv_t; /* At the task-level, the z180 address environment is represented as struct diff --git a/arch/z80/src/common/up_initialize.c b/arch/z80/src/common/up_initialize.c index a73c098236..df66b9fd41 100644 --- a/arch/z80/src/common/up_initialize.c +++ b/arch/z80/src/common/up_initialize.c @@ -138,7 +138,7 @@ void up_initialize(void) * needs to be done before any tasks are created). */ -#if CONFIG_ADDRENV +#if CONFIG_ARCH_ADDRENV (void)up_mmuinit(); #endif diff --git a/arch/z80/src/common/up_internal.h b/arch/z80/src/common/up_internal.h index bd5b0f70b5..0caf4d69a8 100644 --- a/arch/z80/src/common/up_internal.h +++ b/arch/z80/src/common/up_internal.h @@ -142,7 +142,7 @@ void up_sigdeliver(void); /* Defined in CPU-specific logic (only for Z180) */ -#if CONFIG_ADDRENV +#if CONFIG_ARCH_ADDRENV int up_mmuinit(void); #endif diff --git a/arch/z80/src/z180/z180_mmu.c b/arch/z80/src/z180/z180_mmu.c index c4ed03aa43..3289026f96 100644 --- a/arch/z80/src/z180/z180_mmu.c +++ b/arch/z80/src/z180/z180_mmu.c @@ -57,8 +57,8 @@ ****************************************************************************/ /* Configuration ************************************************************/ -#ifndef CONFIG_ADDRENV -# warning "OS address environment support is required (CONFIG_ADDRENV)" +#ifndef CONFIG_ARCH_ADDRENV +# warning "OS address environment support is required (CONFIG_ARCH_ADDRENV)" #endif #ifndef CONFIG_GRAN @@ -182,7 +182,7 @@ return g_physhandle ? OK : -ENOMEM; * Low-level interfaces used in binfmt/ to instantiate tasks with address * environments. These interfaces all operate on type group_addrenv_t which * is an abstract representation of a task group's address environment and - * must be defined in arch/arch.h if CONFIG_ADDRENV is defined. + * must be defined in arch/arch.h if CONFIG_ARCH_ADDRENV is defined. * * up_addrenv_create - Create an address environment * up_addrenv_destroy - Destroy an address environment.