arch/arm/src/stm32h7: Add stm32h7 sdmmc driver. This is the initial sdmmc driver for stm32h7. It is mostly copied from stm32f7, with modified register addresses and bits, and IDMA added. This is still WIP, it only works with IDMA.
This commit is contained in:
Jukka Laitinen
Gregory Nutt
parent
d1c9cf2e93
commit
66b0b0c09b
@ -195,6 +195,20 @@ config STM32H7_USBHOST_PKTDUMP
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default n
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depends on USBHOST
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config STM32H7_SDMMC1
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bool "SDMMC1"
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default n
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select STM32H7_SDMMC
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select ARCH_HAVE_SDIO
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select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
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config STM32H7_SDMMC2
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bool "SDMMC2"
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default n
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select STM32H7_SDMMC
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select ARCH_HAVE_SDIO
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select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
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menu "STM32H7 I2C Selection"
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config STM32H7_I2C1
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@ -763,6 +777,83 @@ config STM32H7_PM_SERIAL_ACTIVITY
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endif # PM
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endmenu # U[S]ART Configuration
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menu "SD/MMC Configuration"
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depends on STM32H7_SDMMC
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config STM32H7_SDMMC_XFRDEBUG
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bool "SDMMC transfer debug"
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depends on DEBUG_FS_INFO
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default n
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---help---
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Enable special debug instrumentation analyze SDMMC data transfers.
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This logic is as non-invasive as possible: It samples SDMMC
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registers at key points in the data transfer and then dumps all of
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the registers at the end of the transfer. If DEBUG_DMA is also
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enabled, then DMA register will be collected as well. Requires also
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DEBUG_FS and CONFIG_DEBUG_INFO.
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config STM32H7_SDMMC_IDMA
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bool "Support IDMA data transfers"
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default y
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select STM32H7_SDMMC_DMA
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depends on STM32H7_DMA
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---help---
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Support IDMA data transfers.
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menu "SDMMC1 Configuration"
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depends on STM32H7_SDMMC1
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config SDMMC1_WIDTH_D1_ONLY
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bool "Use D1 only on SDMMC1"
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default n
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---help---
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Select 1-bit transfer mode. Default: 4-bit transfer mode.
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config SDMMC1_SDIO_MODE
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bool "SDIO Card Support"
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default n
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---help---
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Build in additional support needed only for SDIO cards (vs. SD
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memory cards)
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config SDMMC1_SDIO_PULLUP
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bool "Enable internal Pull-Ups"
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default n
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---help---
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If you are using an external SDCard module that does not have the
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pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
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Module) then enable this option to activate the internal pull-up
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resistors.
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endmenu # "SDMMC1 Configuration"
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menu "SDMMC2 Configuration"
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depends on STM32H7_SDMMC2
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config SDMMC2_WIDTH_D1_ONLY
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bool "Use D1 only on SDMMC2"
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default n
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---help---
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Select 1-bit transfer mode. Default: 4-bit transfer mode.
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config SDMMC2_SDIO_MODE
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bool "SDIO Card Support"
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default n
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---help---
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Build in additional support needed only for SDIO cards (vs. SD
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memory cards)
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config SDMMC2_SDIO_PULLUP
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bool "Enable internal Pull-Ups"
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default n
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---help---
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If you are using an external SDCard module that does not have the
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pull-up resistors for the SDIO interface (like the Gadgeteer SD Card
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Module) then enable this option to activate the internal pull-up
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resistors.
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endmenu # "SDMMC2 Configuration"
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endmenu # "SD/MMC Configuration"
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config STM32H7_CUSTOM_CLOCKCONFIG
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bool "Custom clock configuration"
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default n
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@ -114,6 +114,10 @@ ifeq ($(CONFIG_STM32H7_SPI),y)
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CHIP_CSRCS += stm32_spi.c
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endif
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ifeq ($(CONFIG_STM32H7_SDMMC),y)
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CHIP_CSRCS += stm32_sdmmc.c
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endif
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += stm32_otgdev.c
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endif
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54
arch/arm/src/stm32h7/chip/stm32_sdmmc.h
Normal file
54
arch/arm/src/stm32h7/chip/stm32_sdmmc.h
Normal file
@ -0,0 +1,54 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32_sdmmc.h
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*
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* Copyright (C) 2016, 2019 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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* Jukka Laitinen <jukka.laitinen@iki.fi>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SDMMC_H
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#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SDMMC_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32H7_STM32H7X3XX)
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# include "stm32h7x3xx_sdmmc.h"
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#else
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# error "Unsupported STM32 H7 part"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_SDMMC_H */
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246
arch/arm/src/stm32h7/chip/stm32h7x3xx_sdmmc.h
Normal file
246
arch/arm/src/stm32h7/chip/stm32h7x3xx_sdmmc.h
Normal file
@ -0,0 +1,246 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/chip/stm32h7x3xx_sdmmc.h
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*
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* Copyright (C) 2009, 2011-2016, 2019 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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* Jukka Laitinen <jukka.laitinen@iki.fi>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SDMMC_H
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#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32H7X3XX_SDMMC_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */
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#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */
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#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */
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#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */
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#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */
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#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n))
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#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */
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#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */
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#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */
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#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */
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#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */
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#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */
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#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */
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#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */
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#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */
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#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */
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#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */
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#define STM32_SDMMC_IDMACTRLR_OFFSET 0x0050 /* SDMMC DMA control register */
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#define STM32_SDMMC_IDMABASE0R_OFFSET 0x0058 /* SDMMC IDMA buffer 0 base register */
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#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */
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/* Register Bitfield Definitions ****************************************************/
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#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */
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#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT)
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# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
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# define STM32_SDMMC_POWER_PWRCTRL_CYCLE (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
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# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
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#define STM32_SDMMC_POWER_RESET (0) /* Reset value */
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#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 9-0: Clock divide factor */
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#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0x3ff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#define STM32_SDMMC_CLKCR_PWRSAV (1 << 12) /* Bit 12: Power saving configuration bit */
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#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (14) /* Bits 12-11: Wide bus mode enable bits */
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#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT)
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# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */
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# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */
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# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */
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#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 16) /* Bit 16: STM32_SDMMC_CK dephasing selection bit */
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#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 17) /* Bit 17: HW Flow Control enable */
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#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */
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#define STM32_SDMMC_ARG_RESET (0) /* Reset value */
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#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0)
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#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT)
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#define STM32_SDMMC_CMD_CMDTRANS (1 << 6) /* Bit 6: The CPSM treats the command as a data transfer command */
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#define STM32_SDMMC_CMD_CMDSTOP (1 << 7) /* Bit 7: The CPSM treats the command as a Stop Transmission command */
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#define STM32_SDMMC_CMD_WAITRESP_SHIFT (8) /* Bits 8-9: Wait for response bits */
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#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT)
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# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */
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# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
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# define STM32_SDMMC_CMD_SHORTRESPONSE_NOCRC (2 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response, no CRC */
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# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
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#define STM32_SDMMC_CMD_WAITINT (1 << 10) /* Bit 10: CPSM waits for interrupt request */
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#define STM32_SDMMC_CMD_WAITPEND (1 << 11) /* Bit 11: CPSM Waits for ends of data transfer */
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#define STM32_SDMMC_CMD_CPSMEN (1 << 12) /* Bit 12: Command path state machine enable */
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#define STM32_SDMMC_CMD_DTHOLD (1 << 13) /* Bit 13: Hold new data block transmission and reception in the DPSM */
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#define STM32_SDMMC_CMD_BOOTMODE (1 << 14) /* Bit 14: Select bootmode */
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#define STM32_SDMMC_CMD_BOOTEN (1 << 15) /* Bit 15: Enable boot mode */
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#define STM32_SDMMC_CMD_SUSPEND (1 << 16) /* Bit 16: SD I/O suspend command */
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#define STM32_SDMMC_CMD_RESET (0) /* Reset value */
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#define STM32_SDMMC_RESPCMD_SHIFT (0)
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#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT)
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#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */
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#define STM32_SDMMC_DLEN_SHIFT (0)
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#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT)
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#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */
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#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */
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#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */
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#define STM32_SDMMC_DCTRL_DTMODE_SHIFT (2) /* Bits 2-3: Data transfer mode */
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#define STM32_SDMMC_DCTRL_DTMODE_MASK (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
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# define STM32_SDMMC_DCTRL_DTMODE_END (0 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
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# define STM32_SDMMC_DCTRL_DTMODE_SDIO (1 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
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# define STM32_SDMMC_DCTRL_DTMODE_EMMC (2 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
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# define STM32_SDMMC_DCTRL_DTMODE_BLOCK (3 << STM32_SDMMC_DCTRL_DTMODE_SHIFT)
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#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */
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#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (0xf << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
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#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */
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#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */
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#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */
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#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */
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#define STM32_SDMMC_DCTRL_BOOTACKEN (1 << 12) /* Bit 12: Enable reception of boot ack */
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#define STM32_SDMMC_DCTRL_FIFORST (1 << 13) /* Bit 13: FIFO reset */
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#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */
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#define STM32_SDMMC_DCOUNT_SHIFT (0)
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#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT)
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#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */
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#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */
|
||||
#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */
|
||||
#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */
|
||||
#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */
|
||||
#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */
|
||||
#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */
|
||||
#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */
|
||||
#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */
|
||||
#define STM32_SDMMC_STA_DHOLD (1 << 9) /* Bit 9: Data transfer hold */
|
||||
#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */
|
||||
#define STM32_SDMMC_STA_DABORT (1 << 11) /* Bit 11: Data transfer aborted by CMD12 */
|
||||
#define STM32_SDMMC_STA_DPSMACT (1 << 12) /* Bit 12: Data path state machine active */
|
||||
#define STM32_SDMMC_STA_CPSMACT (1 << 13) /* Bit 13: Command path state machine active */
|
||||
#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */
|
||||
#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */
|
||||
#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */
|
||||
#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */
|
||||
#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */
|
||||
#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */
|
||||
#define STM32_SDMMC_STA_BUSYD0 (1 << 20) /* Bit 20: Card signals busy on SDMMC_D0 */
|
||||
#define STM32_SDMMC_STA_BUSYD0END (1 << 21) /* Bit 21: card SDMMC_D0 signal changed from busy to NOT busy */
|
||||
#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */
|
||||
#define STM32_SDMMC_STA_ACKFAIL (1 << 23) /* Bit 23: Boot ack check fail */
|
||||
#define STM32_SDMMC_STA_ACKTIMEOUT (1 << 24) /* Bit 24: Boot ack timeout */
|
||||
#define STM32_SDMMC_STA_VSWEND (1 << 25) /* Bit 25: Voltage switch critical timing section completion */
|
||||
#define STM32_SDMMC_STA_CKSTOP (1 << 26) /* Bit 26: SDMMC_CK stopped in Voltage switch procedure */
|
||||
#define STM32_SDMMC_STA_IDMATE (1 << 27) /* Bit 27: IDMA transfer error */
|
||||
#define STM32_SDMMC_STA_IDMABTC (1 << 28) /* Bit 28: IDMA buffer transfer complete */
|
||||
|
||||
#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */
|
||||
#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DHOLDC (1 << 9) /* Bit 9: DHOLD flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_DABORTC (1 << 11) /* Bit 11: DABORT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_BUSYD0ENDC (1 << 21) /* Bit 21: BUSYD0END flag clear bit */
|
||||
#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_ACKFAILC (1 << 23) /* Bit 23: ACKFAIL flag clear bit */
|
||||
#define STM32_SDMMC_ICR_ACKTIMEOUTC (1 << 24) /* Bit 24: ACKTIMEOUT flag clear bit */
|
||||
#define STM32_SDMMC_ICR_VSWENDC (1 << 25) /* Bit 25: VSWEND flag clear bit */
|
||||
#define STM32_SDMMC_ICR_CKSTOPC (1 << 26) /* Bit 26: CKSTOP flag clear bit */
|
||||
#define STM32_SDMMC_ICR_IDMATEC (1 << 27) /* Bit 27: IDMA transfer error clear bit */
|
||||
#define STM32_SDMMC_ICR_IDMABTCC (1 << 28) /* Bit 28: IDMA buffer transfer complete clear bit */
|
||||
|
||||
#define STM32_SDMMC_ICR_RESET 0x00000000
|
||||
#define STM32_SDMMC_ICR_ALLFLAGS 0x1fe00fff
|
||||
|
||||
#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DHOLDIE (1 << 9) /* Bit 9: Data hold interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */
|
||||
#define STM32_SDMMC_MASK_DABOTRTIE (1 << 11) /* Bit 11: Data transfer aborted interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
|
||||
#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
|
||||
#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 18) /* Bit 18: Tx FIFO full interrupt enable */
|
||||
#define STM32_SDMMC_MASK_BUSYD0ENDIE (1 << 21) /* Bit 21: BUSYD0END interrupt enable */
|
||||
#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
|
||||
#define STM32_SDMMC_MASK_ACKFAILIE (1 << 23) /* Bit 23: Acknowledgment Fail interrupt enable */
|
||||
#define STM32_SDMMC_MASK_ACKTIMEOUTIE (1 << 24) /* Bit 24: Acknowledgment timeout interrupt enable */
|
||||
#define STM32_SDMMC_MASK_VSWENDIE (1 << 25) /* Bit 25: Voltage switch critical timing section completion interrupt enable */
|
||||
#define STM32_SDMMC_MASK_CKSTOPIE (1 << 26) /* Bit 26: Voltage Switch clock stopped interrupt enable */
|
||||
#define STM32_SDMMC_MASK_IDMABTCIE (1 << 28) /* Bit 28: IDMA buffer transfer complete interrupt enable */
|
||||
|
||||
#define STM32_SDMMC_MASK_RESET (0)
|
||||
|
||||
#define STM32_SDMMC_IDMACTRLR_IDMAEN (1 << 0)
|
||||
|
||||
#define STM32_SDMMC_FIFOCNT_SHIFT (0)
|
||||
#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32H7X3XX_SDMMC_H */
|
||||
2995
arch/arm/src/stm32h7/stm32_sdmmc.c
Normal file
2995
arch/arm/src/stm32h7/stm32_sdmmc.c
Normal file
File diff suppressed because it is too large
Load Diff
128
arch/arm/src/stm32h7/stm32_sdmmc.h
Normal file
128
arch/arm/src/stm32h7/stm32_sdmmc.h
Normal file
@ -0,0 +1,128 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_sdmmc.h
|
||||
*
|
||||
* Copyright (C) 2009, 2011, 2016, 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_SDMMC_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32_SDMMC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_sdmmc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on
|
||||
* failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct sdio_dev_s; /* See include/nuttx/sdio.h */
|
||||
FAR struct sdio_dev_s *sdio_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- posssible from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* cardinslot - true is a card has been detected in the slot; false if a
|
||||
* card has been removed from the slot. Only transitions
|
||||
* (inserted->removed or removed->inserted should be reported)
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_SDMMC_H */
|
||||
@ -220,6 +220,12 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_MDMAEN;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H7_SDMMC1
|
||||
/* SDMMC clock enable */
|
||||
|
||||
regval |= RCC_AHB3ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
@ -396,7 +402,11 @@ static inline void rcc_enableapb2(void)
|
||||
regval |= RCC_APB2ENR_SPI5EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
#ifdef CONFIG_STM32H7_SDMMC2
|
||||
/* SDMMC2 clock enable */
|
||||
|
||||
regval |= RCC_APB2ENR_SDMMC2EN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user