sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

WM8904: Tried disabling the SYSCLK while updating the FLL. Didn't help but is still probably a correct change

Browse Source
This commit is contained in:
Gregory Nutt 2014-08-03 18:44:51 -06:00
parent 72b739fbcb
commit 678c0aac8d
2 changed files with 24 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/audio/wm8904.c
View File

@ -629,6 +629,15 @@ static void wm8904_setbitrate(FAR struct wm8904_dev_s *priv)
audvdbg("sample rate=%u nchannels=%u bpsamp=%u fout=%lu\n",
priv->samprate, priv->nchannels, priv->bpsamp, (unsigned long)fout);
/* Disable the SYSCLK.
*
* "The SYSCLK signal is enabled by register bit CLK_SYS_ENA. This bit should be
* set to 0 when reconfiguring clock sources. ... "
*/
regval = WM8904_SYSCLK_SRCFLL | WM8904_CLK_DSP_ENA;
wm8904_writereg(priv, WM8904_CLKRATE2, regval);
/* "The FLL is enabled using the FLL_ENA register bit. Note that, when
* changing FLL settings, it is recommended that the digital circuit be
* disabled via FLL_ENA and then re-enabled after the other register
@ -781,7 +790,8 @@ static void wm8904_setbitrate(FAR struct wm8904_dev_s *priv)
* FLL_OSC_EN=0 : FLL internal oscillator disabled
* FLL_ENA=0 : The FLL is not enabled
*
* "FLL_OSC_ENA must be enabled before enabling FLL_ENA."
* FLL_OSC_ENA must be enabled before enabling FLL_ENA (FLL_OSC_ENA is
* only required for free-running modes).
*/
wm8904_writereg(priv, WM8904_FLL_CTRL1, 0);
@ -825,16 +835,22 @@ static void wm8904_setbitrate(FAR struct wm8904_dev_s *priv)
* Already set above
*/
/* Allow time for FLL lock. Typical is 2 MSec. Lock status is available
* in the WM8904 interrupt status register.
*/
usleep(5*5000);
/* Enable the FLL */
regval = WM8904_FLL_FRACN_ENA | WM8904_FLL_ENA;
wm8904_writereg(priv, WM8904_FLL_CTRL1, regval);
/* Allow time for FLL lock. Typical is 2 MSec. Lock status is available
* in the WM8904 interrupt status register.
* REVISIT: Probably not necessary.
*/
usleep(5*5000);
/* Re-enable the SYSCLK. */
regval = WM8904_SYSCLK_SRCFLL | WM8904_CLK_SYS_ENA | WM8904_CLK_DSP_ENA;
wm8904_writereg(priv, WM8904_CLKRATE2, regval);
}
/****************************************************************************

2
drivers/audio/wm8904_debug.c
View File

@ -426,7 +426,7 @@ void wm8904_clock_analysis(FAR struct audio_lowerhalf_s *dev,
lrclk = bclk / tmp;
syslog(" LRCLK_RATE: BCLK / %lu\n", (unsigned long)tmp);
syslog(" LRCLK: %lu\n", (unsigned long)lrclk);
syslog(" LRCLK: %lu Hz\n", (unsigned long)lrclk);
syslog(" LRCLK_DIR: %s\n",
(regval & WM8904_LRCLK_DIR) != 0 ? "Output" : "Input");
}