diff --git a/arch/arm/src/armv7-m/gnu/up_exception.S b/arch/arm/src/armv7-m/gnu/up_exception.S
index 1629dc99bb..ddf04afc7c 100644
--- a/arch/arm/src/armv7-m/gnu/up_exception.S
+++ b/arch/arm/src/armv7-m/gnu/up_exception.S
@@ -188,6 +188,12 @@ exception_common:
 #else
 	/* Set the BASEPRI register so that further normal interrupts will be
 	 * masked.  Nested, high priority may still occur, however.
+	 *
+	 * REVISIT:  I think this is un-necessary:  "When the processor is
+	 * executing an exception handler, an exception can preempt the exception
+	 * handler if its priority is higher than the priority of the exception
+	 * being handled. See Interrupt priority grouping for more information
+	 * about preemption by an interrupt."
 	 */
 
 	mov		r2, #NVIC_SYSH_DISABLE_PRIORITY
diff --git a/arch/arm/src/armv7-m/gnu/up_lazyexception.S b/arch/arm/src/armv7-m/gnu/up_lazyexception.S
index 54625cffde..a47a0137e6 100644
--- a/arch/arm/src/armv7-m/gnu/up_lazyexception.S
+++ b/arch/arm/src/armv7-m/gnu/up_lazyexception.S
@@ -160,6 +160,7 @@ exception_common:
 
 	mov		r2, sp					/* R2=Copy of the main/process stack pointer */
 	add		r2, #HW_XCPT_SIZE		/* R2=MSP/PSP before the interrupt was taken */
+
 #ifdef CONFIG_ARMV7M_USEBASEPRI
 	mrs		r3, basepri				/* R3=Current BASEPRI setting */
 #else
@@ -197,6 +198,12 @@ exception_common:
 #else
 	/* Set the BASEPRI register so that further normal interrupts will be
 	 * masked.  Nested, high priority may still occur, however.
+	 *
+	 * REVISIT:  I think this is un-necessary:  "When the processor is
+	 * executing an exception handler, an exception can preempt the exception
+	 * handler if its priority is higher than the priority of the exception
+	 * being handled. See Interrupt priority grouping for more information
+	 * about preemption by an interrupt."
 	 */
 
 	mov		r2, #NVIC_SYSH_DISABLE_PRIORITY