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Update some comments.

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This commit is contained in:
Gregory Nutt 2018-08-03 16:20:42 -06:00
parent 9b7e5ede0a
commit 679d2875f2
2 changed files with 13 additions and 0 deletions
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6
arch/arm/src/armv7-m/gnu/up_exception.S
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@ -188,6 +188,12 @@ exception_common:
#else #else
/* Set the BASEPRI register so that further normal interrupts will be /* Set the BASEPRI register so that further normal interrupts will be
* masked. Nested, high priority may still occur, however. * masked. Nested, high priority may still occur, however.
*
* REVISIT: I think this is un-necessary: "When the processor is
* executing an exception handler, an exception can preempt the exception
* handler if its priority is higher than the priority of the exception
* being handled. See Interrupt priority grouping for more information
* about preemption by an interrupt."
*/ */
mov r2, #NVIC_SYSH_DISABLE_PRIORITY mov r2, #NVIC_SYSH_DISABLE_PRIORITY

7
arch/arm/src/armv7-m/gnu/up_lazyexception.S
View File

@ -160,6 +160,7 @@ exception_common:
mov r2, sp /* R2=Copy of the main/process stack pointer */ mov r2, sp /* R2=Copy of the main/process stack pointer */
add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */
#ifdef CONFIG_ARMV7M_USEBASEPRI #ifdef CONFIG_ARMV7M_USEBASEPRI
mrs r3, basepri /* R3=Current BASEPRI setting */ mrs r3, basepri /* R3=Current BASEPRI setting */
#else #else
@ -197,6 +198,12 @@ exception_common:
#else #else
/* Set the BASEPRI register so that further normal interrupts will be /* Set the BASEPRI register so that further normal interrupts will be
* masked. Nested, high priority may still occur, however. * masked. Nested, high priority may still occur, however.
*
* REVISIT: I think this is un-necessary: "When the processor is
* executing an exception handler, an exception can preempt the exception
* handler if its priority is higher than the priority of the exception
* being handled. See Interrupt priority grouping for more information
* about preemption by an interrupt."
*/ */
mov r2, #NVIC_SYSH_DISABLE_PRIORITY mov r2, #NVIC_SYSH_DISABLE_PRIORITY