style fixes
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@ -1460,32 +1460,32 @@ static void stm32l4_i2c_setclock(FAR struct stm32l4_i2c_priv_s *priv,
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}
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}
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else if (i2cclk_mhz == 48)
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{
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if (frequency == 100000)
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{
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presc = 2;
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scl_delay = 10;
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sda_delay = 0;
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scl_h_period = 62;
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scl_l_period = 85;
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}
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else if (frequency == 400000)
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{
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presc = 1;
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scl_delay = 8;
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sda_delay = 0;
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scl_h_period = 12;
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scl_l_period = 33;
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}
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else if (frequency == 1000000)
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{
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presc = 0;
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scl_delay = 5;
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sda_delay = 0;
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scl_h_period = 8;
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scl_l_period = 22;
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}
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}
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{
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if (frequency == 100000)
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{
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presc = 2;
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scl_delay = 10;
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sda_delay = 0;
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scl_h_period = 62;
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scl_l_period = 85;
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}
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else if (frequency == 400000)
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{
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presc = 1;
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scl_delay = 8;
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sda_delay = 0;
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scl_h_period = 12;
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scl_l_period = 33;
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}
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else if (frequency == 1000000)
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{
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presc = 0;
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scl_delay = 5;
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sda_delay = 0;
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scl_h_period = 8;
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scl_l_period = 22;
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}
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}
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else
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{
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DEBUGPANIC();
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@ -731,26 +731,26 @@ static void stm32l4_stdclockconfig(void)
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putreg32(regval, STM32L4_RCC_CR);
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if (!(regval & RCC_CR_MSION))
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{
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/* Enable MSI */
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{
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/* Enable MSI */
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regval = getreg32(STM32L4_RCC_CR);
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regval |= RCC_CR_MSION;
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putreg32(regval, STM32L4_RCC_CR);
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regval = getreg32(STM32L4_RCC_CR);
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regval |= RCC_CR_MSION;
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putreg32(regval, STM32L4_RCC_CR);
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/* Wait until the MSI is ready (or until a timeout elapsed) */
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/* Wait until the MSI is ready (or until a timeout elapsed) */
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for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the MSIRDY flag is the set in the CR */
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for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the MSIRDY flag is the set in the CR */
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if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
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{
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/* If so, then break-out with timeout > 0 */
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if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0)
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{
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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break;
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}
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}
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}
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#elif defined(STM32L4_BOARD_USEHSE)
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@ -797,7 +797,7 @@ static void stm32l4_stdclockconfig(void)
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stm32l4_pwr_enableclk(true);
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stm32_pwr_setvos(1);
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#endif
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}
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}
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else
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{
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/* Select regulator voltage output Scale 2 mode for
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