Tiva: Update I2C register definitions to include support for the TM4C129X
This commit is contained in:
Gregory Nutt
parent
c4f64c72c8
commit
67aeab7105
@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/tiva/chip/tiva_i2c.h
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2013-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -60,13 +60,12 @@
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#define TIVA_I2CM_ICR_OFFSET 0x001c /* I2C Master Interrupt Clear */
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#define TIVA_I2CM_CR_OFFSET 0x0020 /* I2C Master Configuration */
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM_CLKOCNT_OFFSET 0x0024 /* I2C Master Clock Low Timeout Count */
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# define TIVA_I2CM_BMON_OFFSET 0x002c /* I2C Master Configuration */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM_BLEN_OFFSET 0x0030 /* I2C Master Burst Length */
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# define TIVA_I2CM_BCNT_OFFSET 0x0034 /* I2C Master Burst Count */
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#endif
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@ -85,22 +84,20 @@
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#define TIVA_I2CS_MIS_OFFSET 0x0814 /* I2C Slave Masked Interrupt Status */
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#define TIVA_I2CS_ICR_OFFSET 0x0818 /* I2C Slave Interrupt Clear */
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS_SOAR2_OFFSET 0x081c /* I2C Slave Own Address 2 */
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# define TIVA_I2CS_ACKCTL_OFFSET 0x0820 /* I2C Slave ACK Control */
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#endif
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/* I2C Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CSC_FIFODATA_OFFSET 0x0f00 /* I2C FIFO Data */
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# define TIVA_I2CSC_FIFOCTL_OFFSET 0x0f04 /* I2C FIFO Control */
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# define TIVA_I2CSC_FIFOSTATUS_OFFSET 0x0f08 /* I2C FIFO Status */
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CSC_PP_OFFSET 0x0fc0 /* I2C Peripheral Properties */
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# define TIVA_I2CSC_PC_OFFSET 0x0fc4 /* I2C Peripheral Configuration */
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#endif
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@ -121,13 +118,12 @@
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#define TIVA_I2CM0_ICR (TIVA_I2C0_BASE + TIVA_I2CM_ICR_OFFSET)
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#define TIVA_I2CM0_CR (TIVA_I2C0_BASE + TIVA_I2CM_CR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM0_CLKOCNT (TIVA_I2C0_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
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# define TIVA_I2CM0_BMON (TIVA_I2C0_BASE + TIVA_I2CM_BMON_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM0_BLEN (TIVA_I2C0_BASE + TIVA_I2CM_BLEN_OFFSET)
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# define TIVA_I2CM0_BCNT (TIVA_I2C0_BASE + TIVA_I2CM_BCNT_OFFSET)
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#endif
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@ -146,22 +142,20 @@
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#define TIVA_I2CS0_MIS (TIVA_I2C0_BASE + TIVA_I2CS_MIS_OFFSET)
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#define TIVA_I2CS0_ICR (TIVA_I2C0_BASE + TIVA_I2CS_ICR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS0_SOAR2 (TIVA_I2C0_BASE + TIVA_I2CS_SOAR2_OFFSET)
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# define TIVA_I2CS0_ACKCTL (TIVA_I2C0_BASE + TIVA_I2CS_ACKCTL_OFFSET)
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#endif
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/* I2C0 Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CSC0_FIFODATA (TIVA_I2C0_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
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# define TIVA_I2CSC0_FIFOCTL (TIVA_I2C0_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
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# define TIVA_I2CSC0_FIFOSTATUS (TIVA_I2C0_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CSC0_PP (TIVA_I2C0_BASE + TIVA_I2CSC_PP_OFFSET)
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# define TIVA_I2CSC0_PC (TIVA_I2C0_BASE + TIVA_I2CSC_PC_OFFSET)
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#endif
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@ -181,13 +175,12 @@
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#define TIVA_I2CM1_ICR (TIVA_I2C1_BASE + TIVA_I2CM_ICR_OFFSET)
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#define TIVA_I2CM1_CR (TIVA_I2C1_BASE + TIVA_I2CM_CR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM1_CLKOCNT (TIVA_I2C1_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
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# define TIVA_I2CM1_BMON (TIVA_I2C1_BASE + TIVA_I2CM_BMON_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM1_BLEN (TIVA_I2C1_BASE + TIVA_I2CM_BLEN_OFFSET)
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# define TIVA_I2CM1_BCNT (TIVA_I2C1_BASE + TIVA_I2CM_BCNT_OFFSET)
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#endif
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@ -206,22 +199,20 @@
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#define TIVA_I2CS1_MIS (TIVA_I2C1_BASE + TIVA_I2CS_MIS_OFFSET)
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#define TIVA_I2CS1_ICR (TIVA_I2C1_BASE + TIVA_I2CS_ICR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS1_SOAR2 (TIVA_I2C1_BASE + TIVA_I2CS_SOAR2_OFFSET)
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# define TIVA_I2CS1_ACKCTL (TIVA_I2C1_BASE + TIVA_I2CS_ACKCTL_OFFSET)
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#endif
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/* I2C1 Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CSC1_FIFODATA (TIVA_I2C1_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
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# define TIVA_I2CSC1_FIFOCTL (TIVA_I2C1_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
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# define TIVA_I2CSC1_FIFOSTATUS (TIVA_I2C1_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CSC1_PP (TIVA_I2C1_BASE + TIVA_I2CSC_PP_OFFSET)
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# define TIVA_I2CSC1_PC (TIVA_I2C1_BASE + TIVA_I2CSC_PC_OFFSET)
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#endif
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@ -241,13 +232,12 @@
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#define TIVA_I2CM2_ICR (TIVA_I2C2_BASE + TIVA_I2CM_ICR_OFFSET)
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#define TIVA_I2CM2_CR (TIVA_I2C2_BASE + TIVA_I2CM_CR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM2_CLKOCNT (TIVA_I2C2_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
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# define TIVA_I2CM2_BMON (TIVA_I2C2_BASE + TIVA_I2CM_BMON_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM2_BLEN (TIVA_I2C2_BASE + TIVA_I2CM_BLEN_OFFSET)
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# define TIVA_I2CM2_BCNT (TIVA_I2C2_BASE + TIVA_I2CM_BCNT_OFFSET)
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#endif
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@ -266,22 +256,20 @@
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#define TIVA_I2CS2_MIS (TIVA_I2C2_BASE + TIVA_I2CS_MIS_OFFSET)
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#define TIVA_I2CS2_ICR (TIVA_I2C2_BASE + TIVA_I2CS_ICR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS2_SOAR2 (TIVA_I2C2_BASE + TIVA_I2CS_SOAR2_OFFSET)
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# define TIVA_I2CS2_ACKCTL (TIVA_I2C2_BASE + TIVA_I2CS_ACKCTL_OFFSET)
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#endif
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/* I2C2 Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CSC2_FIFODATA (TIVA_I2C2_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
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# define TIVA_I2CSC2_FIFOCTL (TIVA_I2C2_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
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# define TIVA_I2CSC2_FIFOSTATUS (TIVA_I2C2_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CSC2_PP (TIVA_I2C2_BASE + TIVA_I2CSC_PP_OFFSET)
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# define TIVA_I2CSC2_PC (TIVA_I2C2_BASE + TIVA_I2CSC_PC_OFFSET)
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#endif
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@ -301,13 +289,12 @@
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#define TIVA_I2CM3_ICR (TIVA_I2C3_BASE + TIVA_I2CM_ICR_OFFSET)
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#define TIVA_I2CM3_CR (TIVA_I2C3_BASE + TIVA_I2CM_CR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM3_CLKOCNT (TIVA_I2C3_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
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# define TIVA_I2CM3_BMON (TIVA_I2C3_BASE + TIVA_I2CM_BMON_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM3_BLEN (TIVA_I2C3_BASE + TIVA_I2CM_BLEN_OFFSET)
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# define TIVA_I2CM3_BCNT (TIVA_I2C3_BASE + TIVA_I2CM_BCNT_OFFSET)
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#endif
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@ -326,22 +313,20 @@
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#define TIVA_I2CS3_MIS (TIVA_I2C3_BASE + TIVA_I2CS_MIS_OFFSET)
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#define TIVA_I2CS3_ICR (TIVA_I2C3_BASE + TIVA_I2CS_ICR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS3_SOAR2 (TIVA_I2C3_BASE + TIVA_I2CS_SOAR2_OFFSET)
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# define TIVA_I2CS3_ACKCTL (TIVA_I2C3_BASE + TIVA_I2CS_ACKCTL_OFFSET)
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#endif
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/* I2C3 Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CSC3_FIFODATA (TIVA_I2C3_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
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# define TIVA_I2CSC3_FIFOCTL (TIVA_I2C3_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
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# define TIVA_I2CSC3_FIFOSTATUS (TIVA_I2C3_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CSC3_PP (TIVA_I2C3_BASE + TIVA_I2CSC_PP_OFFSET)
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# define TIVA_I2CSC3_PC (TIVA_I2C3_BASE + TIVA_I2CSC_PC_OFFSET)
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#endif
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@ -361,13 +346,12 @@
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#define TIVA_I2CM4_ICR (TIVA_I2C4_BASE + TIVA_I2CM_ICR_OFFSET)
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#define TIVA_I2CM4_CR (TIVA_I2C4_BASE + TIVA_I2CM_CR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM4_CLKOCNT (TIVA_I2C4_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
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# define TIVA_I2CM4_BMON (TIVA_I2C4_BASE + TIVA_I2CM_BMON_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM4_BLEN (TIVA_I2C4_BASE + TIVA_I2CM_BLEN_OFFSET)
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# define TIVA_I2CM4_BCNT (TIVA_I2C4_BASE + TIVA_I2CM_BCNT_OFFSET)
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#endif
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@ -386,22 +370,20 @@
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#define TIVA_I2CS4_MIS (TIVA_I2C4_BASE + TIVA_I2CS_MIS_OFFSET)
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#define TIVA_I2CS4_ICR (TIVA_I2C4_BASE + TIVA_I2CS_ICR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS4_SOAR2 (TIVA_I2C4_BASE + TIVA_I2CS_SOAR2_OFFSET)
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# define TIVA_I2CS4_ACKCTL (TIVA_I2C4_BASE + TIVA_I2CS_ACKCTL_OFFSET)
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#endif
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/* I2C4 Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CSC4_FIFODATA (TIVA_I2C4_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
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# define TIVA_I2CSC4_FIFOCTL (TIVA_I2C4_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
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# define TIVA_I2CSC4_FIFOSTATUS (TIVA_I2C4_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CSC4_PP (TIVA_I2C4_BASE + TIVA_I2CSC_PP_OFFSET)
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# define TIVA_I2CSC4_PC (TIVA_I2C4_BASE + TIVA_I2CSC_PC_OFFSET)
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#endif
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@ -421,13 +403,12 @@
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#define TIVA_I2CM5_ICR (TIVA_I2C5_BASE + TIVA_I2CM_ICR_OFFSET)
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#define TIVA_I2CM5_CR (TIVA_I2C5_BASE + TIVA_I2CM_CR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CM5_CLKOCNT (TIVA_I2C5_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
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# define TIVA_I2CM5_BMON (TIVA_I2C5_BASE + TIVA_I2CM_BMON_OFFSET)
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#endif
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C129)
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# define TIVA_I2CM5_BLEN (TIVA_I2C5_BASE + TIVA_I2CM_BLEN_OFFSET)
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# define TIVA_I2CM5_BCNT (TIVA_I2C5_BASE + TIVA_I2CM_BCNT_OFFSET)
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#endif
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@ -446,27 +427,253 @@
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#define TIVA_I2CS5_MIS (TIVA_I2C5_BASE + TIVA_I2CS_MIS_OFFSET)
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#define TIVA_I2CS5_ICR (TIVA_I2C5_BASE + TIVA_I2CS_ICR_OFFSET)
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#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
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defined(CONFIG_ARCH_CHIP_TM4C1294NC)
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#if defined(CONFIG_ARCH_CHIP_TM4C)
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# define TIVA_I2CS5_SOAR2 (TIVA_I2C5_BASE + TIVA_I2CS_SOAR2_OFFSET)
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# define TIVA_I2CS5_ACKCTL (TIVA_I2C5_BASE + TIVA_I2CS_ACKCTL_OFFSET)
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#endif
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/* I2C Status and control */
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#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CSC5_FIFODATA (TIVA_I2C5_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
|
||||
# define TIVA_I2CSC5_FIFOCTL (TIVA_I2C5_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
|
||||
# define TIVA_I2CSC5_FIFOSTATUS (TIVA_I2C5_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CSC5_PP (TIVA_I2C5_BASE + TIVA_I2CSC_PP_OFFSET)
|
||||
# define TIVA_I2CSC5_PC (TIVA_I2C5_BASE + TIVA_I2CSC_PC_OFFSET)
|
||||
#endif
|
||||
#endif /* TIVA_NI2C > 5 */
|
||||
|
||||
#if TIVA_NI2C > 6
|
||||
|
||||
/* I2C6 Master */
|
||||
|
||||
#define TIVA_I2CM6_SA (TIVA_I2C6_BASE + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM6_CS (TIVA_I2C6_BASE + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM6_DR (TIVA_I2C6_BASE + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM6_TPR (TIVA_I2C6_BASE + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM6_IMR (TIVA_I2C6_BASE + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM6_RIS (TIVA_I2C6_BASE + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM6_MIS (TIVA_I2C6_BASE + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM6_ICR (TIVA_I2C6_BASE + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM6_CR (TIVA_I2C6_BASE + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CM6_CLKOCNT (TIVA_I2C6_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
|
||||
# define TIVA_I2CM6_BMON (TIVA_I2C6_BASE + TIVA_I2CM_BMON_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CM6_BLEN (TIVA_I2C6_BASE + TIVA_I2CM_BLEN_OFFSET)
|
||||
# define TIVA_I2CM6_BCNT (TIVA_I2C6_BASE + TIVA_I2CM_BCNT_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
|
||||
# define TIVA_I2CM6_CR2 (TIVA_I2C6_BASE + TIVA_I2CM_CR2_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C6 Slave */
|
||||
|
||||
#define TIVA_I2CS6_OAR (TIVA_I2C6_BASE + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS6_CSR (TIVA_I2C6_BASE + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS6_DR (TIVA_I2C6_BASE + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS6_IMR (TIVA_I2C6_BASE + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS6_RIS (TIVA_I2C6_BASE + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS6_MIS (TIVA_I2C6_BASE + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS6_ICR (TIVA_I2C6_BASE + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CS6_SOAR2 (TIVA_I2C6_BASE + TIVA_I2CS_SOAR2_OFFSET)
|
||||
# define TIVA_I2CS6_ACKCTL (TIVA_I2C6_BASE + TIVA_I2CS_ACKCTL_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C Status and control */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CSC6_FIFODATA (TIVA_I2C6_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
|
||||
# define TIVA_I2CSC6_FIFOCTL (TIVA_I2C6_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
|
||||
# define TIVA_I2CSC6_FIFOSTATUS (TIVA_I2C6_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CSC6_PP (TIVA_I2C6_BASE + TIVA_I2CSC_PP_OFFSET)
|
||||
# define TIVA_I2CSC6_PC (TIVA_I2C6_BASE + TIVA_I2CSC_PC_OFFSET)
|
||||
#endif
|
||||
#endif /* TIVA_NI2C > 5 */
|
||||
|
||||
#if TIVA_NI2C > 7
|
||||
|
||||
/* I2C7 Master */
|
||||
|
||||
#define TIVA_I2CM7_SA (TIVA_I2C7_BASE + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM7_CS (TIVA_I2C7_BASE + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM7_DR (TIVA_I2C7_BASE + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM7_TPR (TIVA_I2C7_BASE + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM7_IMR (TIVA_I2C7_BASE + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM7_RIS (TIVA_I2C7_BASE + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM7_MIS (TIVA_I2C7_BASE + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM7_ICR (TIVA_I2C7_BASE + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM7_CR (TIVA_I2C7_BASE + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CM7_CLKOCNT (TIVA_I2C7_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
|
||||
# define TIVA_I2CM7_BMON (TIVA_I2C7_BASE + TIVA_I2CM_BMON_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CM7_BLEN (TIVA_I2C7_BASE + TIVA_I2CM_BLEN_OFFSET)
|
||||
# define TIVA_I2CM7_BCNT (TIVA_I2C7_BASE + TIVA_I2CM_BCNT_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
|
||||
# define TIVA_I2CM7_CR2 (TIVA_I2C7_BASE + TIVA_I2CM_CR2_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C7 Slave */
|
||||
|
||||
#define TIVA_I2CS7_OAR (TIVA_I2C7_BASE + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS7_CSR (TIVA_I2C7_BASE + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS7_DR (TIVA_I2C7_BASE + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS7_IMR (TIVA_I2C7_BASE + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS7_RIS (TIVA_I2C7_BASE + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS7_MIS (TIVA_I2C7_BASE + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS7_ICR (TIVA_I2C7_BASE + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CS7_SOAR2 (TIVA_I2C7_BASE + TIVA_I2CS_SOAR2_OFFSET)
|
||||
# define TIVA_I2CS7_ACKCTL (TIVA_I2C7_BASE + TIVA_I2CS_ACKCTL_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C Status and control */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CSC7_FIFODATA (TIVA_I2C7_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
|
||||
# define TIVA_I2CSC7_FIFOCTL (TIVA_I2C7_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
|
||||
# define TIVA_I2CSC7_FIFOSTATUS (TIVA_I2C7_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CSC7_PP (TIVA_I2C7_BASE + TIVA_I2CSC_PP_OFFSET)
|
||||
# define TIVA_I2CSC7_PC (TIVA_I2C7_BASE + TIVA_I2CSC_PC_OFFSET)
|
||||
#endif
|
||||
#endif /* TIVA_NI2C > 5 */
|
||||
|
||||
#if TIVA_NI2C > 8
|
||||
|
||||
/* I2C8 Master */
|
||||
|
||||
#define TIVA_I2CM8_SA (TIVA_I2C8_BASE + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM8_CS (TIVA_I2C8_BASE + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM8_DR (TIVA_I2C8_BASE + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM8_TPR (TIVA_I2C8_BASE + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM8_IMR (TIVA_I2C8_BASE + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM8_RIS (TIVA_I2C8_BASE + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM8_MIS (TIVA_I2C8_BASE + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM8_ICR (TIVA_I2C8_BASE + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM8_CR (TIVA_I2C8_BASE + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CM8_CLKOCNT (TIVA_I2C8_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
|
||||
# define TIVA_I2CM8_BMON (TIVA_I2C8_BASE + TIVA_I2CM_BMON_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CM8_BLEN (TIVA_I2C8_BASE + TIVA_I2CM_BLEN_OFFSET)
|
||||
# define TIVA_I2CM8_BCNT (TIVA_I2C8_BASE + TIVA_I2CM_BCNT_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
|
||||
# define TIVA_I2CM8_CR2 (TIVA_I2C8_BASE + TIVA_I2CM_CR2_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C8 Slave */
|
||||
|
||||
#define TIVA_I2CS8_OAR (TIVA_I2C8_BASE + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS8_CSR (TIVA_I2C8_BASE + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS8_DR (TIVA_I2C8_BASE + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS8_IMR (TIVA_I2C8_BASE + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS8_RIS (TIVA_I2C8_BASE + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS8_MIS (TIVA_I2C8_BASE + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS8_ICR (TIVA_I2C8_BASE + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CS8_SOAR2 (TIVA_I2C8_BASE + TIVA_I2CS_SOAR2_OFFSET)
|
||||
# define TIVA_I2CS8_ACKCTL (TIVA_I2C8_BASE + TIVA_I2CS_ACKCTL_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C Status and control */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CSC8_FIFODATA (TIVA_I2C8_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
|
||||
# define TIVA_I2CSC8_FIFOCTL (TIVA_I2C8_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
|
||||
# define TIVA_I2CSC8_FIFOSTATUS (TIVA_I2C8_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CSC8_PP (TIVA_I2C8_BASE + TIVA_I2CSC_PP_OFFSET)
|
||||
# define TIVA_I2CSC8_PC (TIVA_I2C8_BASE + TIVA_I2CSC_PC_OFFSET)
|
||||
#endif
|
||||
#endif /* TIVA_NI2C > 5 */
|
||||
|
||||
#if TIVA_NI2C > 9
|
||||
|
||||
/* I2C9 Master */
|
||||
|
||||
#define TIVA_I2CM9_SA (TIVA_I2C9_BASE + TIVA_I2CM_SA_OFFSET)
|
||||
#define TIVA_I2CM9_CS (TIVA_I2C9_BASE + TIVA_I2CM_CS_OFFSET)
|
||||
#define TIVA_I2CM9_DR (TIVA_I2C9_BASE + TIVA_I2CM_DR_OFFSET)
|
||||
#define TIVA_I2CM9_TPR (TIVA_I2C9_BASE + TIVA_I2CM_TPR_OFFSET)
|
||||
#define TIVA_I2CM9_IMR (TIVA_I2C9_BASE + TIVA_I2CM_IMR_OFFSET)
|
||||
#define TIVA_I2CM9_RIS (TIVA_I2C9_BASE + TIVA_I2CM_RIS_OFFSET)
|
||||
#define TIVA_I2CM9_MIS (TIVA_I2C9_BASE + TIVA_I2CM_MIS_OFFSET)
|
||||
#define TIVA_I2CM9_ICR (TIVA_I2C9_BASE + TIVA_I2CM_ICR_OFFSET)
|
||||
#define TIVA_I2CM9_CR (TIVA_I2C9_BASE + TIVA_I2CM_CR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CM9_CLKOCNT (TIVA_I2C9_BASE + TIVA_I2CM_CLKOCNT_OFFSET)
|
||||
# define TIVA_I2CM9_BMON (TIVA_I2C9_BASE + TIVA_I2CM_BMON_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CM9_BLEN (TIVA_I2C9_BASE + TIVA_I2CM_BLEN_OFFSET)
|
||||
# define TIVA_I2CM9_BCNT (TIVA_I2C9_BASE + TIVA_I2CM_BCNT_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB)
|
||||
# define TIVA_I2CM9_CR2 (TIVA_I2C9_BASE + TIVA_I2CM_CR2_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C9 Slave */
|
||||
|
||||
#define TIVA_I2CS9_OAR (TIVA_I2C9_BASE + TIVA_I2CS_OAR_OFFSET)
|
||||
#define TIVA_I2CS9_CSR (TIVA_I2C9_BASE + TIVA_I2CS_CSR_OFFSET)
|
||||
#define TIVA_I2CS9_DR (TIVA_I2C9_BASE + TIVA_I2CS_DR_OFFSET)
|
||||
#define TIVA_I2CS9_IMR (TIVA_I2C9_BASE + TIVA_I2CS_IMR_OFFSET)
|
||||
#define TIVA_I2CS9_RIS (TIVA_I2C9_BASE + TIVA_I2CS_RIS_OFFSET)
|
||||
#define TIVA_I2CS9_MIS (TIVA_I2C9_BASE + TIVA_I2CS_MIS_OFFSET)
|
||||
#define TIVA_I2CS9_ICR (TIVA_I2C9_BASE + TIVA_I2CS_ICR_OFFSET)
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CS9_SOAR2 (TIVA_I2C9_BASE + TIVA_I2CS_SOAR2_OFFSET)
|
||||
# define TIVA_I2CS9_ACKCTL (TIVA_I2C9_BASE + TIVA_I2CS_ACKCTL_OFFSET)
|
||||
#endif
|
||||
|
||||
/* I2C Status and control */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define TIVA_I2CSC9_FIFODATA (TIVA_I2C9_BASE + TIVA_I2CSC_FIFODATA_OFFSET)
|
||||
# define TIVA_I2CSC9_FIFOCTL (TIVA_I2C9_BASE + TIVA_I2CSC_FIFOCTL_OFFSET)
|
||||
# define TIVA_I2CSC9_FIFOSTATUS (TIVA_I2C9_BASE + TIVA_I2CSC_FIFOSTATUS_OFFSET)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define TIVA_I2CSC9_PP (TIVA_I2C9_BASE + TIVA_I2CSC_PP_OFFSET)
|
||||
# define TIVA_I2CSC9_PC (TIVA_I2C9_BASE + TIVA_I2CSC_PC_OFFSET)
|
||||
#endif
|
||||
#endif /* TIVA_NI2C > 5 */
|
||||
|
||||
/* I2C_Register Bit Definitions *****************************************************/
|
||||
|
||||
/* I2C Master Slave Address (I2CM_SA) */
|
||||
@ -485,12 +692,11 @@
|
||||
#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */
|
||||
#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_CS_CLKTO (1 << 7) /* Bit 7: Clock Timeout Error (read) */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_CS_ACTDMATX (1 << 30) /* Bit 30: DMA TX Active Status (read) */
|
||||
# define I2CM_CS_ACTDMARX (1 << 31) /* Bit 31: DMA RX Active Status (read) */
|
||||
#endif
|
||||
@ -500,12 +706,11 @@
|
||||
#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */
|
||||
#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_CS_HS (1 << 4) /* Bit 4: High-Speed Enable (write) */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_CS_QCMD (1 << 5) /* Bit 5: Quick Command (write) */
|
||||
# define I2CM_CS_BURST (1 << 6) /* Bit 6: Burst Enable (write) */
|
||||
#endif
|
||||
@ -517,13 +722,12 @@
|
||||
|
||||
/* I2C Master Timer Period (I2CM_TPR) */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_TPR_SHIFT (0) /* Bits 6-0: SCL Clock Period */
|
||||
# define I2CM_TPR_MASK (0x7f << I2CM_TPR_SHIFT)
|
||||
# define I2CM_TPR_HS (1 << 7) /* Bit 7: High-Speed Enable (write) */
|
||||
|
||||
# if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
# if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_TPR_PULSEL_SHIFT (16) /* Bits 18-16: Glitch Suppression Pulse Width (write) */
|
||||
# define I2CM_TPR_PULSEL_MASK (7 << I2CM_TPR_PULSEL_SHIFT)
|
||||
# define I2CM_TPR_PULSEL_BYPASS (0 << I2CM_TPR_PULSEL_SHIFT) /* Bypass */
|
||||
@ -545,12 +749,11 @@
|
||||
|
||||
#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_IMR_CLKIM (1 << 1) /* Bit 1: Clock Timeout Interrupt Mask */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_IMR_DMARXIM (1 << 2) /* Bit 2: Receive DMA Interrupt Mask */
|
||||
# define I2CM_IMR_DMATXIM (1 << 3) /* Bit 3: Transmit DMA Interrupt Mask */
|
||||
# define I2CM_IMR_NACKIM (1 << 4) /* Bit 4: Address/Data NACK Interrupt Mask */
|
||||
@ -567,12 +770,11 @@
|
||||
|
||||
#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_RIS_CLKRIS (1 << 1) /* Bit 1: Clock Timeout Raw Interrupt Status */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_RIS_DMARXRIS (1 << 2) /* Bit 2: Receive DMA Interrupt Status */
|
||||
# define I2CM_RIS_DMATXRIS (1 << 3) /* Bit 3: Transmit DMA Interrupt Status */
|
||||
# define I2CM_RIS_NACKRIS (1 << 4) /* Bit 4: Address/Data NACK Interrupt Status */
|
||||
@ -589,12 +791,11 @@
|
||||
|
||||
#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_MIS_CLKMIS (1 << 1) /* Bit 1: Clock Timeout Masked Interrupt Status */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_MIS_DMARXMIS (1 << 2) /* Bit 2: Receive DMA Interrupt Status */
|
||||
# define I2CM_MIS_DMATXMIS (1 << 3) /* Bit 3: Transmit DMA Interrupt Status */
|
||||
# define I2CM_MIS_NACKMIS (1 << 4) /* Bit 4: Address/Data NACK Interrupt Status */
|
||||
@ -611,12 +812,11 @@
|
||||
|
||||
#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_ICR_CLKC (1 << 1) /* Bit 1: Clock Timeout Interrupt Clear */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_ICR_DMARXIC (1 << 2) /* Bit 2: Receive DMA Interrupt Clear */
|
||||
# define I2CM_ICR_DMATXIC (1 << 3) /* Bit 3: Transmit DMA Interrupt Clear */
|
||||
# define I2CM_ICR_NACKIC (1 << 4) /* Bit 4: Address/Data NACK Interrupt Clear */
|
||||
@ -641,30 +841,28 @@
|
||||
|
||||
/* I2C Master Clock Low Timeout Count */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_CLKOCNT_CNTL_SHIFT (0) /* Bits 7-0: I2C Master Count */
|
||||
# define I2CM_CLKOCNT_CNTL_MASK (0xff << I2CM_CLKOCNT_CNTL_SHIFT)
|
||||
#endif
|
||||
|
||||
/* I2C Master Configuration */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_BMON_SCL (1 << 0) /* Bit 0: II2C SCL Status */
|
||||
# define I2CM_BMON_SCA (1 << 1) /* Bit 1: II2C SDA Status */
|
||||
#endif
|
||||
|
||||
/* I2C Master Burst Length */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_BLEN_SHIFT (0) /* Bits 7-0: I2C Burst Length */
|
||||
# define I2CM_BLEN_MASK (0xff << I2CM_BLEN_SHIFT)
|
||||
#endif
|
||||
|
||||
/* I2C Master Burst Count */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_BCNT_SHIFT (0) /* Bits 7-0: I2C Burst Count */
|
||||
# define I2CM_BCNT_MASK (0xff << I2CM_BCNT_SHIFT)
|
||||
#endif
|
||||
@ -686,7 +884,7 @@
|
||||
|
||||
/* I2C Slave Own Address (I2CS_OAR) */
|
||||
|
||||
#define I2CS_OAR_MASK 0xff /* Bits 7-0: I2C Slave Own Address */
|
||||
#define I2CS_OAR_MASK 0x7f /* Bits 6-0: I2C Slave Own Address */
|
||||
|
||||
/* I2C Slave Control/Status (I2CS_CSR) */
|
||||
|
||||
@ -694,12 +892,11 @@
|
||||
#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */
|
||||
#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CS_CSR_OAR2SEL (1 << 3) /* Bit 3: OAR2 Address Matched (read) */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CS_CSR_QCMDST (1 << 4) /* Bit 4: Quick Command Status (read) */
|
||||
# define I2CS_CSR_QCMDRW (1 << 5) /* Bit 5: Quick Command Read / Write (read) */
|
||||
# define I2CS_CSR_ACTDMATX (1 << 30) /* Bit 30: DMA TX Active Status (read) */
|
||||
@ -708,7 +905,7 @@
|
||||
|
||||
#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CS_CSR_TXFIFO (1 << 1) /* Bit 1: TX FIFO Enable (write) */
|
||||
# define I2CS_CSR_RXFIFO (1 << 2) /* Bit 2: RX FIFO Enable (write) */
|
||||
#endif
|
||||
@ -722,13 +919,12 @@
|
||||
|
||||
#define I2CM_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_IMR_STARTIM (1 << 1) /* Bit 1: Start Condition Interrupt Mask */
|
||||
# define I2CM_IMR_STOPIM (1 << 2) /* Bit 2: Stop Condition Interrupt Mask */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_IMR_DMARXIM (1 << 3) /* Bit 3: Receive DMA Interrupt Mask */
|
||||
# define I2CM_IMR_DMATXIM (1 << 4) /* Bit 4: Transmit DMA Interrupt Mask */
|
||||
# define I2CM_IMR_TXIM (1 << 5) /* Bit 5: Transmit FIFO Request Interrupt Mask */
|
||||
@ -741,13 +937,12 @@
|
||||
|
||||
#define I2CM_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_RIS_STARTRIS (1 << 1) /* Bit 1: Start Condition Raw Interrupt Status */
|
||||
# define I2CM_RIS_STOPRIS (1 << 2) /* Bit 2: Stop Condition Raw Interrupt Status */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_RIS_DMARXRIS (1 << 3) /* Bit 3: Receive DMA Interrupt Mask */
|
||||
# define I2CM_RIS_DMATXRIS (1 << 4) /* Bit 4: Transmit DMA Interrupt Mask */
|
||||
# define I2CM_RIS_TXRIS (1 << 5) /* Bit 5: Transmit FIFO Request Interrupt Mask */
|
||||
@ -760,13 +955,12 @@
|
||||
|
||||
#define I2CM_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_MIS_STARTMIS (1 << 1) /* Bit 1: Start Condition Masked Interrupt Status */
|
||||
# define I2CM_MIS_STOPMIS (1 << 2) /* Bit 2: Stop Condition Masked Interrupt Status */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_MIS_DMARXMIS (1 << 3) /* Bit 3: Receive DMA Interrupt Mask */
|
||||
# define I2CM_MIS_DMATXMIS (1 << 4) /* Bit 4: Transmit DMA Interrupt Mask */
|
||||
# define I2CM_MIS_TXMIS (1 << 5) /* Bit 5: Transmit FIFO Request Interrupt Mask */
|
||||
@ -779,13 +973,12 @@
|
||||
|
||||
#define I2CM_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CM_ICR_STARTIC (1 << 1) /* Bit 1: Start Condition Interrupt Clear */
|
||||
# define I2CM_ICR_STOPIC (1 << 2) /* Bit 2: Stop Condition Interrupt Clear */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CM_ICR_DMARXIC (1 << 3) /* Bit 3: Receive DMA Interrupt Mask */
|
||||
# define I2CM_ICR_DMATXIC (1 << 4) /* Bit 4: Transmit DMA Interrupt Mask */
|
||||
# define I2CM_ICR_TXIC (1 << 5) /* Bit 5: Transmit FIFO Request Interrupt Mask */
|
||||
@ -796,8 +989,7 @@
|
||||
|
||||
/* I2C Slave Own Address 2 */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CS_SOAR2_SHIFT (0) /* Bits 0-6: I2C Slave Own Address 2 */
|
||||
# define I2CS_SOAR2_MASK (0x7f << I2CS_SOAR2_SHIFT)
|
||||
# define I2CS_SOAR2_OAR2EN (1 << 7) /* Bit 7: I2C Slave Own Address 2 Enable */
|
||||
@ -805,22 +997,21 @@
|
||||
|
||||
/* I2C Slave ACK Control */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CS_ACKCTL_ACKOEN (1 << 0) /* Bit 0: I2C Slave ACK Override Enable */
|
||||
# define I2CS_ACKCTL_ACKOVAL (1 << 1) /* Bit 1: I2C Slave ACK Override Value */
|
||||
#endif
|
||||
|
||||
/* I2C FIFO Data */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CSC_FIFODATA_SHIFT (0) /* Bits 7-0: I2C RX FIFO Read / Write Data Byte */
|
||||
# define I2CSC_FIFODATA_MASK (0xff << I2CSC_FIFODATA_SHIFT)
|
||||
#endif
|
||||
|
||||
/* I2C FIFO Control */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CSC_FIFOCTRL_TXTRIG_SHIFT (0) /* Bits 2-0: TX FIFO Trigger */
|
||||
# define I2CSC_FIFOCTRL_TXTRIG_MASK (7 << I2CSC_FIFOCTRL_TXTRIG_SHIFT)
|
||||
# define I2CSC_FIFOCTRL_TXTRIG(n) ((uint32_)(n) << I2CSC_FIFOCTRL_TXTRIG_SHIFT)
|
||||
@ -837,7 +1028,7 @@
|
||||
|
||||
/* I2C FIFO Status */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C129)
|
||||
# define I2CSC_FIFOSTATUS_TXFE (1 << 0) /* Bit 0: TX FIFO Empty */
|
||||
# define I2CSC_FIFOSTATUS_TXFF (1 << 1) /* Bit 1: TX FIFO Full */
|
||||
# define I2CSC_FIFOSTATUS_TXBLWTRIG (1 << 2) /* Bit 2: TX FIFO Below Trigger Level */
|
||||
@ -848,15 +1039,13 @@
|
||||
|
||||
/* I2C Peripheral Properties */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CSC_PP_HS (1 << 0) /* Bit 0: High-Speed Capable */
|
||||
#endif
|
||||
|
||||
/* I2C Peripheral Configuration */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C123GH6ZRB) || \
|
||||
defined(CONFIG_ARCH_CHIP_TM4C1294NC)
|
||||
#if defined(CONFIG_ARCH_CHIP_TM4C)
|
||||
# define I2CSC_PC_HS (1 << 0) /* Bit 0: High-Speed Capable */
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user