SAMA5 SSC: If running from SDRAM, BOARD_MCK_FREQUENCY is not a constant and cannot be used in pre-processor conditionals
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Gregory Nutt
parent
be1bd45076
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67bea2d342
@ -268,12 +268,14 @@ config SAMA5_SSC0
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default n
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select I2S
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depends on SAMA5_DMAC0
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select AUDIO
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config SAMA5_SSC1
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bool "Synchronous Serial Controller 1 (SSC1)"
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default n
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select I2S
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depends on SAMA5_DMAC1
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select AUDIO
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config SAMA5_CAN0
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bool "CAN controller 0 (CAN0)"
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@ -300,7 +302,7 @@ config SAMA5_TDES
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config SAMA5_TRNG
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bool "True Random Number Generator (TRNG)"
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default n
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select DEV_RANDOM
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select ARCH_HAVE_RNG
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config SAMA5_ARM
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bool "Performance Monitor Unit (ARM)"
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/sama5/sam_ssc.c
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -55,6 +55,7 @@
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#include <nuttx/arch.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/wqueue.h>
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#include <nuttx/audio/audio.h>
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#include <nuttx/audio/i2s.h>
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#include "up_internal.h"
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@ -102,6 +103,10 @@
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# error Invalid value for CONFIG_SAMA5_SSC0_DATALEN
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#endif
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#ifndef CONFIG_AUDIO
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# error CONFIG_AUDIO required by this driver
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#endif
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/* Check if we need to build RX and/or TX support */
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#undef SSC_HAVE_RX
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@ -117,6 +122,8 @@
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# define SSC_HAVE_TX
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#endif
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#if defined(SSC_HAVE_RX) || defined(SSC_HAVE_TX)
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/* Check if we need the sample rate to set MCK/2 divider */
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#undef SSC_HAVE_MCK2
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@ -161,27 +168,6 @@
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#define SCC_PERIOD (SSC_FSLEN + CONFIG_SAMA5_SSC0_DATALEN * SSC_DATNB)
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/* Clocking *****************************************************************/
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/* Select MCU-specific settings
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*
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* SSC is driven by the main clock, divided down so that the maximum
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* peripheral clocking is not exceeded.
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*/
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#if BOARD_MCK_FREQUENCY <= SAM_SSC_MAXPERCLK
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# define SSC_FREQUENCY BOARD_MCK_FREQUENCY
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# define SSC_PCR_DIV PMC_PCR_DIV1
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#elif (BOARD_MCK_FREQUENCY >> 1) <= SAM_SSC_MAXPERCLK
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# define SSC_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
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# define SSC_PCR_DIV PMC_PCR_DIV2
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#elif (BOARD_MCK_FREQUENCY >> 2) <= SAM_SSC_MAXPERCLK
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# define SSC_FREQUENCY (BOARD_MCK_FREQUENCY >> 2)
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# define SSC_PCR_DIV PMC_PCR_DIV4
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#elif (BOARD_MCK_FREQUENCY >> 3) <= SAM_SSC_MAXPERCLK
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# define SSC_FREQUENCY (BOARD_MCK_FREQUENCY >> 3)
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# define SSC_PCR_DIV PMC_PCR_DIV8
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#else
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# error Cannot realize SSC input frequency
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#endif
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/* Clock source definitions */
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@ -316,6 +302,8 @@ struct sam_ssc_s
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struct i2s_dev_s dev; /* Externally visible I2S interface */
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uintptr_t base; /* SSC controller register base address */
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sem_t exclsem; /* Assures mutually exclusive acess to SSC */
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uint8_t datalen; /* Data width (2-32) */
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uint8_t pid; /* Peripheral ID */
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uint16_t rxenab:1; /* True: RX transfers enabled */
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uint16_t txenab:1; /* True: TX transfers enabled */
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uint16_t loopback:1; /* True: Loopback mode */
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@ -324,8 +312,7 @@ struct sam_ssc_s
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uint16_t txclk:2; /* Transmitter clock source. See SSC_CLKSRC_* definitions */
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uint16_t rxout:2; /* Receiver clock output. See SSC_CLKOUT_* definitions */
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uint16_t txout:2; /* Transmitter clock output. See SSC_CLKOUT_* definitions */
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uint8_t datalen; /* Data width (2-32) */
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uint8_t pid; /* Peripheral ID */
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uint32_t frequency; /* SSC clock frequency */
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#ifdef SSC_HAVE_MCK2
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uint32_t samplerate; /* Data sample rate (determines only MCK/2 divider) */
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#endif
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@ -757,7 +744,7 @@ static void ssc_exclsem_take(struct sam_ssc_s *priv)
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}
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/****************************************************************************
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* Name: ssc_exclsem_take
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* Name: ssc_bufsem_take
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*
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* Description:
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* Take the buffer semaphore handling any exceptional conditions
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@ -1994,9 +1981,11 @@ static int ssc_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
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i2s_callback_t callback, void *arg, uint32_t timeout)
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{
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struct sam_ssc_s *priv = (struct sam_ssc_s *)dev;
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#ifdef SSC_HAVE_RX
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struct sam_buffer_s *bfcontainer;
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irqstate_t flags;
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int ret;
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#endif
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DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & 3) == 0);
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i2svdbg("apb=%p nmaxbytes=%d arg=%p timeout=%d\n",
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@ -2058,6 +2047,7 @@ errout_with_exclsem:
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#else
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i2sdbg("ERROR: SSC%d has no receiver\n", priv->sscno);
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UNUSED(priv);
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return -ENOSYS;
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#endif
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}
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@ -2197,9 +2187,11 @@ static int ssc_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb,
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i2s_callback_t callback, void *arg, uint32_t timeout)
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{
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struct sam_ssc_s *priv = (struct sam_ssc_s *)dev;
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#ifdef SSC_HAVE_TX
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struct sam_buffer_s *bfcontainer;
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irqstate_t flags;
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int ret;
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#endif
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DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & 3) == 0);
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i2svdbg("apb=%p nbytes=%d arg=%p timeout=%d\n",
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@ -2261,6 +2253,7 @@ errout_with_exclsem:
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#else
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i2sdbg("ERROR: SSC%d has no transmitter\n", priv->sscno);
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UNUSED(priv);
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return -ENOSYS;
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#endif
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}
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@ -2598,10 +2591,37 @@ static uint32_t ssc_mck2divider(struct sam_ssc_s *priv)
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static void ssc_clocking(struct sam_ssc_s *priv)
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{
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uint32_t regval;
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uint32_t mck;
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/* Determine the maximum SSC peripheral clock frequency */
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mck = BOARD_MCK_FREQUENCY;
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DEBUGASSERT((mck >> 3) <= SAM_SSC_MAXPERCLK);
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if (mck <= SAM_SSC_MAXPERCLK)
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{
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priv->frequency = mck;
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regval = PMC_PCR_DIV1;
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}
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else if ((mck >> 1) <= SAM_SSC_MAXPERCLK)
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{
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priv->frequency = (mck >> 1);
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regval = PMC_PCR_DIV2;
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}
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else if ((mck >> 2) <= SAM_SSC_MAXPERCLK)
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{
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priv->frequency = (mck >> 2);
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regval = PMC_PCR_DIV4;
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}
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else /* if ((mck >> 3) <= SAM_SSC_MAXPERCLK) */
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{
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priv->frequency = (mck >> 3);
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regval = PMC_PCR_DIV8;
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}
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/* Set the maximum SSC peripheral clock frequency */
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regval = PMC_PCR_PID(priv->pid) | PMC_PCR_CMD | SSC_PCR_DIV | PMC_PCR_EN;
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regval |= PMC_PCR_PID(priv->pid) | PMC_PCR_CMD | PMC_PCR_EN;
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putreg32(regval, SAM_PMC_PCR);
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/* Reset, disable receiver & transmitter */
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@ -3189,4 +3209,5 @@ errout_with_alloc:
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return NULL;
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}
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#endif /* SSC_HAVE_RX || SSC_HAVE_TX */
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#endif /* CONFIG_SAMA5_SSC0 || CONFIG_SAMA5_SSC1 */
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