Add GPIO IRQ logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1779 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -46,6 +46,7 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/irq.h>
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/************************************************************************************
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* Definitions
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@ -121,6 +122,124 @@
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#define NR_IRQS (60) /* Really only 43 */
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/* GPIO IRQs -- Note that support for individual GPIO ports can
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* be disabled in order to reduce the size of the implemenation.
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*/
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#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
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# define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
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# define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
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# define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
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# define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3)
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# define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4)
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# define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5)
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# define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6)
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# define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7)
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# define _NGPIOAIRQS (NR_IRQS + 8)
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#else
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# define _NGPIOAIRQS NR_IRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
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# define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
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# define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
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# define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
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# define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
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# define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
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# define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
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# define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
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# define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
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# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
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#else
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# define _NGPIOBIRQS _NGPIOAIRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
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# define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
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# define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
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# define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
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# define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
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# define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
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# define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
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# define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
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# define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
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# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
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#else
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# define _NGPIOCIRQS _NGPIOBIRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
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# define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
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# define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
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# define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
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# define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
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# define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
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# define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
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# define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
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# define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
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# define _NGPIODIRQS (_NGPIOCIRQS + 8)
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#else
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# define _NGPIODIRQS _NGPIOCIRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
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# define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
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# define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
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# define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
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# define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
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# define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
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# define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
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# define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
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# define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
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# define _NGPIOEIRQS (_NGPIODIRQS + 8)
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#else
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# define _NGPIOEIRQS _NGPIODIRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
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# define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
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# define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
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# define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
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# define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
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# define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
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# define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
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# define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
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# define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
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# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
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#else
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# define _NGPIOFIRQS _NGPIOEIRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
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# define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
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# define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
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# define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
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# define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
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# define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
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# define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
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# define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
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# define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
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# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
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#else
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# define _NGPIOGIRQS _NGPIOFIRQS
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
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# define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
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# define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
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# define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
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# define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
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# define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
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# define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
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# define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
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# define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
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# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
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#else
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# define _NGPIOHIRQS _NGPIOGIRQS
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#endif
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#define NR_GPIO_IRQS (_NGPIOHIRQS - NR_IRQS)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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@ -141,6 +260,37 @@ extern "C" {
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* Public Functions
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************************************************************************************/
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/****************************************************************************
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* Name: gpio_irqattach
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*
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* Description:
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* Attach the interrupt handler 'isr' to the GPIO IRQ 'irq'
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*
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****************************************************************************/
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EXTERN int gpio_irqattach(int irq, xcpt_t isr);
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#define gpio_irqdetach(isr) gpio_irqattach(isr, NULL)
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/****************************************************************************
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* Name: gpio_irqenable
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*
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* Description:
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* Enable the GPIO IRQ specified by 'irq'
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*
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****************************************************************************/
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EXTERN void gpio_irqenable(int irq);
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/****************************************************************************
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* Name: gpio_irqdisable
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*
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* Description:
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* Disable the GPIO IRQ specified by 'irq'
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*
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****************************************************************************/
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EXTERN void gpio_irqdisable(int irq);
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#undef EXTERN
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#ifdef __cplusplus
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}
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@ -47,7 +47,8 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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CHIP_ASRCS = lm3s_context.S
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CHIP_CSRCS = lm3s_start.c lm3s_syscontrol.c lm3s_irq.c lm3s_pendsv.c \
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lm3s_gpio.c lm3s_timerisr.c lm3s_lowputc.c lm3s_serial.c
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lm3s_gpio.c lm3s_gpioirq.c lm3s_timerisr.c lm3s_lowputc.c \
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lm3s_serial.c
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ifdef CONFIG_NET
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CHIP_CSRCS += lm3s_ethernet.c
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394
arch/arm/src/lm3s/lm3s_gpioirq.c
Normal file
394
arch/arm/src/lm3s/lm3s_gpioirq.c
Normal file
@ -0,0 +1,394 @@
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/****************************************************************************
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* arch/arm/src/lm3s/lm3s_gpioirq.c
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* arch/arm/src/chip/lm3s_gpioirq.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <string.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/irq.h>
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#include "up_arch.h"
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#include "os_internal.h"
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#include "irq_internal.h"
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#include "lm3s_internal.h"
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/****************************************************************************
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* Private Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* A table of handlers for each GPIO interrupt */
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static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
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/* A table that maps a GPIO group to a GPIO base address. Overly complicated
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* be we support disabling interrupt support for arbitrary ports
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*/
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static const uint32 g_gpiobase[] =
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{
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#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
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LM3S_GPIOA_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
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LM3S_GPIOB_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
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LM3S_GPIOC_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
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LM3S_GPIOD_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
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LM3S_GPIOE_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
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LM3S_GPIOF_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
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LM3S_GPIOG_BASE,
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
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LM3S_GPIOH_BASE,
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#endif
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};
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lm3s_gpiobaseaddress
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*
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* Description:
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* Given a GPIO enumeration value, return the base address of the
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* associated GPIO registers.
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*
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****************************************************************************/
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static inline uint32 lm3s_gpiobaseaddress(unsigned int port)
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{
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return g_gpiobase[port >> 3];
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}
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/****************************************************************************
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* Name: lm3s_gpio*handler
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*
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* Description:
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* Handle interrupts on each enabled GPIO port
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*
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****************************************************************************/
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static int lm3s_gpiohandler(uint32 regbase, int irqbase, void *context)
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{
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uint32 mis;
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int irq;
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int pin;
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/* Handle each pending GPIO interrupt. "The GPIO MIS register is the masked
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* interrupt status register. Bits read High in GPIO MIS reflect the status
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* of input lines triggering an interrupt. Bits read as Low indicate that
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* either no interrupt has been generated, or the interrupt is masked."
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*/
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mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
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/* Clear all GPIO interrupts that we are going to process. "The GPIO ICR
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* register is the interrupt clear register. Writing a 1 to a bit in this
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* register clears the corresponding interrupt edge detection logic register.
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* Writing a 0 has no effect."
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*/
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putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
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/* Now process each IRQ pending in the MIS */
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for (pin = 0; pin < 8 && mis != 0; pin++, mis >>= 1)
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{
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if ((mis & 1) != 0)
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{
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irq = irqbase + pin;
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g_gpioirqvector[irq - NR_IRQS](irq, context);
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}
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}
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return OK;
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}
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#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
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static int lm3s_gpioahandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
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static int lm3s_gpiobhandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
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static int lm3s_gpiochandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
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static int lm3s_gpiodhandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
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static int lm3s_gpioehandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
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static int lm3s_gpiofhandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
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static int lm3s_gpioghandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
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}
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
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static int lm3s_gpiohhandler(int irq, FAR void *context)
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{
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return lm3s_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: gpio_irqinitialize
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*
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* Description:
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* Initialize all vectors to the unexpected interrupt handler
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*
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****************************************************************************/
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int gpio_irqinitialize(void)
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{
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int i;
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/* Point all interrupt vectors to the unexpected interrupt */
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for (i = 0; i < NR_GPIO_IRQS; i++)
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{
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g_gpioirqvector[i] = irq_unexpected_isr;
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}
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/* Then attach all GPIO interrupt handlers */
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#ifndef CONFIG_LM3S_DISABLE_GPIOA_IRQS
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irq_attach(LM3S_IRQ_GPIOA, lm3s_gpioahandler);
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOB_IRQS
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irq_attach(LM3S_IRQ_GPIOB, lm3s_gpiobhandler);
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#endif
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#ifndef CONFIG_LM3S_DISABLE_GPIOC_IRQS
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irq_attach(LM3S_IRQ_GPIOC, lm3s_gpiochandler);
|
||||
#endif
|
||||
#ifndef CONFIG_LM3S_DISABLE_GPIOD_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOD, lm3s_gpiodhandler);
|
||||
#endif
|
||||
#ifndef CONFIG_LM3S_DISABLE_GPIOE_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOE, lm3s_gpioehandler);
|
||||
#endif
|
||||
#ifndef CONFIG_LM3S_DISABLE_GPIOF_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOF, lm3s_gpiofhandler);
|
||||
#endif
|
||||
#ifndef CONFIG_LM3S_DISABLE_GPIOG_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOG, lm3s_gpioghandler);
|
||||
#endif
|
||||
#ifndef CONFIG_LM3S_DISABLE_GPIOH_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOH, lm3s_gpiohhandler);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gpio_irqattach
|
||||
*
|
||||
* Description:
|
||||
* Attach in GPIO interrupt to the provide 'isr'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int gpio_irqattach(int irq, xcpt_t isr)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int gpioirq = irq - NR_IRQS;
|
||||
int ret = ERROR;
|
||||
|
||||
if ((unsigned)gpioirq < NR_GPIO_IRQS)
|
||||
{
|
||||
flags = irqsave();
|
||||
|
||||
/* If the new ISR is NULL, then the ISR is being detached.
|
||||
* In this case, disable the ISR and direct any interrupts
|
||||
* to the unexpected interrupt handler.
|
||||
*/
|
||||
|
||||
if (isr == NULL)
|
||||
{
|
||||
#ifndef CONFIG_ARCH_NOINTC
|
||||
gpio_irqdisable(gpioirq);
|
||||
#endif
|
||||
isr = irq_unexpected_isr;
|
||||
}
|
||||
|
||||
/* Save the new ISR in the table. */
|
||||
|
||||
g_irqvector[gpioirq] = isr;
|
||||
irqrestore(flags);
|
||||
ret = OK;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gpio_irqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the GPIO IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void gpio_irqenable(int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int gpioirq = irq - NR_IRQS;
|
||||
uint32 base;
|
||||
uint32 regval;
|
||||
int pin;
|
||||
int ret = ERROR;
|
||||
|
||||
if ((unsigned)gpioirq < NR_GPIO_IRQS)
|
||||
{
|
||||
/* Get the base address of the GPIO module associated with this IRQ */
|
||||
|
||||
base = lm3s_gpiobaseaddress(gpioirq);
|
||||
pin = (1 << (gpioirq & 7));
|
||||
|
||||
/* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
|
||||
* mask register. Bits set to High in GPIO IM allow the corresponding
|
||||
* pins to trigger their individual interrupts and the combined GPIO INTR
|
||||
* line. Clearing a bit disables interrupt triggering on that pin. All
|
||||
* bits are cleared by a reset.
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
|
||||
regval |= pin;
|
||||
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
|
||||
irqrestore(flags);
|
||||
ret = OK;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gpio_irqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the GPIO IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void gpio_irqdisable(int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int gpioirq = irq - NR_IRQS;
|
||||
uint32 base;
|
||||
uint32 regval;
|
||||
int pin;
|
||||
int ret = ERROR;
|
||||
|
||||
if ((unsigned)gpioirq < NR_GPIO_IRQS)
|
||||
{
|
||||
/* Get the base address of the GPIO module associated with this IRQ */
|
||||
|
||||
base = lm3s_gpiobaseaddress(gpioirq);
|
||||
pin = (1 << (gpioirq & 7));
|
||||
|
||||
/* Disable the GPIO interrupt. "The GPIO IM register is the interrupt
|
||||
* mask register. Bits set to High in GPIO IM allow the corresponding
|
||||
* pins to trigger their individual interrupts and the combined GPIO INTR
|
||||
* line. Clearing a bit disables interrupt triggering on that pin. All
|
||||
* bits are cleared by a reset.
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
|
||||
irqrestore(flags);
|
||||
ret = OK;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -250,8 +250,6 @@ EXTERN void lm3s_clockconfig(uint32 newrcc, uint32 newrcc2);
|
||||
|
||||
EXTERN void up_clockconfig(void);
|
||||
|
||||
/* Configure a GPIO pin */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lm3s_configgpio
|
||||
*
|
||||
@ -292,6 +290,16 @@ EXTERN void lm3s_gpiowrite(uint32 pinset, boolean value);
|
||||
|
||||
EXTERN boolean lm3s_gpioread(uint32 pinset, boolean value);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: gpio_irqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize all vectors to the unexpected interrupt handler
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
EXTERN int weak_function gpio_irqinitialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
@ -175,6 +175,17 @@ void up_irqinitialize(void)
|
||||
|
||||
current_regs = NULL;
|
||||
|
||||
/* Initialize support for GPIO interrupts if included in this build */
|
||||
|
||||
#ifndef CONFIG_LM3S_DISABLE_GPIO_IRQS
|
||||
#ifdef CONFIG_HAVE_WEAKFUNCTIONS
|
||||
if (gpio_irqinitialize != NULL)
|
||||
#endif
|
||||
{
|
||||
gpio_irqinitialize();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Attach the PendSV exception handler and set it to the minimum
|
||||
* prioirity. The PendSV exception is used for performing
|
||||
* context switches.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user