Add single-wire UART support to STM32 serial driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5552 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -4009,5 +4009,7 @@
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* arch/arm/src/*/*_irq.c: Set the priority of the SVCALL exception
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to the highest possible value.
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* arch/armv7-m/up_hardfault.c: Fail if a hardfault occurs
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while CONFIG_ARM7VM_USEBASEI=y.
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while CONFIG_ARM7VM_USEBASEPRI=y.
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* arch/arm/src/stm32/stm32_serial.c: Add support for USART
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single wire more (Contributed by the PX4 team).
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@ -457,32 +457,38 @@ config STM32_USART1
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bool "USART1"
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default n
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select ARCH_HAVE_USART1
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select STM32_USART
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config STM32_USART2
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bool "USART2"
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default n
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select ARCH_HAVE_USART2
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select STM32_USART
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config STM32_USART3
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bool "USART3"
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default n
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select ARCH_HAVE_USART3
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select STM32_USART
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config STM32_UART4
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bool "UART4"
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default n
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select ARCH_HAVE_UART4
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select STM32_USART
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config STM32_UART5
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bool "UART5"
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default n
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select ARCH_HAVE_UART5
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select STM32_USART
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config STM32_USART6
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bool "USART6"
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default n
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depends on STM32_STM32F20XX || STM32_STM32F40XX
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select ARCH_HAVE_USART6
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select STM32_USART
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config STM32_USB
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bool "USB Device"
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@ -1804,8 +1810,11 @@ config STM32_TIM14_DAC2
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endchoice
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bool STM32_USART
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bool
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menu "U[S]ART Configuration"
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depends on STM32_USART1 || STM32_USART2 || STM32_USART3 || STM32_USART4 || STM32_USART5 || STM32_USART6
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depends on STM32_USART
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config USART1_RS485
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bool "RS-485 on USART1"
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@ -1968,6 +1977,14 @@ config SERIAL_TERMIOS
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endmenu
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config STM32_USART_SINGLEWIRE
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bool "Single Wire Support"
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default n
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depends on STM32_USART
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---help---
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Enable single wire UART support. The option enables support for the
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TIOCSSINGLEWIRE ioctl in the STM32 serial driver.
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menu "SPI Configuration"
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depends on STM32_SPI
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/stm32/stm32_serial.c
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*
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* Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -1401,6 +1401,31 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
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}
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break;
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#ifdef CONFIG_STM32_USART_SINGLEWIRE
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case TIOCSSINGLEWIRE:
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{
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/* Change the TX port to be open-drain/push-pull and enable/disable
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* half-duplex mode.
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*/
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uint32_t cr = up_serialin(priv, STM32_USART_CR3_OFFSET);
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if (arg == SER_SINGLEWIRE_ENABLED)
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{
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stm32_configgpio(priv->tx_gpio | GPIO_OPENDRAIN);
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cr |= USART_CR3_HDSEL;
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}
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else
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{
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stm32_configgpio(priv->tx_gpio | GPIO_PUSHPULL);
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cr &= ~USART_CR3_HDSEL;
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}
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up_serialout(priv, STM32_USART_CR3_OFFSET, cr);
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}
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break;
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#endif
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#ifdef CONFIG_SERIAL_TERMIOS
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case TCGETS:
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{
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@ -1,7 +1,7 @@
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/********************************************************************************************
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* include/nuttx/serial/tioctl.h
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*
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -165,16 +165,23 @@
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#define TIOCSRS485 _TIOC(0x002a) /* Set RS485 mode, arg: pointer to struct serial_rs485 */
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#define TIOCGRS485 _TIOC(0x002b) /* Get RS485 mode, arg: pointer to struct serial_rs485 */
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/* Definitions for flags used in struct serial_rs485 (Linux compatible) */
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# define SER_RS485_ENABLED (1 << 0) /* Enable/disble RS-485 support */
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# define SER_RS485_RTS_ON_SEND (1 << 1) /* Logic level for RTS pin when sending */
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# define SER_RS485_RTS_AFTER_SEND (1 << 2) /* Logic level for RTS pin after sent */
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# define SER_RS485_RX_DURING_TX (1 << 4)
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/* Single-wire UART support */
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#define TIOCSSINGLEWIRE _TIOC(0x002c) /* Set single-wire mode */
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#define TIOCGSINGLEWIRE _TIOC(0x002d) /* Get single-wire mode */
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# define SER_SINGLEWIRE_ENABLED (1 << 0) /* Enable/disable single-wire support */
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/* Debugging */
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#define TIOCSERGSTRUCT _TIOC(0x002c) /* Get device TTY structure */
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/* Definitions used in struct serial_rs485 (Linux compatible) */
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#define SER_RS485_ENABLED (1 << 0) /* Enable/disble RS-485 support */
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#define SER_RS485_RTS_ON_SEND (1 << 1) /* Logic level for RTS pin when sending */
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#define SER_RS485_RTS_AFTER_SEND (1 << 2) /* Logic level for RTS pin after sent */
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#define SER_RS485_RX_DURING_TX (1 << 4)
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#define TIOCSERGSTRUCT _TIOC(0x002e) /* Get device TTY structure */
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/********************************************************************************************
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* Public Type Definitions
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