Fixes for STM32 ADC driver on the F4; LC17xx LED initial state
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4257 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
58b5d8f9b6
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686b63f5d0
@ -162,7 +162,7 @@ static void adc_timstart(FAR struct stm32_dev_s *priv, bool enable);
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static int adc_timinit(FAR struct stm32_dev_s *priv);
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#endif
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#ifdef CONFIG_ADC_DMA
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#ifdef CONFIG_STM32_STM32F40XX
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static void adc_startconv(FAR struct stm32_dev_s *priv, bool enable);
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#endif
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@ -226,7 +226,7 @@ static struct stm32_dev_s g_adcpriv2 =
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.intf = 2;
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.base = STM32_ADC2_BASE,
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#ifdef ADC2_HAVE_TIMER
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.trigger = CONFIG_STM32_ADC2_TIMTRIG;
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.trigger = CONFIG_STM32_ADC2_TIMTRIG,
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.tbase = ADC2_TIMER_BASE,
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.extsel = ADC2_EXTSEL_VALUE,
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.pclck = ADC2_TIMER_PCLK_FREQUENCY,
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@ -253,10 +253,10 @@ static struct stm32_dev_s g_adcpriv3 =
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.irq = STM32_IRQ_ADC,
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.isr = adc123_interrupt,
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#endif
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.intf = 3;
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.intf = 3,
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.base = STM32_ADC3_BASE,
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#ifdef ADC3_HAVE_TIMER
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.trigger = CONFIG_STM32_ADC3_TIMTRIG;
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.trigger = CONFIG_STM32_ADC3_TIMTRIG,
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.tbase = ADC3_TIMER_BASE,
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.extsel = ADC3_EXTSEL_VALUE,
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.pclck = ADC3_TIMER_PCLK_FREQUENCY,
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@ -485,27 +485,31 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
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uint16_t ccenable;
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uint16_t ccer;
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uint16_t egr;
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avdbg("Initializing timers extsel = %d\n", priv->extsel);
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/* If the timer base address is zero, then this ADC was not configured to
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* use a timer.
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*/
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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#ifdef CONFIG_STM32_STM32F10XX
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if (!priv->tbase)
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{
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/* Configure the ADC to use the selected timer and timer channel as the trigger
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* EXTTRIG: External Trigger Conversion mode for regular channels DISABLE
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*/
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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regval &= ~ADC_CR2_EXTTRIG;
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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return OK;
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}
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else
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{
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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regval |= ADC_CR2_EXTTRIG;
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}
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#endif
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/* EXTSEL selection: These bits select the external event used to trigger
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* the start of conversion of a regular group. NOTE:
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@ -803,14 +807,14 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)
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*
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****************************************************************************/
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#ifdef CONFIG_ADC_DMA
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#ifdef CONFIG_STM32_STM32F40XX
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static void adc_startconv(struct stm32_dev_s *priv, bool enable)
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{
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uint32_t regval;
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avdbg("enable: %d\n", enable);
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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regval = adc_getreg(priv, STM32_ADC_CR2_OFFSET);
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if (enable)
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{
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/* Start conversion of regular channles */
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@ -961,6 +965,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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uint32_t regval;
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int offset;
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int i;
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int ret;
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avdbg("intf: ADC%d\n", priv->intf);
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flags = irqsave();
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@ -1014,21 +1019,24 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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/* Initialize the Analog watchdog enable */
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regval |= ADC_CR1_AWDEN;
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regval |= (priv->chanlist[0] << ADC_CR1_AWDCH_SHIFT);
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/* Enable interrupt flags */
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regval |= ADC_CR1_ALLINTS;
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adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
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/* ADC CCR configuration */
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#ifdef CONFIG_STM32_STM32F40XX
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regval |= adc_getreg(priv, STM32_ADC_CCR_OFFSET);
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regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK |
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ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
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regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2);
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adc_putreg(priv, STM32_ADC_CCR_OFFSET, regval);
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/* Enable or disable Overrun interrupt */
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regval &= ~ADC_CR1_OVRIE;
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/* Set the resolution of the conversion */
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regval |= ACD_CR1_RES_12BIT;
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#endif
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adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
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/* ADC CR2 Configuration */
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@ -1041,22 +1049,15 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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/* Set ALIGN (Right = 0) */
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regval &= ~ADC_CR2_ALIGN;
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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#if 0
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#ifdef CONFIG_STM32_STM32F10XX
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/* ADC reset calibaration register */
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regval |= ADC_CR2_RSTCAL;
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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usleep(5);
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/* A/D Calibration */
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regval |= ADC_CR2_CAL;
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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#endif
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#ifdef CONFIG_STM32_STM32F40XX
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/* External trigger enable for regular channels */
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regval |= ACD_CR2_EXTEN_RISING;
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#endif
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adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);
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/* Configuration of the channel conversions */
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regval = adc_getreg(priv, STM32_ADC_SQR3_OFFSET) & ADC_SQR3_RESERVED;
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@ -1078,6 +1079,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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{
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regval |= (uint32_t)priv->chanlist[i] << offset;
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}
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/* ADC CCR configuration */
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#ifdef CONFIG_STM32_STM32F40XX
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regval = getreg32(STM32_ADC_CCR);
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regval &= ~(ADC_CCR_MULTI_MASK | ADC_CCR_DELAY_MASK | ADC_CCR_DDS | ADC_CCR_DMA_MASK |
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ADC_CCR_ADCPRE_MASK | ADC_CCR_VBATE | ADC_CCR_TSVREFE);
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regval |= (ADC_CCR_MULTI_NONE | ADC_CCR_DMA_DISABLED | ADC_CCR_ADCPRE_DIV2);
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putreg32(regval, STM32_ADC_CCR);
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#endif
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/* Set the number of conversions */
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@ -1101,12 +1112,16 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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adbg("Error initializing the timers\n");
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}
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#else
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#ifdef CONFIG_STM32_STM32F10XX
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/* Set ADON (Again) to start the conversion. Only if Timers are not
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* configured as triggers
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*/
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adc_enable(priv, true);
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#endif
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#else
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adc_startconv(priv, true);
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#endif /* CONFIG_STM32_STM32F10XX */
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#endif /* ADC_HAVE_TIMER */
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irqrestore(flags);
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@ -1118,6 +1133,10 @@ static void adc_reset(FAR struct adc_dev_s *dev)
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adc_getreg(priv, STM32_ADC_SQR1_OFFSET),
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adc_getreg(priv, STM32_ADC_SQR2_OFFSET),
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adc_getreg(priv, STM32_ADC_SQR3_OFFSET));
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#ifdef CONFIG_STM32_STM32F40XX
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avdbg("CCR: 0x%08x\n",
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getreg32(STM32_ADC_CCR));
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#endif
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}
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/****************************************************************************
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@ -1228,7 +1247,7 @@ static void adc_rxint(FAR struct adc_dev_s *dev, bool enable)
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*
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****************************************************************************/
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static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
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static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
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{
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return -ENOTTY;
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}
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@ -1251,14 +1270,21 @@ static int adc_interrupt(FAR struct adc_dev_s *dev)
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uint32_t adcsr;
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int32_t value;
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/* Identifies the interruption AWD or EOC */
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/* Identifies the interruption AWD, OVR or EOC */
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adcsr = adc_getreg(priv, STM32_ADC_SR_OFFSET);
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if ((adcsr & ADC_SR_AWD) != 0)
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{
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adbg("WARNING: Analog Watchdog, Value converted out of range!\n");
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alldbg("WARNING: Analog Watchdog, Value converted out of range!\n");
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}
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#ifdef CONFIG_STM32_STM32F40XX
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if ((adcsr & ADC_SR_OVR) != 0)
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{
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alldbg("WARNING: Overrun has ocurred!\n");
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}
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#endif
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/* EOC: End of conversion */
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if ((adcsr & ADC_SR_EOC) != 0)
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