LPC-H3131 SDRAM: Fix some build issues
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Gregory Nutt
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commit
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@ -578,7 +578,79 @@ Configurations
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- Toolchain: CodeSourcery for Windows
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NOTES:
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1. This configuration has been used to test USB host functionaly. USB
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1. Built-in applications are not supported by default. To enable NSH
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built-in applications:
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Binary
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CONFIG_BUILTIN=y : Support built-in applications
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Application Configuration -> NSH Library
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CONFIG_NSH_BUILTIN_APPS=y : Enable built-in applications
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2. SDRAM support is not enabled by default. SDRAM support can be enabled
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by adding the following to your NuttX configuration file:
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System Type->LPC31xx Peripheral Support
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CONFIG_LPC31_EXTDRAM=y : Enable external DRAM support
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CONFIG_LPC31_EXTDRAMSIZE=33554432 : 256Mbit -> 32Mbyte
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CONFIG_LPC31_SDRAM_16BIT=y : Organized 16Mbit x 16 bits wide
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Now that you have SDRAM enabled, what are you going to do with it? One
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thing you can is add it to the heap
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System Type->Heap Configuration
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CONFIG_LPC31_EXTDRAMHEAP=y : Add the SDRAM to the heap
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Memory Management
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CONFIG_MM_REGIONS=2 : Two memory regions: ISRAM and SDRAM
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Another thing you could do is to enable the RAM test built-in
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application:
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3. You can enable the NuttX RAM test that may be used to verify the
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external SDAM. To do this, keep the SDRAM out of the heap so that
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it can be tested without crashing programs using the memory.
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First enable built-in applications as described above, then make
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the following additional modifications to the NuttX configuration:
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System Type->Heap Configuration
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CONFIG_LPC31_EXTDRAMHEAP=n : Don't add the SDRAM to the heap
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Memory Management
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CONFIG_MM_REGIONS=1 : One memory regions: ISRAM
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Then enable the RAM test built-in application:
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Application Configuration->System NSH Add-Ons->Ram Test
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CONFIG_SYSTEM_RAMTEST=y
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In this configuration, the SDRAM is not added to heap and so is not
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excessible to the applications. So the RAM test can be freely
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executed against the SRAM memory beginning at address 0x2000:0000
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(DDR CS):
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nsh> ramtest -h
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Usage: ramtest [-w|h|b] <hex-address> <decimal-size>
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Where:
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<hex-address> starting address of the test.
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<decimal-size> number of memory locations (in bytes).
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-w Sets the width of a memory location to 32-bits.
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-h Sets the width of a memory location to 16-bits (default).
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-b Sets the width of a memory location to 8-bits.
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To test the entire external 256MB SRAM:
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nsh> ramtest -w 30000000 33554432
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RAMTest: Marching ones: 30000000 33554432
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RAMTest: Marching zeroes: 30000000 33554432
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RAMTest: Pattern test: 30000000 33554432 55555555 aaaaaaaa
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RAMTest: Pattern test: 30000000 33554432 66666666 99999999
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RAMTest: Pattern test: 30000000 33554432 33333333 cccccccc
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RAMTest: Address-in-address test: 30000000 33554432
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4. This configuration has been used to test USB host functionaly. USB
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host is *not* enabled by default. If you will to enable USB host
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support in the NSH configuration, please modify the NuttX
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configuration as follows:
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@ -1,13 +1,11 @@
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/****************************************************************************
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* configs/ea3131/src/up_mem.c
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* arch/arm/src/board/up_mem.c
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* configs/olimex-lpc-h3131/src/lp31_mem.c
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*
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* Copyright (C) 2009-2010,2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - NXP lpc313x.cdl.drivers.zip example driver code
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* Based on the EA3131 SDRAM initialization logic with adjustments to the
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* timing parameters taken from Olimex LPC-H3131 sample code.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -65,25 +63,25 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* The MPMC delay based on trace lengths between SDRAM and the chip and on
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* the delay strategy used for SDRAM.
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/* My LPC-H3131 is fitted with a Samsung K4S561632J-UC/L75 256Mbit DRAM.
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* The FLASH organization is 16Mbit x 16
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*/
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/* Command, address, and data delay (DEL2) */
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#define H3131_MPMC_DELAY (0x00 << SYSCREG_MPMC_DELAYMODES_DEL1_SHIFT) | \
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#define H3131_MPMC_DELAY ((0x00 << SYSCREG_MPMC_DELAYMODES_DEL1_SHIFT) | \
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(0x20 << SYSCREG_MPMC_DELAYMODES_DEL2_SHIFT) | \
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(0x24 << SYSCREG_MPMC_DELAYMODES_DEL3_SHIFT);
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(0x24 << SYSCREG_MPMC_DELAYMODES_DEL3_SHIFT))
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/* Delay constants in nanosecondss for MT48LC32M16LF SDRAM on board */
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/* Delay constants in nanosecondss for K4S561632J-UC/L75 SDRAM on board */
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/* 90MHz SDRAM Clock */
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#define H3131_SDRAM_TRP (20) /* ns */
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#define H3131_SDRAM_TRFC (80) /* ns */
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#define H3131_SDRAM_TRAS (48) /* ns */
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#define H3131_SDRAM_TREX (80) /* ns */
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#define H3131_SDRAM_TAPR 2
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#define H3131_SDRAM_TAPR 2 /* clocks */
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#define H3131_SDRAM_TWR (15) /* ns */
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#define H3131_SDRAM_TRC (72) /* ns */
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#define H3131_SDRAM_TRRD (2) /* clocks */
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@ -111,7 +109,7 @@
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#endif
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#define NS2HCLKS(ns,hclk2,mask) (_NS2HCLKS & mask)
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#define NS2HCLKS(ns,hclk2,mask) (_NS2HCLKS(ns,hclk2) & mask)
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/****************************************************************************
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* Private Data
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@ -127,53 +125,12 @@
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* Description:
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* Configure SDRAM on the Olimex LPC-H3131 board
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*
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* Micron Initialization Sequence from their data sheet for the Micron
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* MT48LC32M16A2 32M x 16 SDRAM chip:
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*
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* "SDRAMs must be powered up and initialized in a predefined manner.
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* Operational procedures other than those specified may result in
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* undefined operation. Once power is applied to VDD and VDDQ
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* (simultaneously) and the clock is stable (stable clock is defined as
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* a signal cycling within timing constraints specified for the clock
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* pin), the SDRAM requires a 100µs delay prior to issuing any command
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* other than a COMMAND INHIBIT or NOP.
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*
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* "Starting at some point during this 100µs period and continuing at least
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* through the end of this period, COMMAND INHIBIT or NOP commands should
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* be applied. Once the 100µs delay has been satisfied with at least one
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* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
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* should be applied. All banks must then be precharged, thereby placing
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* the device in the all banks idle state.
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*
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* "Once in the idle state, two AUTO REFRESH cycles must be performed. After
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* the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
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* register programming.
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*
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* "Because the mode register will power up in an unknown state, it should
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* be loaded prior to applying any operational command."
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*
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* The JEDEC recommendation for initializing SDRAM is:
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*
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* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
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* Wait 200uS
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* PRECHARGE all
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* 8 AUTO REFRESH COMMANDS
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* LOAD MODE REGISTER
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* SDRAM is ready for operation
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*
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* The Micron SDRAM parts will work fine with the JEDEC sequence, but also
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* allow for a quicker init sequence of:
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*
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* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
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* Wait at least 100uS (during which time start applying and
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* continue applying NOP or COMMAND INHIBIT)
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* PRECHARGE all
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* 2 AUTO REFRESH COMMANDS (min requirement, more than 2 is also ok)
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* LOAD MODE REGISTER
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* SDRAM is ready for operation
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* My LPC-H3131 is fitted with a Samsung K4S561632J-UC/L75 256Mbit DRAM.
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* The FLASH organization is 16Mbit x 16
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*
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****************************************************************************/
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static inline void lpc31_sdraminitialize(void)
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{
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uint32_t tmp;
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uint32_t regval;
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@ -226,7 +183,7 @@
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putreg32(NS2HCLKS(H3131_SDRAM_TREX, HCLK2, MPMC_DYNTSREX_MASK),
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LPC31_MPMC_DYNTSREX);
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putreg32(H3131_SDRAM_TAPR, LPC31_MPMC_DYNTAPR);
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putreg32(((H3131_SDRAM_TDAL + _NS2HCLKS(H3131_SDRAM_TRP, HCLK2)) MPMC_DYNTDAL_MASK),
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putreg32(((H3131_SDRAM_TDAL + _NS2HCLKS(H3131_SDRAM_TRP, HCLK2)) & MPMC_DYNTDAL_MASK),
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LPC31_MPMC_DYNTDAL);
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putreg32(NS2HCLKS(H3131_SDRAM_TWR, HCLK2, MPMC_DYNTWR_MASK),
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LPC31_MPMC_DYNTWR);
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@ -273,6 +230,8 @@
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/* Recommended refresh interval for normal operation of the Micron
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* MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) =
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* refresh counter interval rate, (subtract one for safety margin).
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*
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* REVISIT: Is this okay for the Samsung part?
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*/
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putreg32(NS2HCLKS(H3131_SDRAM_OPERREFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK),
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@ -375,7 +334,7 @@ void lpc31_meminitialize(void)
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putreg32(H3131_MPMC_DELAY, LPC31_SYSCREG_MPMC_DELAYMODES);
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/* Configure Micron MT48LC32M16A2 SDRAM on the H3131 board */
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/* Configure Samsung K4S561632J-UC/L75 DRAM on the H3131 board */
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lpc31_sdraminitialize();
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}
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