sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

armv7-r: add VBAR cp15 opearation

Browse Source 
Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
ligd 2022-09-19 12:00:54 +08:00 committed by Xiang Xiao
parent 3477c347e8
commit 6903f02d41
2 changed files with 5 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/armv7-r/barriers.h
View File

@ -34,9 +34,11 @@
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define arm_nop(n) __asm__ __volatile__ ("nop\n")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
#define ARM_NOP() arm_nop(15)
#endif /* __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H */

3
arch/arm/src/armv7-r/cp15.h
View File

@ -142,6 +142,9 @@
#define CP15_PMINTENSET(r) _CP15(0, r, c9, c14, 1) /* Interrupt Enable Set Register */
#define CP15_PMINTENCLR(r) _CP15(0, r, c9, c14, 2) /* Interrupt Enable Clear Register */
#define CP15_VBAR(r) _CP15(0, r, c12, c0, 0) /* Vector Base Address Register */
#define CP15_MVBAR(r) _CP15(0, r, c12, c0, 1) /* Monitor Vector Base Address Register */
#define CP15_CONTEXTIDR(r) _CP15(0, r, c13, c0, 1) /* Context ID Register */
#define CP15_TPIDRURW(r) _CP15(0, r, c13, c0, 2) /* Software Thread ID Registers */
#define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3)