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stm32f0l0g0/hardware/stm32_spi.h: remove unused definitions

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raiden00pl 2022-07-20 16:37:37 +02:00 committed by Xiang Xiao
parent fc84813b0a
commit 69986fad84
1 changed files with 0 additions and 36 deletions
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36
arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h
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@ -96,42 +96,6 @@
# define STM32_SPI3_I2SPR (STM32_SPI3_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32_NSPI > 3
# define STM32_SPI4_CR1 (STM32_SPI4_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI4_CR2 (STM32_SPI4_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI4_SR (STM32_SPI4_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI4_DR (STM32_SPI4_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI4_CRCPR (STM32_SPI4_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI4_I2SPR (STM32_SPI4_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32_NSPI > 4
# define STM32_SPI5_CR1 (STM32_SPI5_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI5_CR2 (STM32_SPI5_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI5_SR (STM32_SPI5_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI5_DR (STM32_SPI5_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI5_CRCPR (STM32_SPI5_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI5_I2SPR (STM32_SPI5_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
#if STM32_NSPI > 5
# define STM32_SPI6_CR1 (STM32_SPI6_BASE + STM32_SPI_CR1_OFFSET)
# define STM32_SPI6_CR2 (STM32_SPI6_BASE + STM32_SPI_CR2_OFFSET)
# define STM32_SPI6_SR (STM32_SPI6_BASE + STM32_SPI_SR_OFFSET)
# define STM32_SPI6_DR (STM32_SPI6_BASE + STM32_SPI_DR_OFFSET)
# define STM32_SPI6_CRCPR (STM32_SPI6_BASE + STM32_SPI_CRCPR_OFFSET)
# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE + STM32_SPI_RXCRCR_OFFSET)
# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE + STM32_SPI_TXCRCR_OFFSET)
# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE + STM32_SPI_I2SCFGR_OFFSET)
# define STM32_SPI6_I2SPR (STM32_SPI6_BASE + STM32_SPI_I2SPR_OFFSET)
#endif
/* Register Bitfield Definitions ********************************************/
/* SPI Control Register 1 */