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STM32 SDIO DMA: Ignore DMA FIFO errors; these seem to be bogus. SD multiple block transfers result in CRC errors; avoid them by using smaller FTP buffer sizes

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4410 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-02-21 22:00:28 +00:00
parent 511aad8aba
commit 69b322f99a
3 changed files with 9 additions and 25 deletions
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6
arch/arm/src/stm32/stm32_dma.h
View File

@ -60,13 +60,13 @@
*/
#if defined(CONFIG_STM32_STM32F10XX)
# define DMA_STATUS_FEIF 0
# define DMA_STATUS_DMEIF 0
# define DMA_STATUS_FEIF 0 /* (Not available in F1) */
# define DMA_STATUS_DMEIF 0 /* (Not available in F1) */
# define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */
# define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */
# define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */
#elif defined(CONFIG_STM32_STM32F40XX)
# define DMA_STATUS_FEIF DMA_STREAM_FEIF_BIT /* Stream FIFO error */
# define DMA_STATUS_FEIF 0 /* Stream FIFO error (ignored) */
# define DMA_STATUS_DMEIF DMA_STREAM_DMEIF_BIT /* Stream direct mode error */
# define DMA_STATUS_TEIF DMA_STREAM_TEIF_BIT /* Stream Transfer Error */
# define DMA_STATUS_HTIF DMA_STREAM_HTIF_BIT /* Stream Half Transfer */

21
arch/arm/src/stm32/stm32_sdio.c
View File

@ -188,26 +188,7 @@
# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
/* STM32 F4 stream configuration register (SCR) settings.
*
* Hmmm... I see conflicting statements in the Reference Manual. In the DMA
* section it says:
* "Note: The Burst mode is allowed only when incremetation is enabled:
* – When the PINC bit is at ‘0’, the PBURST bits should also be cleared to ‘00’
* – When the MINC bit is at ‘0’, the MBURST bits should also be cleared to ‘00’."
*
* But in the SDIO section it says:
*
* "4. Configure the DMA2 as follows:
* ...
* c) Program DMA2_Stream3 or DMA2_Stream6 Channel4 control register
* (memory increment, not peripheral increment, peripheral and source
* width is word size).
* ...
* e) Configure the incremental burst transfer to 4 beats (at least from
* peripheral side)..."
*/
/* STM32 F4 stream configuration register (SCR) settings. */
#elif defined(CONFIG_STM32_STM32F40XX)
# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\

7
arch/arm/src/stm32/stm32f40xxx_dma.c
View File

@ -676,11 +676,14 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
* case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be
* generated when the stream is enabled, then the stream will be automatically
* disabled."
*
* NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems to
* be reported spuriously causing good transfers to be marked as failures.
*/
regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET);
regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK);
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS | DMA_SFCR_FEIE);
regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE);
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS);
dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval);
/* "Configure data transfer direction, circular mode, peripheral & memory