Back out the last STM32 DMA priority change. It is not necessary; just dropping the SD frequency was sufficient
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5021 42af7a65-404d-4744-a932-0658087f49c3
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@ -3151,3 +3151,6 @@
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frequency from 24 to 16 MHz. Apparently 24 MHz is too fast for the board.
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This (plus the change to the STM32 DMA (above) fixes SDIO DMA on the
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STM3240G-EVAL (and probably STM3220G-EVAL -- untested).
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* arch/arm/src/stm32/stm32f2xx_dma.c and stm32f4xx_dma.c: Backed out the
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DMA priority change just above. The reduced SD card frequency was
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necessary and sufficient to resolve the problem.
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@ -721,11 +721,11 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
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regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
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DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
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DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|DMA_SCR_PL_MASK|
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DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
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DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
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scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
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DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
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DMA_SCR_DBM|DMA_SCR_CIRC|DMA_SCR_PL_MASK|
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DMA_SCR_DBM|DMA_SCR_CIRC|
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DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
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regval |= scr;
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dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;
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@ -721,11 +721,11 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
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regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
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DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
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DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|DMA_SCR_PL_MASK|
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DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
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DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
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scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
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DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
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DMA_SCR_DBM|DMA_SCR_CIRC|DMA_SCR_PL_MASK|
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DMA_SCR_DBM|DMA_SCR_CIRC|
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DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
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regval |= scr;
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dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;
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