As promised, here's the patch that implements USDHC1 & 2 selection on the imxrt. If only one port is active (either 1 or 2) it will always be numbered as 0, if both are active then USDHC1 will be number 0, USDHC2 will be 1.
This commit is contained in:
Dave Marples
Gregory Nutt
parent
a94970c0df
commit
69e215e083
@ -141,6 +141,10 @@ config ARCH_FAMILY_IMXRT106x
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# Peripheral support
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config IMXRT_USDHC
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bool
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default n
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config IMXRT_HAVE_LPUART
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bool
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default n
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@ -391,12 +395,21 @@ config IMXRT_SNVS_HPRTC
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bool "HP RTC"
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default n
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config IMXRT_USDHC
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bool "USDHC"
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config IMXRT_USDHC1
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bool "USDHC1"
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default n
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select ARCH_HAVE_SDIO
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select IMXRT_USDHC
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---help---
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Support SD host controller
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Support USDHC host controller 1
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config IMXRT_USDHC2
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bool "USDHC2"
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default n
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select ARCH_HAVE_SDIO
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select IMXRT_USDHC
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---help---
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Support USDHC host controller 2
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endmenu # i.MX RT Peripheral Selection
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/imxrt/imxrt_usdhc.c
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* Dave Marples <dave@marples.net>
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*
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@ -77,15 +77,13 @@
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/* Configuration ************************************************************/
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/* Fixme: This is a temporary fix to default to how this worked before,
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* and still allow an override to 2 slots for testing.
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*
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* Once Dave changes this to be keyed off CONFIG_IMXRT_USDHC1 and 2
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* delete this.
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*/
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#if !defined(CONFIG_IMXRT_MAX_SDHCDEV_SLOTS)
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# define CONFIG_IMXRT_MAX_SDHCDEV_SLOTS 1
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#if ((defined(CONFIG_IMXRT_USDHC1) && !defined(CONFIG_IMXRT_USDHC2)) || \
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(defined(CONFIG_IMXRT_USDHC2) && !defined(CONFIG_IMXRT_USDHC1)))
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# define IMXRT_MAX_SDHC_DEV_SLOTS 1
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#elif (defined(CONFIG_IMXRT_USDHC1) && defined(CONFIG_IMXRT_USDHC2))
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# define IMXRT_MAX_SDHC_DEV_SLOTS 2
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#else
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#error Unrecognised number of SDHC slots
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#endif
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#if !defined(CONFIG_IMXRT_USDHC_DMA)
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@ -372,8 +370,9 @@ static void imxrt_callback(void *arg);
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* Private Data
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****************************************************************************/
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struct imxrt_dev_s g_sdhcdev[CONFIG_IMXRT_MAX_SDHCDEV_SLOTS] =
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struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] =
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{
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#ifdef CONFIG_IMXRT_USDHC1
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{
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.addr = IMXRT_USDHC1_BASE,
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.dev =
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@ -423,7 +422,9 @@ struct imxrt_dev_s g_sdhcdev[CONFIG_IMXRT_MAX_SDHCDEV_SLOTS] =
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#endif
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}
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},
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#if (CONFIG_IMXRT_MAX_SDHCDEV_SLOTS > 1)
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#endif
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#ifdef CONFIG_IMXRT_USDHC2
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{
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.addr = IMXRT_USDHC2_BASE,
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.dev =
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@ -1622,7 +1623,7 @@ static void imxrt_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
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* ORed in.
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*/
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regval = getreg32(priv->addr + IMXRT_USDHC_SYSCTL_OFFSET);
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regval = getreg32(priv->addr + IMXRT_USDHC_SYSCTL_OFFSET);
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regval &= ~(USDHC_SYSCTL_SDCLKFS_MASK | USDHC_SYSCTL_DVS_MASK);
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/* Select the new prescaler and divisor values based on the requested
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@ -2704,7 +2705,7 @@ static int imxrt_registercallback(FAR struct sdio_dev_s *dev,
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DEBUGASSERT(priv != NULL);
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priv->cbevents = 0;
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priv->cbarg = arg;
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priv->cbarg = arg;
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priv->callback = callback;
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return OK;
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}
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@ -2799,7 +2800,7 @@ static int imxrt_dmasendsetup(FAR struct sdio_dev_s *dev,
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/* Save the source buffer information for use by the interrupt handler */
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priv->buffer = (uint32_t *) buffer;
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priv->buffer = (uint32_t *) buffer;
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priv->remaining = buflen;
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/* Then set up the SDIO data path */
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@ -2953,7 +2954,7 @@ void imxrt_usdhc_set_sdio_card_isr(FAR struct sdio_dev_s *dev,
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* Initialize SDIO for operation.
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*
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* Input Parameters:
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* slotno - Not used.
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* slotno - Slot to be used
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*
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* Returned Value:
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* A reference to an SDIO interface structure.
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@ -2963,7 +2964,7 @@ void imxrt_usdhc_set_sdio_card_isr(FAR struct sdio_dev_s *dev,
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FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
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{
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DEBUGASSERT(slotno < CONFIG_IMXRT_MAX_SDHCDEV_SLOTS);
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DEBUGASSERT(slotno < IMXRT_MAX_SDHC_DEV_SLOTS);
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struct imxrt_dev_s *priv = &g_sdhcdev[slotno];
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/* Initialize the USDHC slot structure data structure
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@ -2980,17 +2981,19 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
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/* Create a watchdog timer */
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priv->waitwdog = wd_create(); DEBUGASSERT(priv->waitwdog);
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priv->waitwdog = wd_create();
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DEBUGASSERT(priv->waitwdog);
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/* Configure pins for 1 or 4-bit, wide-bus operation (the chip is
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* capable of 8-bit wide bus operation but D4-D7 are not configured). If
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* bus is multiplexed then there is a custom bus configuration utility
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* in the scope of the board support package.
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*/
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switch (priv->addr)
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{
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case IMXRT_USDHC1_BASE:
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/* Configure pins for 1 or 4-bit, wide-bus operation (the chip is
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* capable of 8-bit wide bus operation but D4-D7 are not configured). If
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* bus is multiplexed then there is a custom bus configuration utility
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* in the scope of the board support package.
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*/
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#ifndef CONFIG_SDIO_MUXBUS
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if (slotno == 0)
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{
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/* Data width 1, 4 */
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(void)imxrt_config_gpio(PIN_USDHC1_D0);
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@ -3002,7 +3005,6 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
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(void)imxrt_config_gpio(PIN_USDHC1_D2);
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(void)imxrt_config_gpio(PIN_USDHC1_D3);
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#endif
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/* Clocking and CMD pins (all data widths) */
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(void)imxrt_config_gpio(PIN_USDHC1_DCLK);
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@ -3013,39 +3015,26 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
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(void)imxrt_config_gpio(PIN_USDHC1_CD);
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#endif
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/* Reset the card and assure that it is in the initial, unconfigured
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* state.
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*/
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imxrt_clockall_usdhc1();
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imxrt_reset(&priv->dev);
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imxrt_showregs(priv, "After reset");
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}
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break;
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#if (CONFIG_IMXRT_MAX_SDHCDEV_SLOTS > 1)
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else if (slotno == 1)
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{
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case IMXRT_USDHC2_BASE:
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(void)imxrt_config_gpio(PIN_USDHC2_D0);
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(void)imxrt_config_gpio(PIN_USDHC2_D1);
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(void)imxrt_config_gpio(PIN_USDHC2_D2);
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(void)imxrt_config_gpio(PIN_USDHC2_D3);
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(void)imxrt_config_gpio(PIN_USDHC2_DCLK);
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(void)imxrt_config_gpio(PIN_USDHC2_CMD);
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/* Reset the card and assure that it is in the initial, unconfigured
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* state.
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*/
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imxrt_clockall_usdhc2();
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imxrt_reset(&priv->dev);
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imxrt_showregs(priv, "After reset");
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}
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#endif
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else
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{
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break;
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default:
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return NULL;
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}
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imxrt_reset(&priv->dev);
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imxrt_showregs(priv, "After reset");
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return &g_sdhcdev[slotno].dev;
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}
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