Note reserved bits in STM32 ADC
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/****************************************************************************************************
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* arch/arm/src/stm32/chip/stm32_adc.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011, 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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# define ADC_CR1_RES_8BIT (2 << ADC_CR1_RES_SHIFT) /* 11 ADCCLK cycles. For STM32L15XX: 9 ADCCLK cycles */
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# define ADC_CR1_RES_6BIT (3 << ADC_CR1_RES_SHIFT) /* 9 ADCCLK cycles. For STM32L15XX: 7 ADCCLK cycles */
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# define ADC_CR1_OVRIE (1 << 26) /* Bit 26: Overrun interrupt enable */
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# define ADC_CR1_RESERVED (0xfb3f0000)
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#endif
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/* ADC control register 2 */
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# define ADC_CR2_EXTEN_BOTH (3 << ADC_CR2_EXTEN_SHIFT) /* 11: Trigger detection on both the rising and falling edges */
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# define ADC_CR2_SWSTART (1 << 30) /* Bit 30: Start Conversion of regular channels */
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# define ADC_CR2_RESERVED (0x8080f0fc)
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#else
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# define ADC_CR2_JEXTSEL_SHIFT (12) /* Bits 12-14: External event select for injected group */
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# define ADC_CR2_JEXTSEL_MASK (7 << ADC_CR2_JEXTSEL_SHIFT)
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