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Fix wait loop and void cast (#24)

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* Simplify EINTR/ECANCEL error handling

1. Add semaphore uninterruptible wait function
2 .Replace semaphore wait loop with a single uninterruptible wait
3. Replace all sem_xxx to nxsem_xxx

* Unify the void cast usage

1. Remove void cast for function because many place ignore the returned value witout cast
2. Replace void cast for variable with UNUSED macro
This commit is contained in:
Xiang Xiao 2020-01-02 10:49:34 -06:00 committed by Gregory Nutt
parent 316675f4db
commit 6a3c2aded6
1602 changed files with 6311 additions and 10874 deletions
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4
arch/arm/src/a1x/a1x_irq.c
View File

@ -156,7 +156,7 @@ void up_irqinitialize(void)
{
putreg32(0x00000000, A1X_INTC_EN(i)); /* 0 disables corresponding interrupt */
putreg32(0xffffffff, A1X_INTC_MASK(i)); /* 1 masks corresponding interrupt */
(void)getreg32(A1X_INTC_IRQ_PEND(i)); /* Reading status clears pending interrupts */
getreg32(A1X_INTC_IRQ_PEND(i)); /* Reading status clears pending interrupts */
}
/* Set the interrupt base address to zero. We do not use the vectored
@ -178,7 +178,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
(void)up_irq_enable();
up_irq_enable();
#endif
a1x_dumpintc("initial", 0);

2
arch/arm/src/a1x/a1x_pio.c
View File

@ -163,7 +163,7 @@ static int a1x_pio_interrupt(int irq, void *context)
{
/* Yes.. dispatch the interrupt */
(void)arm_doirq(irq, regs);
arm_doirq(irq, regs);
}
irq++;

18
arch/arm/src/a1x/a1x_serial.c
View File

@ -1528,31 +1528,31 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
(void)uart_register("/dev/ttyS3", &TTYS3_DEV);
uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
(void)uart_register("/dev/ttyS4", &TTYS4_DEV);
uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
(void)uart_register("/dev/ttyS5", &TTYS5_DEV);
uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
#ifdef TTYS6_DEV
(void)uart_register("/dev/ttyS6", &TTYS6_DEV);
uart_register("/dev/ttyS6", &TTYS6_DEV);
#endif
#ifdef TTYS7_DEV
(void)uart_register("/dev/ttyS7", &TTYS7_DEV);
uart_register("/dev/ttyS7", &TTYS7_DEV);
#endif
}

2
arch/arm/src/a1x/a1x_timerisr.c
View File

@ -138,7 +138,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL);
irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL);
/* Enable interrupts from the TIMER 0 port */

8
arch/arm/src/am335x/am335x_gpioirq.c
View File

@ -259,7 +259,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO0 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO0A, am335x_gpio0_interrupt, NULL);
irq_attach(AM335X_IRQ_GPIO0A, am335x_gpio0_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO0A);
#endif
@ -284,7 +284,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO1 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO1A, am335x_gpio1_interrupt, NULL);
irq_attach(AM335X_IRQ_GPIO1A, am335x_gpio1_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO1A);
#endif
@ -309,7 +309,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO2 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO2A, am335x_gpio2_interrupt, NULL);
irq_attach(AM335X_IRQ_GPIO2A, am335x_gpio2_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO2A);
#endif
@ -334,7 +334,7 @@ void am335x_gpio_irqinitialize(void)
/* Attach and enable the GPIO3 IRQ */
(void)irq_attach(AM335X_IRQ_GPIO3A, am335x_gpio3_interrupt, NULL);
irq_attach(AM335X_IRQ_GPIO3A, am335x_gpio3_interrupt, NULL);
up_enable_irq(AM335X_IRQ_GPIO3A);
#endif
}

6
arch/arm/src/am335x/am335x_irq.c
View File

@ -131,8 +131,8 @@ void up_irqinitialize(void)
for (i = 0; i < AM335X_IRQ_NINT; i += 32)
{
putreg32(0xffffffff, AM335X_INTC_MIR_SET(i)); /* 1 masks corresponding interrupt */
(void)getreg32(AM335X_INTC_PEND_IRQ(i)); /* Reading status clears pending interrupts */
(void)getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */
getreg32(AM335X_INTC_PEND_IRQ(i)); /* Reading status clears pending interrupts */
getreg32(AM335X_INTC_PEND_FIQ(i)); /* Reading status clears pending interrupts */
}
/* currents_regs is non-NULL only while processing an interrupt */
@ -150,7 +150,7 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
(void)up_irq_enable();
up_irq_enable();
#endif
}

2
arch/arm/src/am335x/am335x_lcdc.c
View File

@ -585,7 +585,7 @@ int am335x_lcd_initialize(FAR const struct am335x_panel_info_s *panel)
/* Initialize the device state singleton */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
memcpy(&priv->panel, panel, sizeof(struct am335x_panel_info_s));
/* Save framebuffer information */

14
arch/arm/src/am335x/am335x_serial.c
View File

@ -1347,25 +1347,25 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
(void)uart_register("/dev/ttyS3", &TTYS3_DEV);
uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
(void)uart_register("/dev/ttyS4", &TTYS4_DEV);
uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
#ifdef TTYS5_DEV
(void)uart_register("/dev/ttyS5", &TTYS5_DEV);
uart_register("/dev/ttyS5", &TTYS5_DEV);
#endif
}

4
arch/arm/src/am335x/am335x_timerisr.c
View File

@ -154,7 +154,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(AM335X_IRQ_TIMER1_1MS, (xcpt_t)am335x_timerisr, NULL);
irq_attach(AM335X_IRQ_TIMER1_1MS, (xcpt_t)am335x_timerisr, NULL);
/* Clear interrupt status */
@ -193,7 +193,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(AM335X_IRQ_TIMER2, (xcpt_t)am335x_timerisr, NULL);
irq_attach(AM335X_IRQ_TIMER2, (xcpt_t)am335x_timerisr, NULL);
/* Enable overflow interrupt */

10
arch/arm/src/arm/up_assert.c
View File

@ -290,7 +290,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@ -306,13 +306,13 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
(void)syslog_flush();
syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || running_task()->flink == NULL)
{
(void)up_irq_save();
up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@ -353,7 +353,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
(void)syslog_flush();
syslog_flush();
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
@ -367,7 +367,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);

2
arch/arm/src/arm/up_blocktask.c
View File

@ -161,7 +161,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Reset scheduler parameters */

2
arch/arm/src/arm/up_doirq.c
View File

@ -119,7 +119,7 @@ void up_doirq(int irq, uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(NULL);
group_addrenv(NULL);
#endif
}
#endif

2
arch/arm/src/arm/up_releasepending.c
View File

@ -130,7 +130,7 @@ void up_release_pending(void)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

2
arch/arm/src/arm/up_reprioritizertr.c
View File

@ -183,7 +183,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

2
arch/arm/src/arm/up_sigdeliver.c
View File

@ -107,7 +107,7 @@ void up_sigdeliver(void)
*/
sinfo("Resuming\n");
(void)up_irq_save();
up_irq_save();
rtcb->pterrno = saved_errno;
/* Modify the saved return state with the actual saved values in the

2
arch/arm/src/arm/up_unblocktask.c
View File

@ -145,7 +145,7 @@ void up_unblock_task(struct tcb_s *tcb)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

10
arch/arm/src/armv6-m/up_assert.c
View File

@ -347,7 +347,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@ -363,13 +363,13 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
(void)syslog_flush();
syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || running_task()->flink == NULL)
{
(void)up_irq_save();
up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@ -410,7 +410,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
(void)syslog_flush();
syslog_flush();
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
@ -424,7 +424,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);

2
arch/arm/src/armv6-m/up_hardfault.c
View File

@ -134,7 +134,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
getprimask(), getipsr());
#endif
(void)up_irq_save();
up_irq_save();
hfalert("PANIC!!! Hard fault\n");
PANIC();
return OK; /* Won't get here */

2
arch/arm/src/armv6-m/up_sigdeliver.c
View File

@ -111,7 +111,7 @@ void up_sigdeliver(void)
*/
sinfo("Resuming\n");
(void)up_irq_save();
up_irq_save();
rtcb->pterrno = saved_errno;
/* Modify the saved return state with the actual saved values in the

4
arch/arm/src/armv6-m/up_signal_dispatch.c
View File

@ -84,8 +84,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Let sys_call4() do all of the work */
(void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
}
#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL) && !CONFIG_DISABLE_PTHREAD */

12
arch/arm/src/armv7-a/arm_assert.c
View File

@ -375,7 +375,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@ -391,7 +391,7 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
(void)syslog_flush();
syslog_flush();
/* Are we in an interrupt handler or the idle task? */
@ -399,14 +399,14 @@ static void _up_assert(int errorcode)
{
/* Disable interrupts on this CPU */
(void)up_irq_save();
up_irq_save();
for (; ; )
{
#ifdef CONFIG_SMP
/* Try (again) to stop activity on other CPUs */
(void)spin_trylock(&g_cpu_irqlock);
spin_trylock(&g_cpu_irqlock);
#endif
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@ -449,7 +449,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_SMP
#if CONFIG_TASK_NAME_SIZE > 0
@ -473,7 +473,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);

2
arch/arm/src/armv7-a/arm_blocktask.c
View File

@ -182,7 +182,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Reset scheduler parameters */

2
arch/arm/src/armv7-a/arm_doirq.c
View File

@ -118,7 +118,7 @@ static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(NULL);
group_addrenv(NULL);
#endif
}
#endif

2
arch/arm/src/armv7-a/arm_pgalloc.c
View File

@ -163,7 +163,7 @@ static int get_pgtable(FAR group_addrenv_t *addrenv, uintptr_t vaddr)
/* And instantiate the modified environment */
(void)up_addrenv_select(addrenv, NULL);
up_addrenv_select(addrenv, NULL);
}
}

2
arch/arm/src/armv7-a/arm_releasepending.c
View File

@ -150,7 +150,7 @@ void up_release_pending(void)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

2
arch/arm/src/armv7-a/arm_reprioritizertr.c
View File

@ -204,7 +204,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

6
arch/arm/src/armv7-a/arm_sigdeliver.c
View File

@ -152,9 +152,9 @@ void up_sigdeliver(void)
*/
#ifdef CONFIG_SMP
(void)enter_critical_section();
enter_critical_section();
#else
(void)up_irq_save();
up_irq_save();
#endif
/* Restore the saved errno value */
@ -187,7 +187,7 @@ void up_sigdeliver(void)
DEBUGASSERT(rtcb->irqcount == 1);
while (rtcb->irqcount < saved_irqcount)
{
(void)enter_critical_section();
enter_critical_section();
}
#endif

4
arch/arm/src/armv7-a/arm_signal_dispatch.c
View File

@ -93,8 +93,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Yes.. Let sys_call4() do all of the work to get us into user space */
(void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
}
else
{

2
arch/arm/src/armv7-a/arm_unblocktask.c
View File

@ -166,7 +166,7 @@ void up_unblock_task(struct tcb_s *tcb)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

12
arch/arm/src/armv7-m/up_assert.c
View File

@ -369,7 +369,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@ -385,19 +385,19 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
(void)syslog_flush();
syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || (running_task())->flink == NULL)
{
(void)up_irq_save();
up_irq_save();
for (; ; )
{
#ifdef CONFIG_SMP
/* Try (again) to stop activity on other CPUs */
(void)spin_trylock(&g_cpu_irqlock);
spin_trylock(&g_cpu_irqlock);
#endif
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@ -438,7 +438,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_SMP
#if CONFIG_TASK_NAME_SIZE > 0
@ -462,7 +462,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);

2
arch/arm/src/armv7-m/up_hardfault.c
View File

@ -143,7 +143,7 @@ int up_hardfault(int irq, FAR void *context, FAR void *arg)
getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
getreg32(NVIC_AFAULTS));
(void)up_irq_save();
up_irq_save();
_alert("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
PANIC();
return OK;

2
arch/arm/src/armv7-m/up_itm_syslog.c
View File

@ -186,7 +186,7 @@ void itm_syslog_initialize(void)
/* Setup the SYSLOG channel */
(void)syslog_channel(&g_itm_channel);
syslog_channel(&g_itm_channel);
}
#endif /* CONFIG_ARMV7M_ITMSYSLOG */

2
arch/arm/src/armv7-m/up_memfault.c
View File

@ -79,7 +79,7 @@ int up_memfault(int irq, FAR void *context, FAR void *arg)
{
/* Dump some memory management fault info */
(void)up_irq_save();
up_irq_save();
_alert("PANIC!!! Memory Management Fault:\n");
mfinfo(" IRQ: %d context: %p\n", irq, context);
_alert(" CFAULTS: %08x MMFAR: %08x\n",

6
arch/arm/src/armv7-m/up_sigdeliver.c
View File

@ -156,9 +156,9 @@ void up_sigdeliver(void)
*/
#ifdef CONFIG_SMP
(void)enter_critical_section();
enter_critical_section();
#else
(void)up_irq_save();
up_irq_save();
#endif
/* Restore the saved errno value */
@ -199,7 +199,7 @@ void up_sigdeliver(void)
DEBUGASSERT(rtcb->irqcount == 1);
while (rtcb->irqcount < saved_irqcount)
{
(void)enter_critical_section();
enter_critical_section();
}
#endif

4
arch/arm/src/armv7-m/up_signal_dispatch.c
View File

@ -84,8 +84,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Let sys_call4() do all of the work */
(void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
}
#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL) && !CONFIG_DISABLE_PTHREAD */

10
arch/arm/src/armv7-r/arm_assert.c
View File

@ -354,7 +354,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_ARCH_USBDUMP
/* Dump USB trace data */
(void)usbtrace_enumerate(assert_tracecallback, NULL);
usbtrace_enumerate(assert_tracecallback, NULL);
#endif
}
#else
@ -370,13 +370,13 @@ static void _up_assert(int errorcode)
{
/* Flush any buffered SYSLOG data */
(void)syslog_flush();
syslog_flush();
/* Are we in an interrupt handler or the idle task? */
if (CURRENT_REGS || (running_task())->flink == NULL)
{
(void)up_irq_save();
up_irq_save();
for (; ; )
{
#if CONFIG_BOARD_RESET_ON_ASSERT >= 1
@ -417,7 +417,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (prior to the assertion) */
(void)syslog_flush();
syslog_flush();
#if CONFIG_TASK_NAME_SIZE > 0
_alert("Assertion failed at file:%s line: %d task: %s\n",
@ -431,7 +431,7 @@ void up_assert(const uint8_t *filename, int lineno)
/* Flush any buffered SYSLOG data (from the above) */
(void)syslog_flush();
syslog_flush();
#ifdef CONFIG_BOARD_CRASHDUMP
board_crashdump(up_getsp(), running_task(), filename, lineno);

2
arch/arm/src/armv7-r/arm_sigdeliver.c
View File

@ -106,7 +106,7 @@ void up_sigdeliver(void)
*/
sinfo("Resuming\n");
(void)up_irq_save();
up_irq_save();
rtcb->pterrno = saved_errno;
/* Modify the saved return state with the actual saved values in the

4
arch/arm/src/armv7-r/arm_signal_dispatch.c
View File

@ -93,8 +93,8 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
{
/* Yes.. Let sys_call4() do all of the work to get us into user space */
(void)sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
sys_call4(SYS_signal_handler, (uintptr_t)sighand, (uintptr_t)signo,
(uintptr_t)info, (uintptr_t)ucontext);
}
else
{

22
arch/arm/src/c5471/c5471_ethernet.c
View File

@ -989,8 +989,8 @@ static int c5471_transmit(struct c5471_driver_s *priv)
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
(void)wd_start(priv->c_txtimeout, C5471_TXTIMEOUT,
c5471_txtimeout_expiry, 1, (wdparm_t)priv);
wd_start(priv->c_txtimeout, C5471_TXTIMEOUT,
c5471_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@ -1539,7 +1539,7 @@ static void c5471_txdone(struct c5471_driver_s *priv)
/* Then poll the network for new XMIT data */
(void)devif_poll(&priv->c_dev, c5471_txpoll);
devif_poll(&priv->c_dev, c5471_txpoll);
}
/****************************************************************************
@ -1707,7 +1707,7 @@ static void c5471_txtimeout_work(FAR void *arg)
/* Then poll the network for new XMIT data */
(void)devif_poll(&priv->c_dev, c5471_txpoll);
devif_poll(&priv->c_dev, c5471_txpoll);
net_unlock();
}
@ -1778,13 +1778,13 @@ static void c5471_poll_work(FAR void *arg)
{
/* If so, update TCP timing states and poll the network for new XMIT data */
(void)devif_timer(&priv->c_dev, C5471_WDDELAY, c5471_txpoll);
devif_timer(&priv->c_dev, C5471_WDDELAY, c5471_txpoll);
}
/* Setup the watchdog poll timer again */
(void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
(wdparm_t)priv);
wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
(wdparm_t)priv);
net_unlock();
}
@ -1870,8 +1870,8 @@ static int c5471_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
(void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
1, (wdparm_t)priv);
wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
@ -1969,7 +1969,7 @@ static void c5471_txavail_work(FAR void *arg)
{
/* If so, then poll the network for new XMIT data */
(void)devif_poll(&priv->c_dev, c5471_txpoll);
devif_poll(&priv->c_dev, c5471_txpoll);
}
}
@ -2458,7 +2458,7 @@ void up_netinitialize(void)
/* Register the device with the OS so that socket IOCTLs can be performed */
(void)netdev_register(&g_c5471[0].c_dev, NET_LL_ETHERNET);
netdev_register(&g_c5471[0].c_dev, NET_LL_ETHERNET);
}
#endif /* CONFIG_NET */

6
arch/arm/src/c5471/c5471_serial.c
View File

@ -823,9 +823,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
(void)uart_register("/dev/console", &CONSOLE_DEV);
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************

6
arch/arm/src/common/up_exit.c
View File

@ -148,7 +148,7 @@ void _exit(int status)
* The IRQ state will be restored when the next task is started.
*/
(void)enter_critical_section();
enter_critical_section();
sinfo("TCB=%p exiting\n", tcb);
@ -163,7 +163,7 @@ void _exit(int status)
/* Destroy the task at the head of the ready to run list. */
(void)nxtask_exit();
nxtask_exit();
/* Now, perform the context switch to the new ready-to-run task at the
* head of the list.
@ -178,7 +178,7 @@ void _exit(int status)
* the ready-to-run list.
*/
(void)group_addrenv(tcb);
group_addrenv(tcb);
#endif
/* Reset scheduler parameters */

8
arch/arm/src/common/up_initialize.c
View File

@ -221,7 +221,7 @@ void up_initialize(void)
#ifdef CONFIG_PSEUDOTERM_SUSV1
/* Register the master pseudo-terminal multiplexor device */
(void)ptmx_register();
ptmx_register();
#endif
/* Early initialization of the system logging device. Some SYSLOG channel
@ -250,19 +250,19 @@ void up_initialize(void)
#ifdef CONFIG_NETDEV_LOOPBACK
/* Initialize the local loopback device */
(void)localhost_initialize();
localhost_initialize();
#endif
#ifdef CONFIG_NET_TUN
/* Initialize the TUN device */
(void)tun_initialize();
tun_initialize();
#endif
#ifdef CONFIG_NETDEV_TELNET
/* Initialize the Telnet session factory */
(void)telnet_initialize();
telnet_initialize();
#endif
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)

2
arch/arm/src/common/up_lwl_console.c
View File

@ -323,5 +323,5 @@ static ssize_t lwlconsole_write(struct file *filep, const char *buffer,
void lwlconsole_init(void)
{
g_d.upword = 0;
(void)register_driver("/dev/console", &g_consoleops, 0666, NULL);
register_driver("/dev/console", &g_consoleops, 0666, NULL);
}

10
arch/arm/src/cxd56xx/cxd56_adc.c
View File

@ -585,7 +585,7 @@ static int adc_stop(adc_ch_t ch, FAR struct seq_s *seq)
return OK;
}
(void) seq_ioctl(seq, 0, SCUIOC_STOP, 0);
seq_ioctl(seq, 0, SCUIOC_STOP, 0);
if (ch <= CH3)
{
@ -1006,11 +1006,7 @@ void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust)
int cxd56_adcinitialize(void)
{
int ret;
/* Avoid warnings when no ADC options enabled */
(void) ret;
int ret = OK;
#if defined (CONFIG_CXD56_LPADC0) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc0", &g_adcops, 0666, &g_lpadc0priv);
@ -1061,5 +1057,5 @@ int cxd56_adcinitialize(void)
}
#endif
return OK;
return ret;
}

9
arch/arm/src/cxd56xx/cxd56_charger.c
View File

@ -477,7 +477,7 @@ static int charger_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
FAR struct charger_dev_s *priv = inode->i_private;
int ret = -ENOTTY;
sem_wait(&priv->batsem);
nxsem_wait(&priv->batsem);
switch (cmd)
{
@ -621,7 +621,7 @@ static int charger_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
}
sem_post(&priv->batsem);
nxsem_post(&priv->batsem);
return ret;
}
@ -650,7 +650,7 @@ int cxd56_charger_initialize(FAR const char *devpath)
/* Initialize the CXD5247 device structure */
sem_init(&priv->batsem, 0, 1);
nxsem_init(&priv->batsem, 0, 1);
/* Register battery driver */
@ -680,8 +680,7 @@ int cxd56_charger_initialize(FAR const char *devpath)
int cxd56_charger_uninitialize(FAR const char *devpath)
{
(void) unregister_driver(devpath);
unregister_driver(devpath);
return OK;
}

4
arch/arm/src/cxd56xx/cxd56_clock.c
View File

@ -235,7 +235,7 @@ static void clock_semtake(sem_t *id)
{
if (!up_interrupt_context())
{
sem_wait(id);
nxsem_wait(id);
}
}
@ -243,7 +243,7 @@ static void clock_semgive(sem_t *id)
{
if (!up_interrupt_context())
{
sem_post(id);
nxsem_post(id);
}
}

2
arch/arm/src/cxd56xx/cxd56_cpuidlestack.c
View File

@ -98,7 +98,7 @@
int up_cpu_idlestack(int cpu, FAR struct tcb_s *tcb, size_t stack_size)
{
#if CONFIG_SMP_NCPUS > 1
(void)up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL);
#endif
return OK;
}

2
arch/arm/src/cxd56xx/cxd56_cpustart.c
View File

@ -137,7 +137,7 @@ static void appdsp_boot(void)
/* Then transfer control to the IDLE task */
(void)nx_idle_task(0, NULL);
nx_idle_task(0, NULL);
}
/****************************************************************************

12
arch/arm/src/cxd56xx/cxd56_dmac.c
View File

@ -677,7 +677,7 @@ void weak_function up_dma_initialize(void)
g_dmach[i].chan = i;
}
sem_init(&g_dmaexc, 0, 1);
nxsem_init(&g_dmaexc, 0, 1);
}
/****************************************************************************
@ -711,7 +711,7 @@ DMA_HANDLE cxd56_dmachannel(int ch, ssize_t maxsize)
/* Get exclusive access to allocate channel */
sem_wait(&g_dmaexc);
nxsem_wait(&g_dmaexc);
if (ch < 0 || ch >= NCHANNELS)
{
@ -754,12 +754,12 @@ DMA_HANDLE cxd56_dmachannel(int ch, ssize_t maxsize)
dmach->inuse = true;
sem_post(&g_dmaexc);
nxsem_post(&g_dmaexc);
return (DMA_HANDLE)dmach;
err:
sem_post(&g_dmaexc);
nxsem_post(&g_dmaexc);
return NULL;
}
@ -793,7 +793,7 @@ void cxd56_dmafree(DMA_HANDLE handle)
return;
}
sem_wait(&g_dmaexc);
nxsem_wait(&g_dmaexc);
if (!dmach->inuse)
{
@ -811,7 +811,7 @@ void cxd56_dmafree(DMA_HANDLE handle)
dmach->inuse = false;
err:
sem_post(&g_dmaexc);
nxsem_post(&g_dmaexc);
}
/****************************************************************************

11
arch/arm/src/cxd56xx/cxd56_emmc.c
View File

@ -132,15 +132,12 @@ struct cxd56_emmc_state_s g_emmcdev;
static void emmc_takesem(FAR sem_t *sem)
{
while (sem_wait(sem) != 0)
{
ASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(sem);
}
static void emmc_givesem(FAR sem_t *sem)
{
sem_post(sem);
nxsem_post(sem);
}
static void emmc_cmdstarted(void)
@ -908,8 +905,8 @@ int cxd56_emmcinitialize(void)
priv = &g_emmcdev;
memset(priv, 0, sizeof(struct cxd56_emmc_state_s));
sem_init(&priv->excsem, 0, 1);
sem_init(&g_waitsem, 0, 0);
nxsem_init(&priv->excsem, 0, 1);
nxsem_init(&g_waitsem, 0, 0);
ret = emmc_hwinitialize();
if (ret != OK)

14
arch/arm/src/cxd56xx/cxd56_farapi.c
View File

@ -139,11 +139,7 @@ static struct pm_cpu_wakelock_s g_wlock = {
static int farapi_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
return nxsem_wait_uninterruptible(id);
}
#ifdef CONFIG_CXD56_FARAPI_DEBUG
@ -188,7 +184,7 @@ static int cxd56_farapidonehandler(int cpuid, int protoid,
/* Send event flag response */
cxd56_sendmsg(cpuid, CXD56_PROTO_FLG, 5, pdata & 0xff00, 0);
sem_post(&g_farwait);
nxsem_post(&g_farwait);
}
return OK;
@ -258,7 +254,7 @@ void farapi_main(int id, void *arg, struct modulelist_s *mlist)
dump_farapi_message(&msg);
err:
sem_post(&g_farlock);
nxsem_post(&g_farlock);
}
void cxd56_farapiinitialize(void)
@ -274,8 +270,8 @@ void cxd56_farapiinitialize(void)
# endif
}
#endif
sem_init(&g_farlock, 0, 1);
sem_init(&g_farwait, 0, 0);
nxsem_init(&g_farlock, 0, 1);
nxsem_init(&g_farwait, 0, 0);
cxd56_iccinit(CXD56_PROTO_MBX);
cxd56_iccinit(CXD56_PROTO_FLG);

9
arch/arm/src/cxd56xx/cxd56_gauge.c
View File

@ -334,7 +334,7 @@ static int gauge_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
FAR struct bat_gauge_dev_s *priv = inode->i_private;
int ret = -ENOTTY;
sem_wait(&priv->batsem);
nxsem_wait(&priv->batsem);
switch (cmd)
{
@ -372,7 +372,7 @@ static int gauge_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
break;
}
sem_post(&priv->batsem);
nxsem_post(&priv->batsem);
return ret;
}
@ -402,7 +402,7 @@ int cxd56_gauge_initialize(FAR const char *devpath)
/* Initialize the CXD5247 device structure */
sem_init(&priv->batsem, 0, 1);
nxsem_init(&priv->batsem, 0, 1);
/* Register battery driver */
@ -432,8 +432,7 @@ int cxd56_gauge_initialize(FAR const char *devpath)
int cxd56_gauge_uninitialize(FAR const char *devpath)
{
(void) unregister_driver(devpath);
unregister_driver(devpath);
return OK;
}

18
arch/arm/src/cxd56xx/cxd56_ge2d.c
View File

@ -98,11 +98,7 @@ static sem_t g_lock;
static int ge2d_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
return nxsem_wait_uninterruptible(id);
}
/****************************************************************************
@ -111,7 +107,7 @@ static int ge2d_semtake(sem_t *id)
static void ge2d_semgive(sem_t *id)
{
sem_post(id);
nxsem_post(id);
}
/****************************************************************************
@ -243,9 +239,9 @@ int cxd56_ge2dinitialize(FAR const char *devname)
{
int ret;
sem_init(&g_lock, 0, 1);
sem_init(&g_wait, 0, 0);
sem_setprotocol(&g_wait, SEM_PRIO_NONE);
nxsem_init(&g_lock, 0, 1);
nxsem_init(&g_wait, 0, 0);
nxsem_setprotocol(&g_wait, SEM_PRIO_NONE);
ret = register_driver(devname, &g_ge2dfops, 0666, NULL);
if (ret != 0)
@ -276,8 +272,8 @@ void cxd56_ge2duninitialize(FAR const char *devname)
cxd56_img_ge2d_clock_disable();
sem_destroy(&g_lock);
sem_destroy(&g_wait);
nxsem_destroy(&g_lock);
nxsem_destroy(&g_wait);
unregister_driver(devname);
}

12
arch/arm/src/cxd56xx/cxd56_geofence.c
View File

@ -445,7 +445,7 @@ static void cxd56_geofence_sighandler(uint32_t data, FAR void *userdata)
int i;
int ret;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return;
@ -458,11 +458,11 @@ static void cxd56_geofence_sighandler(uint32_t data, FAR void *userdata)
{
fds->revents |= POLLIN;
gnssinfo("Report events: %02x\n", fds->revents);
sem_post(fds->sem);
nxsem_post(fds->sem);
}
}
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
}
/****************************************************************************
@ -624,7 +624,7 @@ static int cxd56_geofence_poll(FAR struct file *filep, FAR struct pollfd *fds,
inode = filep->f_inode;
priv = (FAR struct cxd56_geofence_dev_s *)inode->i_private;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@ -675,7 +675,7 @@ static int cxd56_geofence_poll(FAR struct file *filep, FAR struct pollfd *fds,
}
errout:
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
return ret;
}
#endif
@ -708,7 +708,7 @@ static int cxd56_geofence_register(FAR const char *devpath)
}
memset(priv, 0, sizeof(struct cxd56_geofence_dev_s));
sem_init(&priv->devsem, 0, 1);
nxsem_init(&priv->devsem, 0, 1);
ret = cxd56_geofence_initialize(priv);
if (ret < 0)

57
arch/arm/src/cxd56xx/cxd56_gnss.c
View File

@ -1443,7 +1443,7 @@ static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg)
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@ -1491,7 +1491,7 @@ static int cxd56_gnss_set_signal(FAR struct file *filep, unsigned long arg)
_success:
_err:
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
#endif /* if !defined(CONFIG_DISABLE_SIGNAL) && \
(CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0) */
return ret;
@ -1949,7 +1949,7 @@ static int cxd56_gnss_wait_notify(FAR sem_t *sem, time_t waitsec)
timeout.tv_sec += waitsec; /* <waitsec> seconds timeout for wait */
return sem_timedwait(sem, &timeout);
return nxsem_timedwait(sem, &timeout);
}
/****************************************************************************
@ -2110,7 +2110,7 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata)
int i;
int ret;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return;
@ -2124,9 +2124,9 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata)
#ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_ptr = &sig->info;
(void)sigqueue(sig->pid, sig->info.signo, value);
sigqueue(sig->pid, sig->info.signo, value);
#else
(void)sigqueue(sig->pid, sig->info.signo, &sig->info);
sigqueue(sig->pid, sig->info.signo, &sig->info);
#endif
issetmask = 1;
}
@ -2137,7 +2137,7 @@ static void cxd56_gnss_common_signalhandler(uint32_t data, FAR void *userdata)
GD_SetNotifyMask(sigtype, FALSE);
}
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
}
#endif /* if !defined(CONFIG_DISABLE_SIGNAL) && \
@ -2192,7 +2192,7 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata)
*/
priv->notify_data = dtype;
sem_post(&priv->syncsem);
nxsem_post(&priv->syncsem);
}
return;
@ -2220,7 +2220,7 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata)
break;
}
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return;
@ -2233,11 +2233,11 @@ static void cxd56_gnss_default_sighandler(uint32_t data, FAR void *userdata)
{
fds->revents |= POLLIN;
gnssinfo("Report events: %02x\n", fds->revents);
sem_post(fds->sem);
nxsem_post(fds->sem);
}
}
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
#if !defined(CONFIG_DISABLE_SIGNAL) && \
(CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0)
@ -2267,7 +2267,7 @@ static void cxd56_gnss_cpufifoapi_signalhandler(uint32_t data,
FAR struct cxd56_gnss_dev_s *priv = (FAR struct cxd56_gnss_dev_s *)userdata;
priv->apiret = CXD56_CPU1_GET_DATA((int)data);
sem_post(&priv->apiwait);
nxsem_post(&priv->apiwait);
return;
}
@ -2302,15 +2302,14 @@ static int cxd56_gnss_cpufifo_api(FAR struct file *filep, unsigned int api,
type = CXD56_GNSS_CPUFIFOAPI_SET_DATA(api, data);
cxd56_cpu1sigsend(CXD56_CPU1_DATA_TYPE_CPUFIFOAPI, type);
ret = sem_wait(&priv->apiwait);
ret = nxsem_wait(&priv->apiwait);
if (ret < 0)
{
/* If sem_wait returns -EINTR, there is a possibility that the signal
/* If nxsem_wait returns -EINTR, there is a possibility that the signal
* for GNSS set with CXD56_GNSS_IOCTL_SIGNAL_SET is unmasked
* by SIG_UNMASK in the signal mask.
*/
ret = -errno;
_warn("Cannot wait GNSS semaphore %d\n", ret);
goto _err;
}
@ -2438,7 +2437,7 @@ static int cxd56_gnss_open(FAR struct file *filep)
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@ -2446,7 +2445,7 @@ static int cxd56_gnss_open(FAR struct file *filep)
if (priv->num_open == 0)
{
ret = sem_init(&priv->syncsem, 0, 0);
ret = nxsem_init(&priv->syncsem, 0, 0);
if (ret < 0)
{
goto _err0;
@ -2485,7 +2484,7 @@ static int cxd56_gnss_open(FAR struct file *filep)
goto _err2;
}
sem_destroy(&priv->syncsem);
nxsem_destroy(&priv->syncsem);
}
priv->num_open++;
@ -2497,10 +2496,10 @@ _err2:
#endif
PM_SleepCpu(CXD56_GNSS_GPS_CPUID, PM_SLEEP_MODE_COLD);
_err1:
sem_destroy(&priv->syncsem);
nxsem_destroy(&priv->syncsem);
_err0:
_success:
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
return ret;
}
@ -2527,7 +2526,7 @@ static int cxd56_gnss_close(FAR struct file *filep)
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@ -2548,7 +2547,7 @@ static int cxd56_gnss_close(FAR struct file *filep)
}
errout:
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
return ret;
}
@ -2674,7 +2673,7 @@ static int cxd56_gnss_ioctl(FAR struct file *filep, int cmd,
return -EINVAL;
}
ret = sem_wait(&priv->ioctllock);
ret = nxsem_wait(&priv->ioctllock);
if (ret < 0)
{
return ret;
@ -2682,7 +2681,7 @@ static int cxd56_gnss_ioctl(FAR struct file *filep, int cmd,
ret = g_cmdlist[cmd](filep, arg);
sem_post(&priv->ioctllock);
nxsem_post(&priv->ioctllock);
return ret;
}
@ -2715,7 +2714,7 @@ static int cxd56_gnss_poll(FAR struct file *filep, FAR struct pollfd *fds,
inode = filep->f_inode;
priv = (FAR struct cxd56_gnss_dev_s *)inode->i_private;
ret = sem_wait(&priv->devsem);
ret = nxsem_wait(&priv->devsem);
if (ret < 0)
{
return ret;
@ -2766,7 +2765,7 @@ static int cxd56_gnss_poll(FAR struct file *filep, FAR struct pollfd *fds,
}
errout:
sem_post(&priv->devsem);
nxsem_post(&priv->devsem);
return ret;
}
#endif
@ -2848,21 +2847,21 @@ static int cxd56_gnss_register(FAR const char *devpath)
memset(priv, 0, sizeof(struct cxd56_gnss_dev_s));
ret = sem_init(&priv->devsem, 0, 1);
ret = nxsem_init(&priv->devsem, 0, 1);
if (ret < 0)
{
gnsserr("Failed to initialize gnss devsem!\n");
goto _err0;
}
ret = sem_init(&priv->apiwait, 0, 0);
ret = nxsem_init(&priv->apiwait, 0, 0);
if (ret < 0)
{
gnsserr("Failed to initialize gnss apiwait!\n");
goto _err0;
}
ret = sem_init(&priv->ioctllock, 0, 1);
ret = nxsem_init(&priv->ioctllock, 0, 1);
if (ret < 0)
{
gnsserr("Failed to initialize gnss ioctllock!\n");

30
arch/arm/src/cxd56xx/cxd56_i2c.c
View File

@ -365,7 +365,7 @@ static void cxd56_i2c_timeout(int argc, uint32_t arg, ...)
irqstate_t flags = enter_critical_section();
priv->error = -ENODEV;
sem_post(&priv->wait);
nxsem_post(&priv->wait);
leave_critical_section(flags);
}
@ -465,14 +465,14 @@ static int cxd56_i2c_interrupt(int irq, FAR void *context, FAR void *arg)
if ((priv->error) || (state & INTR_TX_EMPTY) || (state & INTR_RX_FULL))
{
/* Failure of wd_cancel() means that the timer expired.
* In this case, sem_post() has already been called.
* Therefore, call sem_post() only when wd_cancel() succeeds.
* In this case, nxsem_post() has already been called.
* Therefore, call nxsem_post() only when wd_cancel() succeeds.
*/
ret = wd_cancel(priv->timeout);
if (ret == OK)
{
sem_post(&priv->wait);
nxsem_post(&priv->wait);
}
}
@ -535,7 +535,7 @@ static int cxd56_i2c_receive(struct cxd56_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, CXD56_IC_INTR_MASK, INTR_RX_FULL, INTR_RX_FULL);
leave_critical_section(flags);
sem_wait(&priv->wait);
nxsem_wait(&priv->wait);
if (priv->error != OK)
{
@ -581,7 +581,7 @@ static int cxd56_i2c_send(struct cxd56_i2cdev_s *priv, int last)
i2c_reg_rmw(priv, CXD56_IC_INTR_MASK, INTR_TX_EMPTY, INTR_TX_EMPTY);
leave_critical_section(flags);
sem_wait(&priv->wait);
nxsem_wait(&priv->wait);
return 0;
}
@ -610,13 +610,13 @@ static int cxd56_i2c_transfer(FAR struct i2c_master_s *dev,
/* Get exclusive access to the I2C bus */
sem_wait(&priv->mutex);
nxsem_wait(&priv->mutex);
/* Check wait semaphore value. If the value is not 0, the transfer can not
* be performed normally.
*/
ret = sem_getvalue(&priv->wait, &semval);
ret = nxsem_getvalue(&priv->wait, &semval);
DEBUGASSERT(ret == OK && semval == 0);
/* Disable clock gating (clock enable) */
@ -688,7 +688,7 @@ static int cxd56_i2c_transfer(FAR struct i2c_master_s *dev,
cxd56_i2c_clock_gate_enable(priv->port);
sem_post(&priv->mutex);
nxsem_post(&priv->mutex);
return ret;
}
@ -828,7 +828,7 @@ static int cxd56_i2c_transfer_scu(FAR struct i2c_master_s *dev,
/* Get exclusive access to the I2C bus */
sem_wait(&priv->mutex);
nxsem_wait(&priv->mutex);
/* Apply frequency for request msgs */
@ -865,7 +865,7 @@ static int cxd56_i2c_transfer_scu(FAR struct i2c_master_s *dev,
}
}
sem_post(&priv->mutex);
nxsem_post(&priv->mutex);
return ret;
}
@ -1028,8 +1028,8 @@ struct i2c_master_s *cxd56_i2cbus_initialize(int port)
cxd56_i2c_pincontrol(port, true);
sem_init(&priv->mutex, 0, 1);
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->mutex, 0, 1);
nxsem_init(&priv->wait, 0, 0);
priv->timeout = wd_create();
@ -1096,8 +1096,8 @@ int cxd56_i2cbus_uninitialize(FAR struct i2c_master_s *dev)
wd_delete(priv->timeout);
priv->timeout = NULL;
sem_destroy(&priv->mutex);
sem_destroy(&priv->wait);
nxsem_destroy(&priv->mutex);
nxsem_destroy(&priv->wait);
return OK;
}

13
arch/arm/src/cxd56xx/cxd56_icc.c
View File

@ -159,15 +159,12 @@ static struct iccdev_s *g_cpumsg[NCPUS];
static void icc_semtake(sem_t *semid)
{
while (sem_wait(semid) != 0)
{
ASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(semid);
}
static void icc_semgive(sem_t *semid)
{
sem_post(semid);
nxsem_post(semid);
}
static FAR struct iccdev_s *icc_getprotocol(int protoid)
@ -254,9 +251,9 @@ static int icc_irqhandler(int cpuid, uint32_t word[2])
# ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_ptr = priv->sigdata;
(void)sigqueue(priv->pid, priv->signo, value);
sigqueue(priv->pid, priv->signo, value);
# else
(void)sigqueue(priv->pid, priv->signo, priv->sigdata);
sigqueue(priv->pid, priv->signo, priv->sigdata);
# endif
}
#endif
@ -362,7 +359,7 @@ static FAR struct iccdev_s *icc_devnew(void)
priv->rxtimeout = wd_create();
sem_init(&priv->rxwait, 0, 0);
nxsem_init(&priv->rxwait, 0, 0);
/* Initialize receive queue and free list */

4
arch/arm/src/cxd56xx/cxd56_idle.c
View File

@ -111,7 +111,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
(void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@ -135,7 +135,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
(void)cxd56_pmsleep();
cxd56_pmsleep();
break;
default:

12
arch/arm/src/cxd56xx/cxd56_irq.c
View File

@ -173,7 +173,7 @@ static void cxd56_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int cxd56_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@ -181,7 +181,7 @@ static int cxd56_nmi(int irq, FAR void *context, FAR void *arg)
static int cxd56_busfault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Bus fault received\n");
PANIC();
return 0;
@ -189,7 +189,7 @@ static int cxd56_busfault(int irq, FAR void *context, FAR void *arg)
static int cxd56_usagefault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Usage fault received\n");
PANIC();
return 0;
@ -197,7 +197,7 @@ static int cxd56_usagefault(int irq, FAR void *context, FAR void *arg)
static int cxd56_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@ -205,7 +205,7 @@ static int cxd56_pendsv(int irq, FAR void *context, FAR void *arg)
static int cxd56_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@ -213,7 +213,7 @@ static int cxd56_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int cxd56_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;

38
arch/arm/src/cxd56xx/cxd56_powermgr.c
View File

@ -177,15 +177,7 @@ static struct pm_cpu_wakelock_s g_wlock =
static int cxd56_pm_semtake(FAR sem_t *id)
{
while (sem_wait(id) != 0)
{
if (errno != EINTR)
{
pmerr("ERR:sem_wait\n");
return errno;
}
}
return OK;
return nxsem_wait_uninterruptible(id);
}
static int cxd56_pm_needcallback(uint32_t target,
@ -315,7 +307,7 @@ static void cxd56_pm_clkchange(struct cxd56_pm_message_s *message)
cxd56_pmsendmsg(mid, ret);
sem_post(&g_regcblock);
nxsem_post(&g_regcblock);
}
static void cxd56_pm_checkfreqlock(void)
@ -463,7 +455,7 @@ FAR void *cxd56_pm_register_callback(uint32_t target,
entry = (struct pm_cbentry_s *)kmm_malloc(sizeof(struct pm_cbentry_s));
if (entry == NULL)
{
sem_post(&g_regcblock);
nxsem_post(&g_regcblock);
return NULL;
}
@ -471,7 +463,7 @@ FAR void *cxd56_pm_register_callback(uint32_t target,
entry->callback = callback;
dq_addlast((FAR dq_entry_t *)entry, &g_cbqueue);
sem_post(&g_regcblock);
nxsem_post(&g_regcblock);
return (void *)entry;
}
@ -483,7 +475,7 @@ void cxd56_pm_unregister_callback(FAR void *handle)
dq_rem((FAR dq_entry_t *)handle, &g_cbqueue);
kmm_free(handle);
sem_post(&g_regcblock);
nxsem_post(&g_regcblock);
}
static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata,
@ -517,7 +509,7 @@ static int cxd56_pmmsghandler(int cpuid, int protoid, uint32_t pdata,
}
else if (msgid == MSGID_FREQLOCK)
{
sem_post(&g_freqlockwait);
nxsem_post(&g_freqlockwait);
}
else
{
@ -573,7 +565,7 @@ void up_pm_acquire_freqlock(struct pm_cpu_freqlock_s *lock)
lock->count++;
sem_post(&g_freqlock);
nxsem_post(&g_freqlock);
up_pm_release_wakelock(&g_wlock);
}
@ -614,7 +606,7 @@ void up_pm_release_freqlock(struct pm_cpu_freqlock_s *lock)
}
}
sem_post(&g_freqlock);
nxsem_post(&g_freqlock);
up_pm_release_wakelock(&g_wlock);
}
@ -651,7 +643,7 @@ int up_pm_get_freqlock_count(struct pm_cpu_freqlock_s *lock)
}
}
sem_post(&g_freqlock);
nxsem_post(&g_freqlock);
return count;
}
@ -795,22 +787,22 @@ int cxd56_pm_initialize(void)
sq_init(&g_freqlockqueue);
sq_init(&g_wakelockqueue);
ret = sem_init(&g_regcblock, 0, 1);
ret = nxsem_init(&g_regcblock, 0, 1);
if (ret < 0)
{
return -EPERM;
return ret;
}
ret = sem_init(&g_freqlock, 0, 1);
ret = nxsem_init(&g_freqlock, 0, 1);
if (ret < 0)
{
return -EPERM;
return ret;
}
ret = sem_init(&g_freqlockwait, 0, 0);
ret = nxsem_init(&g_freqlockwait, 0, 0);
if (ret < 0)
{
return -EPERM;
return ret;
}
attr.mq_maxmsg = 8;

2
arch/arm/src/cxd56xx/cxd56_rtc.c
View File

@ -160,7 +160,7 @@ static void rtc_dumptime(FAR const struct timespec *tp, FAR const char *msg)
{
FAR struct tm tm;
(void)gmtime_r(&tp->tv_sec, &tm);
gmtime_r(&tp->tv_sec, &tm);
rtcinfo("%s:\n", msg);
rtcinfo("RTC %u.%09u\n", tp->tv_sec, tp->tv_nsec);

2
arch/arm/src/cxd56xx/cxd56_rtc_lowerhalf.c
View File

@ -417,7 +417,7 @@ static int cxd56_setrelative(FAR struct rtc_lowerhalf_s *lower,
seconds = ts.tv_sec + (alarminfo->reltime + 1);
(void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
gmtime_r(&seconds, (FAR struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */

32
arch/arm/src/cxd56xx/cxd56_scu.c
View File

@ -374,11 +374,7 @@ static const struct coeff_addr_s g_caddrs[3][2] =
static int seq_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
return nxsem_wait_uninterruptible(id);
}
/****************************************************************************
@ -387,7 +383,7 @@ static int seq_semtake(sem_t *id)
static void seq_semgive(sem_t *id)
{
sem_post(id);
nxsem_post(id);
}
/****************************************************************************
@ -1514,9 +1510,9 @@ static void seq_handlefifointr(FAR struct cxd56_scudev_s *priv, uint32_t intr)
# ifdef CONFIG_CAN_PASS_STRUCTS
value.sival_ptr = notify->ts;
(void)sigqueue(notify->pid, notify->signo, value);
sigqueue(notify->pid, notify->signo, value);
# else
(void)sigqueue(notify->pid, notify->signo, (FAR void *)notify->ts);
sigqueue(notify->pid, notify->signo, (FAR void *)notify->ts);
# endif
#endif
}
@ -1606,9 +1602,9 @@ static void seq_handlemathfintr(FAR struct cxd56_scudev_s *priv,
# ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_ptr = notify->arg;
(void)sigqueue(notify->pid, notify->signo, value);
sigqueue(notify->pid, notify->signo, value);
# else
(void)sigqueue(notify->pid, notify->signo, (FAR void *)notify->arg);
sigqueue(notify->pid, notify->signo, (FAR void *)notify->arg);
# endif
detected = 0;
}
@ -1999,7 +1995,7 @@ static int seq_fifoinit(FAR struct seq_s *seq, int fifoid, uint16_t fsize)
/* Initialize DMA done wait semaphore */
sem_init(&fifo->dmawait, 0, 0);
nxsem_init(&fifo->dmawait, 0, 0);
fifo->dmaresult = -1;
#endif
@ -2085,7 +2081,7 @@ static void seq_fifofree(FAR struct scufifo_s *fifo)
scufifo_memfree(fifo->start);
#ifdef CONFIG_CXD56_UDMAC
sem_destroy(&fifo->dmawait);
nxsem_destroy(&fifo->dmawait);
#endif
kmm_free(fifo);
@ -3422,12 +3418,12 @@ void scu_initialize(void)
memset(priv, 0, sizeof(struct cxd56_scudev_s));
sem_init(&priv->syncwait, 0, 0);
sem_init(&priv->syncexc, 0, 1);
nxsem_init(&priv->syncwait, 0, 0);
nxsem_init(&priv->syncexc, 0, 1);
for (i = 0; i < 3; i++)
{
sem_init(&priv->oneshotwait[i], 0, 0);
nxsem_init(&priv->oneshotwait[i], 0, 0);
}
scufifo_initialize();
@ -3489,11 +3485,11 @@ void scu_uninitialize(void)
cxd56_scuseq_clock_disable();
sem_destroy(&priv->syncwait);
sem_destroy(&priv->syncexc);
nxsem_destroy(&priv->syncwait);
nxsem_destroy(&priv->syncexc);
for (i = 0; i < 3; i++)
{
sem_destroy(&priv->oneshotwait[i]);
nxsem_destroy(&priv->oneshotwait[i]);
}
}

72
arch/arm/src/cxd56xx/cxd56_sdhci.c
View File

@ -356,7 +356,7 @@ struct cxd56_sdhcregs_s
/* Low-level helpers ********************************************************/
static void cxd56_takesem(struct cxd56_sdiodev_s *priv);
#define cxd56_givesem(priv) (sem_post(&(priv)->waitsem))
#define cxd56_givesem(priv) (nxsem_post(&(priv)->waitsem))
static void cxd56_configwaitints(struct cxd56_sdiodev_s *priv,
uint32_t waitints, sdio_eventset_t waitevents,
sdio_eventset_t wkupevents);
@ -570,16 +570,7 @@ static FAR uint32_t cxd56_sdhci_adma_dscr[CXD56_SDIO_MAX_LEN_ADMA_DSCR * 2];
static void cxd56_takesem(struct cxd56_sdiodev_s *priv)
{
/* Take the semaphore (perhaps waiting) */
while (sem_wait(&priv->waitsem) != 0)
{
/* The only case that an error should occr here is if the wait was
* awakened by a signal.
*/
ASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(&priv->waitsem);
}
/****************************************************************************
@ -1075,7 +1066,7 @@ static void cxd56_endwait(struct cxd56_sdiodev_s *priv,
{
/* Cancel the watchdog timeout */
(void)wd_cancel(priv->waitwdog);
wd_cancel(priv->waitwdog);
/* Disable event-related interrupts */
@ -1279,8 +1270,8 @@ static int cxd56_interrupt(int irq, FAR void *context, FAR void *arg)
putreg32(getreg32(CXD56_SDHCI_IRQSTATEN) & (~SDHCI_INT_CINT),
CXD56_SDHCI_IRQSTATEN);
work_cancel(HPWORK, &priv->cbwork);
(void)work_queue(HPWORK, &priv->cbwork,
(worker_t)cxd56_sdhci_irq_handler, &priv->dev, 0);
work_queue(HPWORK, &priv->cbwork,
(worker_t)cxd56_sdhci_irq_handler, &priv->dev, 0);
}
#endif /* CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION */
@ -1429,13 +1420,13 @@ static void cxd56_sdio_sdhci_reset(FAR struct sdio_dev_s *dev)
/* Initialize the SDHC slot structure data structure */
/* Initialize semaphores */
sem_init(&priv->waitsem, 0, 0);
nxsem_init(&priv->waitsem, 0, 0);
/* The waitsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
sem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
nxsem_setprotocol(&priv->waitsem, SEM_PRIO_NONE);
/* Create a watchdog timer */
@ -2147,7 +2138,7 @@ static int cxd56_sdio_cancel(FAR struct sdio_dev_s *dev)
/* Cancel any watchdog timeout */
(void)wd_cancel(priv->waitwdog);
wd_cancel(priv->waitwdog);
/* If this was a DMA transfer, make sure that DMA is stopped */
@ -3216,8 +3207,8 @@ static void cxd56_sdio_callback(void *arg)
work_cancel(HPWORK, &priv->cbwork);
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, delay);
work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
priv->cbarg, delay);
}
else
{
@ -3233,18 +3224,7 @@ static void cxd56_sdio_callback(void *arg)
#ifdef CONFIG_CXD56_SDIO_ENABLE_MULTIFUNCTION
static void cxd56_sdio_takesem(FAR struct cxd56_sdiodev_s *priv)
{
/* Take the semaphore, giving exclusive access to the driver (perhaps
* waiting)
*/
while (sem_wait(&priv->sc.sem) != 0)
{
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
ASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(&priv->sc.sem);
}
/****************************************************************************
@ -3737,13 +3717,13 @@ static int cxd56_sdio_register_irq(FAR struct sdio_dev_s *dev, int func_num,
cxd56_sdio_writeb_internal(sf0, SDIO_CCCR_INTEN, regorg, NULL);
goto REG_IRQ_FAIL;
}
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
REG_IRQ_FAIL:
sf->irq_callback = NULL;
mcerr("ERROR: Ret: %d\n", ret);
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
}
@ -3844,11 +3824,11 @@ static int cxd56_sdio_function_disable(FAR struct sdio_dev_s *dev,
{
goto FUNC_DIS_ERR;
}
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return 0;
FUNC_DIS_ERR:
mcerr("ERROR: Io fail ret %u\n", ret);
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
}
@ -3908,12 +3888,12 @@ static int cxd56_sdio_function_enable(FAR struct sdio_dev_s *dev,
if (0 == ret)
{
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return 0;
}
FUNC_EN_ERR:
mcerr("ERROR: Io fail ret %u\n", ret);
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return -EIO;
}
@ -3941,7 +3921,7 @@ static int cxd56_sdio_readb(FAR struct sdio_dev_s *dev, int func_num,
cxd56_sdio_takesem(priv);
ret = cxd56_sdio_readb_internal(priv->sc.fn[func_num], addr, rdata);
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
}
@ -3969,7 +3949,7 @@ static int cxd56_sdio_writeb(FAR struct sdio_dev_s *dev, int func_num,
cxd56_sdio_takesem(priv);
ret = cxd56_sdio_writeb_internal(priv->sc.fn[func_num], addr, data, rdata);
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
}
@ -4093,13 +4073,13 @@ static int cxd56_sdio_write(FAR struct sdio_dev_s *dev, int func_num,
data += size;
addr += size;
}
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return 0;
WRITE_TIME_OUT:
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return wkupevent & SDIOWAIT_TIMEOUT ? -ETIMEDOUT : -EIO;
WRITE_ERR:
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
}
@ -4223,13 +4203,13 @@ static int cxd56_sdio_read(FAR struct sdio_dev_s *dev, int func_num,
data += size;
addr += size;
}
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return 0;
READ_TIME_OUT:
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return wkupevent & SDIOWAIT_TIMEOUT ? -ETIMEDOUT : -EIO;
READ_ERR:
sem_post(&priv->sc.sem);
nxsem_post(&priv->sc.sem);
return ret;
}
@ -4273,7 +4253,7 @@ static int cxd56_sdio_initialize(struct cxd56_sdiodev_s *priv)
priv->sc.full_speed = false;
priv->blocksize = SDIO_BLOCK_SIZE;
sem_init(&priv->sc.sem, 0, 1);
nxsem_init(&priv->sc.sem, 0, 1);
#ifdef CONFIG_SDIO_DMA
priv->sc.dma = true;
#endif

9
arch/arm/src/cxd56xx/cxd56_serial.c
View File

@ -543,10 +543,7 @@ static void up_detach(FAR struct uart_dev_s *dev)
static bool up_rxflowcontrol(FAR struct uart_dev_s *dev,
unsigned int nbuffered, bool upper)
{
(void)nbuffered;
up_rxint(dev, !upper);
return true;
}
#endif /* CONFIG_SERIAL_IFLOWCONTROL */
@ -924,13 +921,13 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
#endif
#ifdef TTYS2_DEV
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
}

10
arch/arm/src/cxd56xx/cxd56_sph.c
View File

@ -167,16 +167,12 @@ static int sph_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static int sph_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
return nxsem_wait_uninterruptible(id);
}
static void sph_semgive(sem_t *id)
{
sem_post(id);
nxsem_post(id);
}
static int sph_lock(FAR struct sph_dev_s *priv)
@ -263,7 +259,7 @@ static inline int cxd56_sphdevinit(FAR const char *devname, int num)
return ERROR;
}
sem_init(&priv->wait, 0, 0);
nxsem_init(&priv->wait, 0, 0);
priv->id = num;
irq_attach(CXD56_IRQ_SPH0 + num, cxd56_sphirqhandler, NULL);

35
arch/arm/src/cxd56xx/cxd56_spi.c
View File

@ -428,21 +428,12 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
{
/* Take the semaphore (perhaps waiting) */
while (sem_wait(&priv->exclsem) != 0)
{
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
ASSERT(errno == EINTR);
}
return nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
(void)sem_post(&priv->exclsem);
return nxsem_post(&priv->exclsem);
}
return OK;
}
/****************************************************************************
@ -1174,7 +1165,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
return NULL;
}
#endif
sem_init(&priv->dmasem, 0, 0);
nxsem_init(&priv->dmasem, 0, 0);
}
#endif
@ -1199,7 +1190,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
return NULL;
}
#endif
sem_init(&priv->dmasem, 0, 0);
nxsem_init(&priv->dmasem, 0, 0);
}
#endif
@ -1240,7 +1231,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
/* Initialize the SPI semaphore that enforces mutually exclusive access */
sem_init(&priv->exclsem, 0, 1);
nxsem_init(&priv->exclsem, 0, 1);
#ifdef CONFIG_CXD56_SPI3_SCUSEQ
/* Enable the SPI, but not enable port 3 when SCU support enabled.
@ -1258,7 +1249,7 @@ FAR struct spi_dev_s *cxd56_spibus_initialize(int port)
for (i = 0; i < CXD56_SPI_FIFOSZ; i++)
{
(void)spi_getreg(priv, CXD56_SPI_DR_OFFSET);
spi_getreg(priv, CXD56_SPI_DR_OFFSET);
}
/* Enable clock gating (clock disable) */
@ -1321,7 +1312,7 @@ void spi_flush(FAR struct spi_dev_s *dev)
do
{
(void)spi_getreg(priv, CXD56_SPI_DR_OFFSET);
spi_getreg(priv, CXD56_SPI_DR_OFFSET);
}
while (spi_getreg(priv, CXD56_SPI_SR_OFFSET) & SPI_SR_RNE);
@ -1471,7 +1462,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t status, void *data)
spierr("dma error\n");
}
(void)sem_post(&priv->dmasem);
nxsem_post(&priv->dmasem);
}
/****************************************************************************
@ -1493,7 +1484,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *data)
spierr("dma error\n");
}
(void)sem_post(&priv->dmasem);
nxsem_post(&priv->dmasem);
}
/****************************************************************************
@ -1554,7 +1545,7 @@ static void spi_dmatxwait(FAR struct cxd56_spidev_s *priv)
{
uint32_t val;
if (sem_wait(&priv->dmasem) != OK)
if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
@ -1578,7 +1569,7 @@ static void spi_dmarxwait(FAR struct cxd56_spidev_s *priv)
{
uint32_t val;
if (sem_wait(&priv->dmasem) != OK)
if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
@ -1602,12 +1593,12 @@ static void spi_dmatrxwait(FAR struct cxd56_spidev_s *priv)
{
uint32_t val;
if (sem_wait(&priv->dmasem) != OK)
if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}
if (sem_wait(&priv->dmasem) != OK)
if (nxsem_wait(&priv->dmasem) != OK)
{
spierr("dma error\n");
}

13
arch/arm/src/cxd56xx/cxd56_sysctl.c
View File

@ -86,15 +86,12 @@ static int sysctl_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static void sysctl_semtake(sem_t *semid)
{
while (sem_wait(semid) != 0)
{
ASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(semid);
}
static void sysctl_semgive(sem_t *semid)
{
sem_post(semid);
nxsem_post(semid);
}
static int sysctl_rxhandler(int cpuid, int protoid,
@ -150,10 +147,10 @@ void cxd56_sysctlinitialize(void)
{
cxd56_iccinit(CXD56_PROTO_SYSCTL);
sem_init(&g_exc, 0, 1);
sem_init(&g_sync, 0, 0);
nxsem_init(&g_exc, 0, 1);
nxsem_init(&g_sync, 0, 0);
cxd56_iccregisterhandler(CXD56_PROTO_SYSCTL, sysctl_rxhandler, NULL);
(void)register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL);
register_driver("/dev/sysctl", &g_sysctlfops, 0666, NULL);
}

4
arch/arm/src/cxd56xx/cxd56_timer.c
View File

@ -569,7 +569,7 @@ void cxd56_timer_initialize(FAR const char *devpath, int timer)
priv->ops = &g_tmrops;
(void)irq_attach(irq, cxd56_timer_interrupt, priv);
irq_attach(irq, cxd56_timer_interrupt, priv);
/* Enable NVIC interrupt. */
@ -577,7 +577,7 @@ void cxd56_timer_initialize(FAR const char *devpath, int timer)
/* Register the timer driver as /dev/timerX */
(void)timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv);
timer_register(devpath, (FAR struct timer_lowerhalf_s *)priv);
}
#endif /* CONFIG_TIMER */

2
arch/arm/src/cxd56xx/cxd56_timerisr.c
View File

@ -184,7 +184,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(CXD56_IRQ_SYSTICK, (xcpt_t)cxd56_timerisr, NULL);
irq_attach(CXD56_IRQ_SYSTICK, (xcpt_t)cxd56_timerisr, NULL);
/* Enable SysTick interrupts */

12
arch/arm/src/cxd56xx/cxd56_uart0.c
View File

@ -128,11 +128,7 @@ static sem_t g_lock;
static int uart0_semtake(sem_t *id)
{
while (sem_wait(id) != 0)
{
ASSERT(errno == EINTR);
}
return OK;
return nxsem_wait_uninterruptible(id);
}
/****************************************************************************
@ -141,7 +137,7 @@ static int uart0_semtake(sem_t *id)
static void uart0_semgive(sem_t *id)
{
sem_post(id);
nxsem_post(id);
}
/****************************************************************************
@ -301,7 +297,7 @@ int cxd56_uart0initialize(FAR const char *devname)
{
int ret;
sem_init(&g_lock, 0, 1);
nxsem_init(&g_lock, 0, 1);
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
@ -319,7 +315,7 @@ int cxd56_uart0initialize(FAR const char *devname)
void cxd56_uart0uninitialize(FAR const char *devname)
{
unregister_driver(devname);
sem_destroy(&g_lock);
nxsem_destroy(&g_lock);
}
#endif /* CONFIG_CXD56_UART0 */

24
arch/arm/src/cxd56xx/cxd56_udmac.c
View File

@ -252,8 +252,8 @@ void cxd56_udmainitialize(void)
/* Initialize the channel list */
sem_init(&g_dmac.exclsem, 0, 1);
sem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS);
nxsem_init(&g_dmac.exclsem, 0, 1);
nxsem_init(&g_dmac.chansem, 0, CXD56_DMA_NCHANNELS);
for (i = 0; i < CXD56_DMA_NCHANNELS; i++)
{
@ -311,21 +311,11 @@ DMA_HANDLE cxd56_udmachannel(void)
* reserved for us.
*/
while (sem_wait(&g_dmac.chansem) < 0)
{
/* sem_wait should fail only if it is awakened by a a signal */
DEBUGASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(&g_dmac.chansem);
/* Get exclusive access to the DMA channel list */
while (sem_wait(&g_dmac.exclsem) < 0)
{
/* sem_wait should fail only if it is awakened by a a signal */
DEBUGASSERT(errno == EINTR);
}
nxsem_wait_uninterruptible(&g_dmac.exclsem);
/* Search for an available DMA channel */
@ -346,11 +336,11 @@ DMA_HANDLE cxd56_udmachannel(void)
}
}
sem_post(&g_dmac.exclsem);
nxsem_post(&g_dmac.exclsem);
/* Attach DMA interrupt vector */
(void)irq_attach(CXD56_IRQ_DMA_A_0 + ch, cxd56_dmac_interrupt, NULL);
irq_attach(CXD56_IRQ_DMA_A_0 + ch, cxd56_dmac_interrupt, NULL);
/* Enable the IRQ at the AIC (still disabled at the DMA controller) */
@ -405,7 +395,7 @@ void cxd56_udmafree(DMA_HANDLE handle)
* thread that may be waiting for a channel.
*/
sem_post(&g_dmac.chansem);
nxsem_post(&g_dmac.chansem);
}
/****************************************************************************

4
arch/arm/src/cxd56xx/cxd56_usbdev.c
View File

@ -3348,9 +3348,9 @@ static void cxd56_notify_signal(uint16_t state, uint16_t power)
#ifdef CONFIG_CAN_PASS_STRUCTS
union sigval value;
value.sival_int = state << 16 | power;
(void)sigqueue(priv->pid, priv->signo, value);
sigqueue(priv->pid, priv->signo, value);
#else
(void)sigqueue(priv->pid, priv->signo, state << 16 | power);
sigqueue(priv->pid, priv->signo, state << 16 | power);
#endif
}
}

4
arch/arm/src/cxd56xx/cxd56_wdt.c
View File

@ -673,12 +673,12 @@ int cxd56_wdt_initialize(void)
#ifdef CONFIG_CXD56_WDT_INTERRUPT
/* Attach our WDT interrupt handler (But don't enable it yet) */
(void)irq_attach(CXD56_IRQ_WDT_INT, cxd56_wdtinterrupt, priv);
irq_attach(CXD56_IRQ_WDT_INT, cxd56_wdtinterrupt, priv);
#endif
/* Register the watchdog driver as /dev/watchdog0 */
(void)watchdog_register(DEVPATH, (FAR struct watchdog_lowerhalf_s *)priv);
watchdog_register(DEVPATH, (FAR struct watchdog_lowerhalf_s *)priv);
/* Register pm event callback */

2
arch/arm/src/dm320/dm320_decodeirq.c
View File

@ -118,7 +118,7 @@ void up_decodeirq(uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(NULL);
group_addrenv(NULL);
#endif
}
#endif

6
arch/arm/src/dm320/dm320_serial.c
View File

@ -737,9 +737,9 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
(void)uart_register("/dev/console", &CONSOLE_DEV);
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
}
/****************************************************************************

6
arch/arm/src/dm320/dm320_usbdev.c
View File

@ -1304,7 +1304,7 @@ static inline void dm320_ep0setup(struct dm320_usbdev_s *priv)
/* Restart the write queue */
(void)dm320_wrrequest(privep);
dm320_wrrequest(privep);
}
else
{
@ -1581,7 +1581,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg)
if ((csr0 & USB_PERCSR0_RXPKTRDY) != 0)
{
usbtrace(TRACE_INTENTRY(DM320_TRACEINTID_RXPKTRDY), csr0);
(void)dm320_getreg8(DM320_USB_COUNT0);
dm320_getreg8(DM320_USB_COUNT0);
dm320_ep0setup(priv);
}
else if ((csr0 & USB_PERCSR0_SENTST) != 0)
@ -1643,7 +1643,7 @@ static int dm320_ctlrinterrupt(int irq, FAR void *context, FAR void *arg)
if (!dm320_rqempty(privep))
{
(void)dm320_wrrequest(privep);
dm320_wrrequest(privep);
}
}
break;

31
arch/arm/src/efm32/efm32_dma.c
View File

@ -297,7 +297,7 @@ void weak_function up_dma_initialize(void)
/* Attach DMA interrupt vector */
(void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt, NULL);
irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt, NULL);
/* Enable the DMA controller */
@ -336,7 +336,6 @@ DMA_HANDLE efm32_dmachannel(void)
struct dma_channel_s *dmach;
unsigned int chndx;
uint32_t bit;
int ret;
/* Take a count from from the channel counting semaphore. We may block
* if there are no free channels. When we get the count, then we can
@ -344,35 +343,11 @@ DMA_HANDLE efm32_dmachannel(void)
* reserved for us.
*/
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&g_dmac.chansem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&g_dmac.chansem);
/* Get exclusive access to the DMA channel list */
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&g_dmac.exclsem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&g_dmac.exclsem);
/* Search for an available DMA channel */

27
arch/arm/src/efm32/efm32_i2c.c
View File

@ -480,21 +480,7 @@ static const char *efm32_i2c_state_str(int i2c_state)
static inline void efm32_i2c_sem_wait(FAR struct efm32_i2c_priv_s *priv)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&priv->sem_excl);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&priv->sem_excl);
}
/****************************************************************************
@ -544,7 +530,7 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
{
/* Get the current time */
(void)clock_gettime(CLOCK_REALTIME, &abstime);
clock_gettime(CLOCK_REALTIME, &abstime);
/* Calculate a time in the future */
@ -578,17 +564,16 @@ static inline int efm32_i2c_sem_waitdone(FAR struct efm32_i2c_priv_s *priv)
/* Wait until either the transfer is complete or the timeout expires */
ret = nxsem_timedwait(&priv->sem_isr, &abstime);
ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime);
/* Disable I2C interrupts */
efm32_i2c_putreg(priv, EFM32_I2C_IEN_OFFSET, 0);
if (ret < 0 && ret != -EINTR)
if (ret < 0)
{
/* Break out of the loop on irrecoverable errors. This would include
* timeouts and mystery errors reported by nxsem_timedwait. NOTE that
* we try again if we are awakened by a signal (EINTR).
* timeouts and mystery errors reported by nxsem_timedwait.
*/
break;
@ -1495,7 +1480,7 @@ static int efm32_i2c_transfer(FAR struct i2c_master_s *dev,
I2C_CMD_CLEARPC | I2C_CMD_CLEARTX);
if (efm32_i2c_getreg(priv, EFM32_I2C_IF_OFFSET) & I2C_IF_RXDATAV)
{
(void)efm32_i2c_getreg(priv, EFM32_I2C_RXDATA_OFFSET);
efm32_i2c_getreg(priv, EFM32_I2C_RXDATA_OFFSET);
}
/* Clear all pending interrupts prior to starting transfer. */

4
arch/arm/src/efm32/efm32_idle.c
View File

@ -119,7 +119,7 @@ static void up_idlepm(void)
{
/* The new state change failed, revert to the preceding state */
(void)pm_changestate(PM_IDLE_DOMAIN, oldstate);
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
@ -143,7 +143,7 @@ static void up_idlepm(void)
break;
case PM_SLEEP:
(void)efm32_pmstandby();
efm32_pmstandby();
break;
default:

12
arch/arm/src/efm32/efm32_irq.c
View File

@ -166,7 +166,7 @@ static void efm32_dumpnvic(const char *msg, int irq)
#ifdef CONFIG_DEBUG_FEATURES
static int efm32_nmi(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! NMI received\n");
PANIC();
return 0;
@ -174,7 +174,7 @@ static int efm32_nmi(int irq, FAR void *context, FAR void *arg)
static int efm32_busfault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Bus fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@ -182,7 +182,7 @@ static int efm32_busfault(int irq, FAR void *context, FAR void *arg)
static int efm32_usagefault(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Usage fault received: %08x\n", getreg32(NVIC_CFAULTS));
PANIC();
return 0;
@ -190,7 +190,7 @@ static int efm32_usagefault(int irq, FAR void *context, FAR void *arg)
static int efm32_pendsv(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! PendSV received\n");
PANIC();
return 0;
@ -198,7 +198,7 @@ static int efm32_pendsv(int irq, FAR void *context, FAR void *arg)
static int efm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Debug Monitor received\n");
PANIC();
return 0;
@ -206,7 +206,7 @@ static int efm32_dbgmonitor(int irq, FAR void *context, FAR void *arg)
static int efm32_reserved(int irq, FAR void *context, FAR void *arg)
{
(void)up_irq_save();
up_irq_save();
_err("PANIC!!! Reserved interrupt\n");
PANIC();
return 0;

6
arch/arm/src/efm32/efm32_leserial.c
View File

@ -794,14 +794,14 @@ void up_serialinit(void)
/* Register the console */
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
(void)uart_register("/dev/ttyLE0", &TTYLE0_DEV);
uart_register("/dev/ttyLE0", &TTYLE0_DEV);
#ifdef TTYLE1_DEV
(void)uart_register("/dev/ttyLE1", &TTYLE1_DEV);
uart_register("/dev/ttyLE1", &TTYLE1_DEV);
#endif
}

2
arch/arm/src/efm32/efm32_pwm.c
View File

@ -481,7 +481,7 @@ static int pwm_interrupt(int irq, void *context, FAR void *arg)
/* Disable first interrupts, stop and reset the timer */
(void)pwm_stop((FAR struct pwm_lowerhalf_s *)priv);
pwm_stop((FAR struct pwm_lowerhalf_s *)priv);
/* Then perform the callback into the upper half driver */

12
arch/arm/src/efm32/efm32_serial.c
View File

@ -1168,23 +1168,23 @@ void up_serialinit(void)
/* Register the console */
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
/* Register all UARTs */
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
#ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
#endif
#ifdef TTYS2_DEV
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
uart_register("/dev/ttyS2", &TTYS2_DEV);
#endif
#ifdef TTYS3_DEV
(void)uart_register("/dev/ttyS3", &TTYS3_DEV);
uart_register("/dev/ttyS3", &TTYS3_DEV);
#endif
#ifdef TTYS4_DEV
(void)uart_register("/dev/ttyS4", &TTYS4_DEV);
uart_register("/dev/ttyS4", &TTYS4_DEV);
#endif
}

58
arch/arm/src/efm32/efm32_spi.c
View File

@ -377,7 +377,7 @@ static void spi_rxflush(const struct efm32_spiconfig_s *config)
{
/* Read and discard the data */
(void)spi_getreg(config, EFM32_USART_RXDATA_OFFSET);
spi_getreg(config, EFM32_USART_RXDATA_OFFSET);
}
}
@ -437,24 +437,11 @@ static void spi_dma_timeout(int argc, uint32_t arg1, ...)
static void spi_dmarxwait(struct efm32_spidev_s *priv)
{
irqstate_t flags;
int ret;
/* Take the semaphore (perhaps waiting). */
flags = enter_critical_section();
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&priv->rxdmasem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&priv->rxdmasem);
/* Cancel the timeout only if both the RX and TX transfers have completed */
@ -480,24 +467,11 @@ static void spi_dmarxwait(struct efm32_spidev_s *priv)
static void spi_dmatxwait(struct efm32_spidev_s *priv)
{
irqstate_t flags;
int ret;
/* Take the semaphore (perhaps waiting). */
flags = enter_critical_section();
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&priv->txdmasem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&priv->txdmasem);
/* Cancel the timeout only if both the RX and TX transfers have completed */
@ -522,7 +496,7 @@ static void spi_dmatxwait(struct efm32_spidev_s *priv)
#ifdef CONFIG_EFM32_SPI_DMA
static inline void spi_dmarxwakeup(struct efm32_spidev_s *priv)
{
(void)nxsem_post(&priv->rxdmasem);
nxsem_post(&priv->rxdmasem);
}
#endif
@ -537,7 +511,7 @@ static inline void spi_dmarxwakeup(struct efm32_spidev_s *priv)
#ifdef CONFIG_EFM32_SPI_DMA
static inline void spi_dmatxwakeup(struct efm32_spidev_s *priv)
{
(void)nxsem_post(&priv->txdmasem);
nxsem_post(&priv->txdmasem);
}
#endif
@ -755,27 +729,15 @@ static inline void spi_dmatxstart(FAR struct efm32_spidev_s *priv)
static int spi_lock(struct spi_dev_s *dev, bool lock)
{
struct efm32_spidev_s *priv = (struct efm32_spidev_s *)dev;
int ret;
if (lock)
{
/* Take the semaphore (perhaps waiting) */
do
{
ret = nxsem_wait(&priv->exclsem);
/* The only case that an error should occur here is if the wait
* was awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
(void)nxsem_post(&priv->exclsem);
ret = OK;
ret = nxsem_post(&priv->exclsem);
}
return ret;
@ -1655,8 +1617,8 @@ static int spi_portinitialize(struct efm32_spidev_s *priv)
/* Initialized semaphores used to wait for DMA completion */
(void)nxsem_init(&priv->rxdmasem, 0, 0);
(void)nxsem_init(&priv->txdmasem, 0, 0);
nxsem_init(&priv->rxdmasem, 0, 0);
nxsem_init(&priv->txdmasem, 0, 0);
/* These semaphores are used for signaling and, hence, should not have
* priority inheritance enabled.

2
arch/arm/src/efm32/efm32_timerisr.c
View File

@ -125,7 +125,7 @@ void arm_timer_initialize(void)
/* Attach the timer interrupt vector */
(void)irq_attach(EFM32_IRQ_SYSTICK, (xcpt_t)efm32_timerisr, NULL);
irq_attach(EFM32_IRQ_SYSTICK, (xcpt_t)efm32_timerisr, NULL);
/* Enable SysTick interrupts */

22
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -1452,7 +1452,7 @@ static void efm32_rxfifo_discard(FAR struct efm32_ep_s *privep, int len)
for (i = 0; i < len; i += 4)
{
volatile uint32_t data = efm32_getreg(regaddr);
(void)data;
UNUSED(data);
}
}
}
@ -2223,7 +2223,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
{
/* Actually, I think we could just stall here. */
(void)efm32_req_dispatch(priv, &priv->ctrlreq);
efm32_req_dispatch(priv, &priv->ctrlreq);
}
}
else
@ -2269,7 +2269,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
{
/* Actually, I think we could just stall here. */
(void)efm32_req_dispatch(priv, &priv->ctrlreq);
efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@ -2333,7 +2333,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_GETSETDESC), 0);
if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE)
{
(void)efm32_req_dispatch(priv, &priv->ctrlreq);
efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@ -2358,7 +2358,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
ctrlreq->index == 0 &&
ctrlreq->len == 1)
{
(void)efm32_req_dispatch(priv, &priv->ctrlreq);
efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@ -2430,7 +2430,7 @@ static inline void efm32_ep0out_stdrequest(struct efm32_usbdev_s *priv,
{
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_GETSETIF), 0);
(void)efm32_req_dispatch(priv, &priv->ctrlreq);
efm32_req_dispatch(priv, &priv->ctrlreq);
}
break;
@ -2508,7 +2508,7 @@ static inline void efm32_ep0out_setup(struct efm32_usbdev_s *priv)
{
/* Dispatch any non-standard requests */
(void)efm32_req_dispatch(priv, &priv->ctrlreq);
efm32_req_dispatch(priv, &priv->ctrlreq);
}
else
{
@ -4007,10 +4007,10 @@ static void efm32_ep0_configure(FAR struct efm32_usbdev_s *priv)
{
/* Enable EP0 IN and OUT */
(void)efm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL,
CONFIG_USBDEV_EP0_MAXSIZE);
(void)efm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL,
CONFIG_USBDEV_EP0_MAXSIZE);
efm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL,
CONFIG_USBDEV_EP0_MAXSIZE);
efm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL,
CONFIG_USBDEV_EP0_MAXSIZE);
}
/****************************************************************************

24
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -723,21 +723,7 @@ static inline void efm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t set
static void efm32_takesem(sem_t *sem)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(sem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@ -1193,13 +1179,7 @@ static int efm32_chan_wait(FAR struct efm32_usbhost_s *priv,
* wait here.
*/
ret = nxsem_wait(&chan->waitsem);
/* nxsem_wait should succeed. But it is possible that we could be
* awakened by a signal too.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
nxsem_wait_uninterruptible(&chan->waitsem);
}
while (chan->waiter);

2
arch/arm/src/imx1/imx_decodeirq.c
View File

@ -137,7 +137,7 @@ void up_decodeirq(uint32_t *regs)
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(NULL);
group_addrenv(NULL);
#endif
}
#endif

8
arch/arm/src/imx1/imx_serial.c
View File

@ -1141,15 +1141,15 @@ void up_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
uart_register("/dev/ttyS2", &TTYS2_DEV);
# endif
# endif
#endif

31
arch/arm/src/imx1/imx_spi.c
View File

@ -340,7 +340,7 @@ static void spi_txuint8(struct imx_spidev_s *priv)
static void spi_rxnull(struct imx_spidev_s *priv)
{
(void)spi_getreg(priv, CSPI_RXD_OFFSET);
spi_getreg(priv, CSPI_RXD_OFFSET);
}
static void spi_rxuint16(struct imx_spidev_s *priv)
@ -504,7 +504,6 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
#ifndef CONFIG_SPI_POLLWAIT
irqstate_t flags;
uint32_t regval;
int ret;
#endif
int ntxd;
@ -558,13 +557,9 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
* with the transfer, so it should be safe with no timeout.
*/
do
{
/* Wait to be signaled from the interrupt handler */
/* Wait to be signaled from the interrupt handler */
ret = nxsem_wait(&priv->waitsem);
}
while (ret < 0 && ret == -EINTR);
nxsem_wait_uninterruptible(&priv->waitsem);
#else
/* Perform the transfer using polling logic. This will totally
@ -713,19 +708,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&priv->exclsem);
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
(void)nxsem_post(&priv->exclsem);
ret = OK;
ret = nxsem_post(&priv->exclsem);
}
return ret;
@ -919,7 +906,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
uint16_t response = 0;
(void)spi_transfer(priv, &wd, &response, 1);
spi_transfer(priv, &wd, &response, 1);
return response;
}
@ -948,7 +935,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
(void)spi_transfer(priv, txbuffer, rxbuffer, nwords);
spi_transfer(priv, txbuffer, rxbuffer, nwords);
}
#endif
@ -975,7 +962,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
(void)spi_transfer(priv, buffer, NULL, nwords);
spi_transfer(priv, buffer, NULL, nwords);
}
#endif
@ -1002,7 +989,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
(void)spi_transfer(priv, NULL, buffer, nwords);
spi_transfer(priv, NULL, buffer, nwords);
}
#endif

2
arch/arm/src/imx6/imx_cpuboot.c
View File

@ -298,7 +298,7 @@ void arm_cpu_boot(int cpu)
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* And finally, enable interrupts */
(void)up_irq_enable();
up_irq_enable();
#endif
/* The next thing that we expect to happen is for logic running on CPU0

31
arch/arm/src/imx6/imx_ecspi.c
View File

@ -465,7 +465,7 @@ static void spi_txuint8(struct imx_spidev_s *priv)
static void spi_rxnull(struct imx_spidev_s *priv)
{
(void)spi_getreg(priv, ECSPI_RXDATA_OFFSET);
spi_getreg(priv, ECSPI_RXDATA_OFFSET);
}
static void spi_rxuint16(struct imx_spidev_s *priv)
@ -629,7 +629,6 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
#ifndef CONFIG_SPI_POLLWAIT
irqstate_t flags;
uint32_t regval;
int ret;
#endif
int ntxd;
@ -683,13 +682,9 @@ static int spi_transfer(struct imx_spidev_s *priv, const void *txbuffer,
* with the transfer, so it should be safe with no timeout.
*/
do
{
/* Wait to be signaled from the interrupt handler */
/* Wait to be signaled from the interrupt handler */
ret = nxsem_wait(&priv->waitsem);
}
while (ret < 0 && ret == -EINTR);
nxsem_wait_uninterruptible(&priv->waitsem);
#else
/* Perform the transfer using polling logic. This will totally
@ -798,19 +793,11 @@ static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
if (lock)
{
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&priv->exclsem);
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
ret = nxsem_wait_uninterruptible(&priv->exclsem);
}
else
{
(void)nxsem_post(&priv->exclsem);
ret = OK;
ret = nxsem_post(&priv->exclsem);
}
return ret;
@ -1032,7 +1019,7 @@ static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
uint16_t response = 0;
(void)spi_transfer(priv, &wd, &response, 1);
spi_transfer(priv, &wd, &response, 1);
return response;
}
@ -1133,7 +1120,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
(void)spi_transfer(priv, txbuffer, rxbuffer, nwords);
spi_transfer(priv, txbuffer, rxbuffer, nwords);
}
#endif
@ -1160,7 +1147,7 @@ static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
(void)spi_transfer(priv, buffer, NULL, nwords);
spi_transfer(priv, buffer, NULL, nwords);
}
#endif
@ -1187,7 +1174,7 @@ static void spi_sndblock(FAR struct spi_dev_s *dev, FAR const void *buffer, size
static void spi_recvblock(FAR struct spi_dev_s *dev, FAR void *buffer, size_t nwords)
{
struct imx_spidev_s *priv = (struct imx_spidev_s *)dev;
(void)spi_transfer(priv, NULL, buffer, nwords);
spi_transfer(priv, NULL, buffer, nwords);
}
#endif

2
arch/arm/src/imx6/imx_irq.c
View File

@ -183,6 +183,6 @@ void up_irqinitialize(void)
/* And finally, enable interrupts */
(void)up_irq_enable();
up_irq_enable();
#endif
}

42
arch/arm/src/imx6/imx_lowputc.c
View File

@ -188,13 +188,13 @@ void imx_lowsetup(void)
* control is enabled. REVISIT: DTR, DCD, RI, and DSR -- not configured.
*/
(void)imx_config_gpio(GPIO_UART1_RX_DATA);
(void)imx_config_gpio(GPIO_UART1_TX_DATA);
imx_config_gpio(GPIO_UART1_RX_DATA);
imx_config_gpio(GPIO_UART1_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
(void)imx_config_gpio(GPIO_UART1_CTS);
imx_config_gpio(GPIO_UART1_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
(void)imx_config_gpio(GPIO_UART1_RTS);
imx_config_gpio(GPIO_UART1_RTS);
#endif
#endif
@ -210,13 +210,13 @@ void imx_lowsetup(void)
* control is enabled.
*/
(void)imx_config_gpio(GPIO_UART2_RX_DATA);
(void)imx_config_gpio(GPIO_UART2_TX_DATA);
imx_config_gpio(GPIO_UART2_RX_DATA);
imx_config_gpio(GPIO_UART2_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
(void)imx_config_gpio(GPIO_UART2_CTS);
imx_config_gpio(GPIO_UART2_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
(void)imx_config_gpio(GPIO_UART2_RTS);
imx_config_gpio(GPIO_UART2_RTS);
#endif
#endif
@ -232,13 +232,13 @@ void imx_lowsetup(void)
* control is enabled.
*/
(void)imx_config_gpio(GPIO_UART3_RX_DATA);
(void)imx_config_gpio(GPIO_UART3_TX_DATA);
imx_config_gpio(GPIO_UART3_RX_DATA);
imx_config_gpio(GPIO_UART3_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
(void)imx_config_gpio(GPIO_UART3_CTS);
imx_config_gpio(GPIO_UART3_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
(void)imx_config_gpio(GPIO_UART3_RTS);
imx_config_gpio(GPIO_UART3_RTS);
#endif
#endif
@ -254,13 +254,13 @@ void imx_lowsetup(void)
* control is enabled.
*/
(void)imx_config_gpio(GPIO_UART4_RX_DATA);
(void)imx_config_gpio(GPIO_UART4_TX_DATA);
imx_config_gpio(GPIO_UART4_RX_DATA);
imx_config_gpio(GPIO_UART4_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
(void)imx_config_gpio(GPIO_UART4_CTS);
imx_config_gpio(GPIO_UART4_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
(void)imx_config_gpio(GPIO_UART4_RTS);
imx_config_gpio(GPIO_UART4_RTS);
#endif
#endif
@ -276,20 +276,20 @@ void imx_lowsetup(void)
* control is enabled.
*/
(void)imx_config_gpio(GPIO_UART5_RX_DATA);
(void)imx_config_gpio(GPIO_UART5_TX_DATA);
imx_config_gpio(GPIO_UART5_RX_DATA);
imx_config_gpio(GPIO_UART5_TX_DATA);
#ifdef CONFIG_UART1_OFLOWCONTROL
(void)imx_config_gpio(GPIO_UART5_CTS);
imx_config_gpio(GPIO_UART5_CTS);
#endif
#ifdef CONFIG_UART1_IFLOWCONTROL
(void)imx_config_gpio(GPIO_UART5_RTS);
imx_config_gpio(GPIO_UART5_RTS);
#endif
#endif
#ifdef IMX_HAVE_UART_CONSOLE
/* Configure the serial console for initial, non-interrupt driver mode */
(void)imx_uart_configure(IMX_CONSOLE_VBASE, &g_console_config);
imx_uart_configure(IMX_CONSOLE_VBASE, &g_console_config);
#endif
#endif /* IMX_HAVE_UART */
#endif /* CONFIG_SUPPRESS_UART_CONFIG */

14
arch/arm/src/imx6/imx_serial.c
View File

@ -601,7 +601,7 @@ static int imx_attach(struct uart_dev_s *dev)
{
/* Configure as a (high) level interrupt */
(void)arm_gic_irq_trigger(priv->irq, false);
arm_gic_irq_trigger(priv->irq, false);
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
@ -922,19 +922,19 @@ void imx_earlyserialinit(void)
void up_serialinit(void)
{
#ifdef CONSOLE_DEV
(void)uart_register("/dev/console", &CONSOLE_DEV);
uart_register("/dev/console", &CONSOLE_DEV);
#endif
#ifdef TTYS0_DEV
(void)uart_register("/dev/ttyS0", &TTYS0_DEV);
uart_register("/dev/ttyS0", &TTYS0_DEV);
# ifdef TTYS1_DEV
(void)uart_register("/dev/ttyS1", &TTYS1_DEV);
uart_register("/dev/ttyS1", &TTYS1_DEV);
# ifdef TTYS2_DEV
(void)uart_register("/dev/ttyS2", &TTYS2_DEV);
uart_register("/dev/ttyS2", &TTYS2_DEV);
# ifdef TTYS3_DEV
(void)uart_register("/dev/ttyS3", &TTYS2_DEV);
uart_register("/dev/ttyS3", &TTYS2_DEV);
# ifdef TTYS4_DEV
(void)uart_register("/dev/ttyS4", &TTYS2_DEV);
uart_register("/dev/ttyS4", &TTYS2_DEV);
# endif
# endif
# endif

4
arch/arm/src/imx6/imx_timerisr.c
View File

@ -256,11 +256,11 @@ void arm_timer_initialize(void)
/* Configure as a (rising) edge-triggered interrupt */
(void)arm_gic_irq_trigger(IMX_IRQ_GPT, true);
arm_gic_irq_trigger(IMX_IRQ_GPT, true);
/* Attach the timer interrupt vector */
(void)irq_attach(IMX_IRQ_GPT, (xcpt_t)imx_timerisr, NULL);
irq_attach(IMX_IRQ_GPT, (xcpt_t)imx_timerisr, NULL);
/* Enable all three GPT output compare interrupts */

72
arch/arm/src/imxrt/imxrt_edma.c
View File

@ -185,26 +185,12 @@ static struct imxrt_edmatcd_s g_tcd_pool[CONFIG_IMXRT_EDMA_NTCD]
static void imxrt_takechsem(void)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&g_edma.chsem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR || ret == -ECANCELED);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&g_edma.chsem);
}
static inline void imxrt_givechsem(void)
{
(void)nxsem_post(&g_edma.chsem);
nxsem_post(&g_edma.chsem);
}
/****************************************************************************
@ -218,26 +204,12 @@ static inline void imxrt_givechsem(void)
#if CONFIG_IMXRT_EDMA_NTCD > 0
static void imxrt_takedsem(void)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&g_edma.dsem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR || ret == -ECANCELED);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&g_edma.dsem);
}
static inline void imxrt_givedsem(void)
{
(void)nxsem_post(&g_edma.dsem);
nxsem_post(&g_edma.dsem);
}
#endif
@ -296,7 +268,7 @@ static void imxrt_tcd_free(struct imxrt_edmatcd_s *tcd)
flags = spin_lock_irqsave();
sq_addlast((sq_entry_t *)tcd, &g_tcd_free);
(void)imxrt_givedsem();
imxrt_givedsem();
spin_unlock_irqrestore(flags);
}
#endif
@ -811,26 +783,26 @@ void weak_function up_dma_initialize(void)
* NOTE that there are only 16 vectors for 32 DMA channels.
*/
(void)irq_attach(IMXRT_IRQ_EDMA0_16, imxrt_edma_interrupt, &g_edma.dmach[0]);
(void)irq_attach(IMXRT_IRQ_EDMA1_17, imxrt_edma_interrupt, &g_edma.dmach[1]);
(void)irq_attach(IMXRT_IRQ_EDMA2_18, imxrt_edma_interrupt, &g_edma.dmach[2]);
(void)irq_attach(IMXRT_IRQ_EDMA3_19, imxrt_edma_interrupt, &g_edma.dmach[3]);
(void)irq_attach(IMXRT_IRQ_EDMA4_20, imxrt_edma_interrupt, &g_edma.dmach[4]);
(void)irq_attach(IMXRT_IRQ_EDMA5_21, imxrt_edma_interrupt, &g_edma.dmach[5]);
(void)irq_attach(IMXRT_IRQ_EDMA6_22, imxrt_edma_interrupt, &g_edma.dmach[6]);
(void)irq_attach(IMXRT_IRQ_EDMA7_23, imxrt_edma_interrupt, &g_edma.dmach[7]);
(void)irq_attach(IMXRT_IRQ_EDMA8_24, imxrt_edma_interrupt, &g_edma.dmach[8]);
(void)irq_attach(IMXRT_IRQ_EDMA9_25, imxrt_edma_interrupt, &g_edma.dmach[9]);
(void)irq_attach(IMXRT_IRQ_EDMA10_26, imxrt_edma_interrupt, &g_edma.dmach[10]);
(void)irq_attach(IMXRT_IRQ_EDMA11_27, imxrt_edma_interrupt, &g_edma.dmach[11]);
(void)irq_attach(IMXRT_IRQ_EDMA12_28, imxrt_edma_interrupt, &g_edma.dmach[12]);
(void)irq_attach(IMXRT_IRQ_EDMA13_29, imxrt_edma_interrupt, &g_edma.dmach[13]);
(void)irq_attach(IMXRT_IRQ_EDMA14_30, imxrt_edma_interrupt, &g_edma.dmach[14]);
(void)irq_attach(IMXRT_IRQ_EDMA15_31, imxrt_edma_interrupt, &g_edma.dmach[15]);
irq_attach(IMXRT_IRQ_EDMA0_16, imxrt_edma_interrupt, &g_edma.dmach[0]);
irq_attach(IMXRT_IRQ_EDMA1_17, imxrt_edma_interrupt, &g_edma.dmach[1]);
irq_attach(IMXRT_IRQ_EDMA2_18, imxrt_edma_interrupt, &g_edma.dmach[2]);
irq_attach(IMXRT_IRQ_EDMA3_19, imxrt_edma_interrupt, &g_edma.dmach[3]);
irq_attach(IMXRT_IRQ_EDMA4_20, imxrt_edma_interrupt, &g_edma.dmach[4]);
irq_attach(IMXRT_IRQ_EDMA5_21, imxrt_edma_interrupt, &g_edma.dmach[5]);
irq_attach(IMXRT_IRQ_EDMA6_22, imxrt_edma_interrupt, &g_edma.dmach[6]);
irq_attach(IMXRT_IRQ_EDMA7_23, imxrt_edma_interrupt, &g_edma.dmach[7]);
irq_attach(IMXRT_IRQ_EDMA8_24, imxrt_edma_interrupt, &g_edma.dmach[8]);
irq_attach(IMXRT_IRQ_EDMA9_25, imxrt_edma_interrupt, &g_edma.dmach[9]);
irq_attach(IMXRT_IRQ_EDMA10_26, imxrt_edma_interrupt, &g_edma.dmach[10]);
irq_attach(IMXRT_IRQ_EDMA11_27, imxrt_edma_interrupt, &g_edma.dmach[11]);
irq_attach(IMXRT_IRQ_EDMA12_28, imxrt_edma_interrupt, &g_edma.dmach[12]);
irq_attach(IMXRT_IRQ_EDMA13_29, imxrt_edma_interrupt, &g_edma.dmach[13]);
irq_attach(IMXRT_IRQ_EDMA14_30, imxrt_edma_interrupt, &g_edma.dmach[14]);
irq_attach(IMXRT_IRQ_EDMA15_31, imxrt_edma_interrupt, &g_edma.dmach[15]);
/* Attach the DMA error interrupt vector */
(void)irq_attach(IMXRT_IRQ_EDMA_ERROR, imxrt_error_interrupt, NULL);
irq_attach(IMXRT_IRQ_EDMA_ERROR, imxrt_error_interrupt, NULL);
/* Disable and clear all error interrupts */

18
arch/arm/src/imxrt/imxrt_ehci.c
View File

@ -1022,21 +1022,7 @@ static int ehci_wait_usbsts(uint32_t maskbits, uint32_t donebits,
static void imxrt_takesem(sem_t *sem)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(sem);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(sem);
}
/****************************************************************************
@ -1652,7 +1638,7 @@ static void imxrt_qh_enqueue(struct imxrt_qh_s *qhead, struct imxrt_qh_s *qh)
*/
qh->fqp = qh->hw.overlay.nqp;
(void)imxrt_qh_dump(qh, NULL, NULL);
imxrt_qh_dump(qh, NULL, NULL);
/* Add the new QH to the head of the asynchronous queue list.
*

16
arch/arm/src/imxrt/imxrt_enc.c
View File

@ -560,21 +560,7 @@ void imxrt_enc_clock_disable (uint32_t base)
static inline void imxrt_enc_sem_wait(FAR struct imxrt_enc_lowerhalf_s *priv)
{
int ret;
do
{
/* Take the semaphore (perhaps waiting) */
ret = nxsem_wait(&priv->sem_excl);
/* The only case that an error should occur here is if the wait was
* awakened by a signal.
*/
DEBUGASSERT(ret == OK || ret == -EINTR);
}
while (ret == -EINTR);
nxsem_wait_uninterruptible(&priv->sem_excl);
}
/************************************************************************************

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