Board should specify multipliers, not bit settings

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1109 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2008-10-31 22:38:28 +00:00
parent f0ed24d9a9
commit 6a42e356da

View File

@ -104,11 +104,11 @@
*/
#undef STR71X_PLL1IN_DIV2 /* Don't divide main OSC by two */
#define STR71X_PLL1OUT_MUL STR71X_RCCUPLL1CR_MUL16 /* PLL1OUT = 16 * CLK2 */
#define STR71X_PLL1OUT_DIV STR71X_RCCUPLL1CR_DIV2 /* PLL1OUT = CLK2 / 2 */
#define STR71X_APB1_DIV STR71X_PCUPDIVR_APB1DIV1 /* PCLK1 = RCLK */
#define STR71X_APB2_DIV STR71X_PCUPDIVR_APB1DIV1 /* PCLK2 = RCLK */
#define STR71X_MCLK_DIV STR71X_PCUMDIVR_DIV1 /* MCLK = RCLK */
#define STR71X_PLL1OUT_MUL 16 /* PLL1OUT = 16 * CLK2 */
#define STR71X_PLL1OUT_DIV 2 /* PLL1OUT = CLK2 / 2 */
#define STR71X_APB1_DIV 1 /* PCLK1 = RCLK */
#define STR71X_APB2_DIV 1 /* PCLK2 = RCLK */
#define STR71X_MCLK_DIV 1 /* MCLK = RCLK */
/* PLL2 Setup -- only needed for HDLC or USB
*
@ -118,8 +118,8 @@
*/
#undef STR71X_USBIN_PLL2 /* USB input is USB clock */
#define STR71X_PLL2OUT_MUL STR71X_PCUPPL2CR_MUL12 /* PLL2OUT = 12 * HCLK */
#define STR71X_PLL2OUT_DIV STR71X_PCUPPL2CR_DIV1 /* PLL2OUT = HCLK / 1 */
#define STR71X_PLL2OUT_MUL 12 /* PLL2OUT = 12 * HCLK */
#define STR71X_PLL2OUT_DIV 1 /* PLL2OUT = HCLK / 1 */
/* LED definitions **********************************************************/