From 6a43d758786e81f90cf119bf05883fce2d4bff5d Mon Sep 17 00:00:00 2001 From: patacongo Date: Thu, 8 Nov 2012 18:05:39 +0000 Subject: [PATCH] Support for non-common vectors from Freddie Chopin git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5323 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/include/stm32/stm32f10xxx_irq.h | 12 ++-- arch/arm/src/stm32/chip/stm32f10xxx_vectors.h | 64 ++++++++++++++++++- 2 files changed, 71 insertions(+), 5 deletions(-) diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h index 0a7c230bce..7c3f7cf958 100644 --- a/arch/arm/include/stm32/stm32f10xxx_irq.h +++ b/arch/arm/include/stm32/stm32f10xxx_irq.h @@ -62,7 +62,7 @@ */ /* Value line devices */ - + #if defined(CONFIG_STM32_VALUELINE) # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ @@ -83,7 +83,10 @@ # define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */ # define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */ # define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */ - /* 19-22: reserved */ +# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */ +# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */ +# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */ +# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */ # define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */ # define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */ # define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */ @@ -110,9 +113,10 @@ # define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */ # define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */ # define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */ - /* 46-47: reserved */ +# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */ +# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */ # define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */ - /* 49: reserved */ +# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */ # define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */ # define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */ # define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */ diff --git a/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h index 1259f2fce8..24822c37d3 100644 --- a/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h +++ b/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h @@ -56,7 +56,69 @@ # define ARMV7M_PERIPHERAL_INTERRUPTS 61 #else -# error This target requires CONFIG_ARMV7M_CMNVECTOR + +VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* Vector 16+0: Window Watchdog interrupt */ +VECTOR(stm32_pvd, STM32_IRQ_PVD) /* Vector 16+1: PVD through EXTI Line detection interrupt */ +VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* Vector 16+2: Tamper interrupt */ +VECTOR(stm32_rtc, STM32_IRQ_RTC) /* Vector 16+3: RTC Wakeup through EXTI line interrupt */ +VECTOR(stm32_flash, STM32_IRQ_FLASH) /* Vector 16+4: Flash global interrupt */ +VECTOR(stm32_rcc, STM32_IRQ_RCC) /* Vector 16+5: RCC global interrupt */ +VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* Vector 16+6: EXTI Line 0 interrupt */ +VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* Vector 16+7: EXTI Line 1 interrupt */ +VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* Vector 16+8: EXTI Line 2 interrupt */ +VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* Vector 16+9: EXTI Line 3 interrupt */ +VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* Vector 16+10: EXTI Line 4 interrupt */ +VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* Vector 16+11: DMA1 Channel 1 global interrupt */ +VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* Vector 16+12: DMA1 Channel 2 global interrupt */ +VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* Vector 16+13: DMA1 Channel 3 global interrupt */ +VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* Vector 16+14: DMA1 Channel 4 global interrupt */ +VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* Vector 16+15: DMA1 Channel 5 global interrupt */ +VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* Vector 16+16: DMA1 Channel 6 global interrupt */ +VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* Vector 16+17: DMA1 Channel 7 global interrupt */ +VECTOR(stm32_adc1, STM32_IRQ_ADC1) /* Vector 16+18: ADC1 global interrupt */ +UNUSED(STM32_IRQ_RESERVED0) /* Vector 16+19: Reserved 0 */ +UNUSED(STM32_IRQ_RESERVED1) /* Vector 16+20: Reserved 1 */ +UNUSED(STM32_IRQ_RESERVED2) /* Vector 16+21: Reserved 2 */ +UNUSED(STM32_IRQ_RESERVED3) /* Vector 16+22: Reserved 3 */ +VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* Vector 16+23: EXTI Line[9:5] interrupts */ +VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */ +VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */ +VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */ +VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* Vector 16+27: TIM1 Capture Compare interrupt */ +VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* Vector 16+28: TIM2 global interrupt */ +VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* Vector 16+29: TIM3 global interrupt */ +VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* Vector 16+30: TIM4 global interrupt */ +VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* Vector 16+31: I2C1 event interrupt */ +VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* Vector 16+32: I2C1 error interrupt */ +VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* Vector 16+33: I2C2 event interrupt */ +VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* Vector 16+34: I2C2 error interrupt */ +VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* Vector 16+35: SPI1 global interrupt */ +VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* Vector 16+36: SPI2 global interrupt */ +VECTOR(stm32_usart1, STM32_IRQ_USART1) /* Vector 16+37: USART1 global interrupt */ +VECTOR(stm32_usart2, STM32_IRQ_USART2) /* Vector 16+38: USART2 global interrupt */ +VECTOR(stm32_usart3, STM32_IRQ_USART3) /* Vector 16+39: USART3 global interrupt */ +VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* Vector 16+40: EXTI Line[15:10] interrupts */ +VECTOR(stm32_rtcalr, STM32_IRQ_RTCALR) /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */ +VECTOR(stm32_cec, STM32_IRQ_CEC) /* Vector 16+42: CEC global interrupt */ +VECTOR(stm32_tim12, STM32_IRQ_TIM12) /* Vector 16+43: TIM12 global interrupt */ +VECTOR(stm32_tim13, STM32_IRQ_TIM13) /* Vector 16+44: TIM13 global interrupt */ +VECTOR(stm32_tim14, STM32_IRQ_TIM14) /* Vector 16+45: TIM14 global interrupt */ +UNUSED(STM32_IRQ_RESERVED4) /* Vector 16+46: Reserved 4 */ +UNUSED(STM32_IRQ_RESERVED5) /* Vector 16+47: Reserved 5 */ +VECTOR(stm32_fsmc, STM32_IRQ_FSMC) /* Vector 16+48: FSMC global interrupt */ +UNUSED(STM32_IRQ_RESERVED6) /* Vector 16+49: Reserved 6 */ +VECTOR(stm32_tim5, STM32_IRQ_TIM5) /* Vector 16+50: TIM5 global interrupt */ +VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* Vector 16+51: SPI3 global interrupt */ +VECTOR(stm32_uart4, STM32_IRQ_UART4) /* Vector 16+52: USART2 global interrupt */ +VECTOR(stm32_uart5, STM32_IRQ_UART5) /* Vector 16+53: USART5 global interrupt */ +VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* Vector 16+54: TIM6 global interrupt */ +VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* Vector 16+55: TIM7 global interrupt */ +VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* Vector 16+56: DMA2 Channel 1 global interrupt */ +VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* Vector 16+57: DMA2 Channel 2 global interrupt */ +VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* Vector 16+58: DMA2 Channel 3 global interrupt */ +VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45) /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */ +VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* Vector 16+60: DMA2 Channel 5 global interrupt */ + # endif /* CONFIG_ARMV7M_CMNVECTOR */ #elif defined(CONFIG_STM32_CONNECTIVITYLINE)