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Finish SSC header file

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3019 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-10-15 15:05:30 +00:00
parent 4b23c7efa1
commit 6a4601776f
1 changed files with 89 additions and 28 deletions
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117
arch/avr/src/at91uc3/at91uc3_ssc.h
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@ -108,9 +108,9 @@
# define SSC_RCMR_CKS_RXCLK (2 << SSC_RCMR_CKS_SHIFT) /* RX_CLOCK pin */
#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None Input-only */
# define SSC_RCMR_CKO_CONT (1 << SSC_RCMR_CKO_SHIFT) /* Continuous receive clock Output */
# define SSC_RCMR_CKO_XFR (2 << SSC_RCMR_CKO_SHIFT) /* Receive clock only during data transfers Output */
# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None (Input-only) */
# define SSC_RCMR_CKO_CONT (1 << SSC_RCMR_CKO_SHIFT) /* Continuous receive clock */
# define SSC_RCMR_CKO_XFR (2 << SSC_RCMR_CKO_SHIFT) /* Receive clock only during data transfers */
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */
#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT)
@ -136,59 +136,120 @@
/* Receive Frame Mode Register Bit-field Definitions */
#define SSC_RFMR_
#define SSC_RFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
#define SSC_RFMR_DATLEN_MASK (0x1f << SSC_RFMR_DATLEN_SHIFT)
#define SSC_RFMR_LOOP (1 << 5) /* Bit 5: Loop Mode */
#define SSC_RFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */
#define SSC_RFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */
#define SSC_RFMR_DATNB_MASK (15 << SSC_RFMR_DATNB_SHIFT)
#define SSC_RFMR_FSLEN_SHIFT (16) /* Bits 16-19: Receive Frame Sync Length */
#define SSC_RFMR_FSLEN_MASK (15 << SSC_RFMR_FSLEN_SHIFT)
#define SSC_RFMR_FSOS_SHIFT (20) /* Bits 20-22: Receive Frame Sync Output Selection */
#define SSC_RFMR_FSOS_MASK (7 << SSC_RFMR_FSOS_SHIFT)
# define SSC_RFMR_FSOS_NONE (0 << SSC_RFMR_FSOS_SHIFT) /* None (Input-only )*/
# define SSC_RFMR_FSOS_NEGP (1 << SSC_RFMR_FSOS_SHIFT) /* Negative Pulse */
# define SSC_RFMR_FSOS_POSP (2 << SSC_RFMR_FSOS_SHIFT) /* Positive Pulse */
# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* Driven Low during data transfer */
# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* Driven High during data transfer */
# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* Toggling at each start of data transfer */
#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Receive Frame Sync Edge Detection */
#define SSC_RFMR_FSLENHI_SHIFT (28) /* Bits 28-31: Receive Frame Sync Length High Part */
#define SSC_RFMR_FSLENHI_MASK (15 << SSC_RFMR_FSLENHI_SHIFT)
/* Transmit Clock Mode Register Bit-field Definitions */
#define SSC_TCMR_
#define SSC_TCMR_CKS_SHIFT (0) /* Bits 0-1: Transmit Clock Selection */
#define SSC_TCMR_CKS_MASK (3 << SSC_TCMR_CKS_SHIFT)
# define SSC_TCMR_CKS_DIVCLK (0 << SSC_TCMR_CKS_SHIFT) /* Divided clock */
# define SSC_TCMR_CKS_TXCLK (1 << SSC_TCMR_CKS_SHIFT) /* RX_CLOCK clock signal */
# define SSC_TCMR_CKS_RXCLK (2 << SSC_TCMR_CKS_SHIFT) /* TX_CLOCK pin */
#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None (Input-only) */
# define SSC_TCMR_CKO_CONT (1 << SSC_TCMR_CKO_SHIFT) /* Continuous transmit clock Output */
# define SSC_TCMR_CKO_XFR (2 << SSC_TCMR_CKO_SHIFT) /* Transmit clock only during data transfers Output */
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */
#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT)
# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continous clock */
# define SSC_TCMR_CKG_LOW (1 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC low */
# define SSC_TCMR_CKG_HIGH (2 << SSC_TCMR_CKG_SHIFT) /* Enable if TX_FRAME_SYNC high */
#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */
#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT)
# define SSC_TCMR_START_CONT (0 << SSC_TCMR_START_SHIFT) /* Continuous */
# define SSC_TCMR_START_XMTSTART (1 << SSC_TCMR_START_SHIFT) /* Receive start */
# define SSC_TCMR_START_LOW (2 << SSC_TCMR_START_SHIFT) /* TX_FRAME_SYNC low */
# define SSC_TCMR_START_HIGH (3 << SSC_TCMR_START_SHIFT) /* TX_FRAME_SYNC high */
# define SSC_TCMR_START_FALLING (4 << SSC_TCMR_START_SHIFT) /* Falling TX_FRAME_SYNC */
# define SSC_TCMR_START_RISING (5 << SSC_TCMR_START_SHIFT) /* Rising TX_FRAME_SYNC */
# define SSC_TCMR_START_CHANGE (6 << SSC_TCMR_START_SHIFT) /* TX_FRAME_SYNC change */
# define SSC_TCMR_START_BOTH (7 << SSC_TCMR_START_SHIFT) /* Any edge TX_FRAME_SYNC */
#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */
#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT)
#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */
#define SSC_TCMR_PERIOD_MASK (0xff << SSC_TCMR_PERIOD_SHIFT)
/* Transmit Frame Mode Register Bit-field Definitions */
#define SSC_TFMR_
#define SSC_TFMR_DATLEN_SHIFT (0) /* Bits 0-4: Data Length */
#define SSC_TFMR_DATLEN_MASK (0x1f << SSC_TFMR_DATLEN_SHIFT)
#define SSC_TFMR_DATDEF (1 << 5) /* Bit 5: Data Default Value */
#define SSC_TFMR_MSBF (1 << 7) /* Bit 7: Most Significant Bit First */
#define SSC_TFMR_DATNB_SHIFT (8) /* Bits 8-11: Data Number per Frame */
#define SSC_TFMR_DATNB_MASK (15 << SSC_TFMR_DATNB_SHIFT)
#define SSC_TFMR_FSLEN_SHIFT (16) /* Bits 16-19: Transmit Frame Sync Length */
#define SSC_TFMR_FSLEN_MASK (15 << SSC_TFMR_FSLEN_SHIFT)
#define SSC_TFMR_FSOS_SHIFT (20) /* Bits 20-22: Transmit Frame Sync Data Enable */
#define SSC_TFMR_FSOS_MASK (7 << SSC_TFMR_FSOS_SHIFT)
# define SSC_TFMR_FSOS_NONE (0 << SSC_TFMR_FSOS_SHIFT) /* None (Input-only )*/
# define SSC_TFMR_FSOS_NEGP (1 << SSC_TFMR_FSOS_SHIFT) /* Negative Pulse */
# define SSC_TFMR_FSOS_POSP (2 << SSC_TFMR_FSOS_SHIFT) /* Positive Pulse */
# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* Driven Low during data transfer */
# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* Driven High during data transfer */
# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* Toggling at each start of data transfer */
#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Transmit Frame Sync Data Enable */
#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Transmit Frame Sync Edge Detection */
#define SSC_TFMR_FSLENHI_SHIFT (28) /* Bits 28-31: Transmit Frame Sync Length High Part */
#define SSC_TFMR_FSLENHI_MASK (15 << SSC_TFMR_FSLENHI_SHIFT)
/* Receive Holding Register Bit-field Definitions */
#define SSC_RHR_
/* Transmit Holding Register Bit-field Definitions */
#define SSC_THR_
/* These register hold 32-bit values with no bit-fields */
/* Receive Synchronization Holding Register Bit-field Definitions */
#define SSC_RSHR_
#define SSC_RSHR_MASK (0xffff)
/* Transmit Synchronization Holding Register Bit-field Definitions */
#define SSC_TSHR_
#define SSC_TSHR_MASK (0xffff)
/* Receive Compare 0 Register Bit-field Definitions */
#define SSC_RC0R_
#define SSC_RC0R_MASK (0xffff)
/* Receive Compare 1 Register Bit-field Definitions */
#define SSC_RC1R_
/* Status Register Bit-field Definitions */
#define SSC_SR_
#define SSC_RC1R_MASK (0xffff)
/* Interrupt Enable Register Bit-field Definitions */
#define SSC_IER_
/* Interrupt Disable Register Bit-field Definitions */
#define SSC_IDR_
/* Interrupt Mask Register Bit-field Definitions */
#define SSC_IMR_
#define SSC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready */
#define SSC_INT_TXEMPTY (1 << 1) /* Bit 1: Transmit Empty */
#define SSC_INT_RXRDY (1 << 4) /* Bit 4: Receive Ready */
#define SSC_INT_OVRUN (1 << 5) /* Bit 5: Receive Overrun */
#define SSC_INT_CP0 (1 << 8) /* Bit 8: Compare 0 */
#define SSC_INT_CP1 (1 << 9) /* Bit 9: Compare 1 */
#define SSC_INT_TXSYN (1 << 10) /* Bit 10: Transmit Sync */
#define SSC_INT_RXSYN (1 << 11) /* Bit 11: Receive Sync */
(1 << xxx) /* Bit xxx:
_SHIFT (xx) /* Bits xx-xx:
_MASK (xx << xx)
/* Status Register Bit-field Definitions (Only) */
#define SSC_SR_TXEN (1 << 16) /* Bit 16: Transmit Enable */
#define SSC_SR_RXEN (1 << 17) /* Bit 17: Receive Enable */
/************************************************************************************
* Public Types