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arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training

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Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen 2023-08-10 10:03:27 +03:00 committed by Xiang Xiao
parent cd9ac3cf70
commit 6a5d00f68c
4 changed files with 5 additions and 0 deletions
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1
arch/risc-v/src/mpfs/hardware/mpfs_sgmii.h
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@ -601,6 +601,7 @@
#define MPFS_CFG_DDR_SGMII_PHY_RPC20 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC20_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_RPC145 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC145_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_RPC147 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC147_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_RPC156 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC156_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_RPC166 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC166_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_RPC168 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC168_OFFSET)
#define MPFS_CFG_DDR_SGMII_PHY_RPC220 (MPFS_CFG_DDR_SGMII_PHY_BASE + MPFS_CFG_DDR_SGMII_PHY_RPC220_OFFSET)

2
arch/risc-v/src/mpfs/mpfs_ddr.c
View File

@ -582,6 +582,8 @@ static void mpfs_set_ddr_rpc_regs(struct mpfs_ddr_priv_s *priv)
#endif
putreg32(LIBERO_SETTING_RPC_156_VALUE, MPFS_CFG_DDR_SGMII_PHY_RPC156);
putreg32(0x2, MPFS_CFG_DDR_SGMII_PHY_RPC27);
putreg32(0, MPFS_CFG_DDR_SGMII_PHY_RPC203);

1
boards/risc-v/mpfs/icicle/include/board_liberodefs.h
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@ -82,6 +82,7 @@
#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006
#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000002
#define LIBERO_SETTING_RPC_ODT_CLK 0x00000002
#define LIBERO_SETTING_RPC_156_VALUE 0x00000001
#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000f00
#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000fff
#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000fe6

1
boards/risc-v/mpfs/m100pfsevp/include/board_liberodefs.h
View File

@ -80,6 +80,7 @@
#define LIBERO_SETTING_RPC_ODT_DQS 0x00000006
#define LIBERO_SETTING_RPC_ODT_ADDCMD 0x00000006
#define LIBERO_SETTING_RPC_ODT_CLK 0x00000006
#define LIBERO_SETTING_RPC_156_VALUE 0x00000001
#define LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 0x00000000
#define LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 0x00000003
#define LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 0x00000dc4