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SAMV7: Add an untested RSWDT driver

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This commit is contained in:
Gregory Nutt 2015-12-06 09:56:45 -06:00
parent 8f55ec5c69
commit 6a9876f960
5 changed files with 90 additions and 10 deletions
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8
arch/arm/include/samv7/same70_irq.h
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@ -54,7 +54,7 @@
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT0 (4) /* Watchdog Timer 0 */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EFC (6) /* Embedded Flash Controller */
#define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */
@ -113,7 +113,7 @@
#define SAM_PID_PWM1 (60) /* Pulse Width Modulation Controller 1 */
#define SAM_PID_FPU (61) /* ARM Floating Point Unit interrupt */
#define SAM_PID_SDRAMC (62) /* SDRAM Controller */
#define SAM_PID_WDT1 (63) /* Watchdog Timer 1 */
#define SAM_PID_RSWDT (63) /* Reinforced Safety Watchdog Timer */
#define SAM_PID_CCW (64) /* ARM Cache ECC Warning */
#define SAM_PID_CCF (65) /* ARM Cache ECC Fault */
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
@ -128,7 +128,7 @@
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT0 (SAM_IRQ_EXTINT+SAM_PID_WDT0) /* Watchdog Timer 0 */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer */
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EFC) /* Embedded Flash Controller */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */
@ -187,7 +187,7 @@
#define SAM_IRQ_PWM1 (SAM_IRQ_EXTINT+SAM_PID_PWM1) /* Pulse Width Modulation Controller 1 */
#define SAM_IRQ_FPU (SAM_IRQ_EXTINT+SAM_PID_FPU) /* ARM Floating Point Unit interrupt */
#define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* SDRAM Controller */
#define SAM_IRQ_WDT1 (SAM_IRQ_EXTINT+SAM_PID_WDT1) /* Watchdog Timer 1 */
#define SAM_IRQ_RSWDT (SAM_IRQ_EXTINT+SAM_PID_RSWDT) /* Reinforced Safety Watchdog Timer */
#define SAM_IRQ_CCW (SAM_IRQ_EXTINT+SAM_PID_CCW) /* ARM Cache ECC Warning */
#define SAM_IRQ_CCF (SAM_IRQ_EXTINT+SAM_PID_CCF) /* ARM Cache ECC Fault */
#define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */

8
arch/arm/include/samv7/samv71_irq.h
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@ -54,7 +54,7 @@
#define SAM_PID_RSTC (1) /* Reset Controller */
#define SAM_PID_RTC (2) /* Real Time Clock */
#define SAM_PID_RTT (3) /* Real Time Timer */
#define SAM_PID_WDT0 (4) /* Watchdog Timer 0 */
#define SAM_PID_WDT (4) /* Watchdog Timer */
#define SAM_PID_PMC (5) /* Power Management Controller */
#define SAM_PID_EFC (6) /* Embedded Flash Controller */
#define SAM_PID_UART0 (7) /* Universal Asynchronous Receiver Transmitter 0 */
@ -113,7 +113,7 @@
#define SAM_PID_PWM1 (60) /* Pulse Width Modulation Controller 1 */
#define SAM_PID_FPU (61) /* ARM Floating Point Unit interrupt */
#define SAM_PID_SDRAMC (62) /* SDRAM Controller */
#define SAM_PID_WDT1 (63) /* Watchdog Timer 1 */
#define SAM_PID_RSWDT (63) /* Reinforced Safetry Watchdog Timer */
#define SAM_PID_CCW (64) /* ARM Cache ECC Warning */
#define SAM_PID_CCF (65) /* ARM Cache ECC Fault */
#define SAM_PID_EMACQ1 (66) /* EMAC Queue 1 Interrupt */
@ -128,7 +128,7 @@
#define SAM_IRQ_RSTC (SAM_IRQ_EXTINT+SAM_PID_RSTC) /* Reset Controller */
#define SAM_IRQ_RTC (SAM_IRQ_EXTINT+SAM_PID_RTC) /* Real Time Clock */
#define SAM_IRQ_RTT (SAM_IRQ_EXTINT+SAM_PID_RTT) /* Real Time Timer */
#define SAM_IRQ_WDT0 (SAM_IRQ_EXTINT+SAM_PID_WDT0) /* Watchdog Timer 0 */
#define SAM_IRQ_WDT (SAM_IRQ_EXTINT+SAM_PID_WDT) /* Watchdog Timer*/
#define SAM_IRQ_PMC (SAM_IRQ_EXTINT+SAM_PID_PMC) /* Power Management Controller */
#define SAM_IRQ_EEFC0 (SAM_IRQ_EXTINT+SAM_PID_EFC) /* Embedded Flash Controller */
#define SAM_IRQ_UART0 (SAM_IRQ_EXTINT+SAM_PID_UART0) /* Universal Asynchronous Receiver Transmitter 0 */
@ -187,7 +187,7 @@
#define SAM_IRQ_PWM1 (SAM_IRQ_EXTINT+SAM_PID_PWM1) /* Pulse Width Modulation Controller 1 */
#define SAM_IRQ_FPU (SAM_IRQ_EXTINT+SAM_PID_FPU) /* ARM Floating Point Unit interrupt */
#define SAM_IRQ_SDRAMC (SAM_IRQ_EXTINT+SAM_PID_SDRAMC) /* SDRAM Controller */
#define SAM_IRQ_WDT1 (SAM_IRQ_EXTINT+SAM_PID_WDT1) /* Watchdog Timer 1 */
#define SAM_IRQ_RSWDT (SAM_IRQ_EXTINT+SAM_PID_RSWDT) /* Reinforced Safety Watchdog Timer */
#define SAM_IRQ_CCW (SAM_IRQ_EXTINT+SAM_PID_CCW) /* ARM Cache ECC Warning */
#define SAM_IRQ_CCF (SAM_IRQ_EXTINT+SAM_PID_CCF) /* ARM Cache ECC Fault */
#define SAM_IRQ_EMACQ1 (SAM_IRQ_EXTINT+SAM_PID_EMACQ1) /* EMAC Queue 1 Interrupt */

76
arch/arm/src/samv7/Kconfig
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@ -576,6 +576,82 @@ config SAMV7_GPIOE_IRQ
endif # SAMV7_GPIO_IRQ
if SAMV7_WDT || SAMV7_RSWDT
menu "Watchdog Configuration"
if SAMV7_WDT
comment "Watchdog Configuration"
config SAMV7_WDT_INTERRUPT
bool "Interrupt on timeout"
default n
---help---
The normal behavior is to reset everything when a watchdog timeout
occurs. An alternative behavior is to simply interrupt when the
timeout occurs. This setting enables that alternative behavior.
config SAMV7_WDT_DEBUGHALT
bool "Halt on DEBUG"
default y if DEBUG
default n if !DEBUG
---help---
Halt the watchdog timer in the debug state
config SAMV7_WDT_IDLEHALT
bool "Halt in IDLE"
default y
---help---
Halt the watchdog timer in the IDLE state
config SAMV7_WDT_REGDEBUG
bool "Register level debug"
default n
depends on DEBUG
---help---
Enable low-level register debug output
endif # SAMV7_WDT
if SAMV7_RSWDT
comment "Reinforced Safety Watchdog Configuration"
config SAMV7_RSWDT_INTERRUPT
bool "Interrupt on timeout"
default n
---help---
The normal behavior is to reset everything when a watchdog timeout
occurs. An alternative behavior is to simply interrupt when the
timeout occurs. This setting enables that alternative behavior.
config SAMV7_RSWDT_DEBUGHALT
bool "Halt on DEBUG"
default y if DEBUG
default n if !DEBUG
---help---
Halt the watchdog timer in the debug state
config SAMV7_RSWDT_IDLEHALT
bool "Halt in IDLE"
default y
---help---
Halt the watchdog timer in the IDLE state
config SAMV7_RSWDT_REGDEBUG
bool "Register level debug"
default n
depends on DEBUG
---help---
Enable low-level register debug output
endif # SAMV7_RSWDT
endmenu # Watchdog configuration
endif # SAMV7_WDT || SAMV7_RSWDT
menuconfig SAMV7_PROGMEM
bool "FLASH program memory"
---help---

4
arch/arm/src/samv7/Make.defs
View File

@ -140,6 +140,10 @@ ifeq ($(CONFIG_SAMV7_WDT),y)
CHIP_CSRCS += sam_wdt.c
endif
ifeq ($(CONFIG_SAMV7_RSWDT),y)
CHIP_CSRCS += sam_rswdt.c
endif
ifeq ($(CONFIG_SAMV7_SPI_MASTER),y)
CHIP_CSRCS += sam_spi.c
endif

4
arch/arm/src/samv7/sam_wdt.c
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@ -695,9 +695,9 @@ int up_wdginitialize(void)
(void)irq_attach(SAM_IRQ_WDT, sam_interrupt);
#endif
/* Register the watchdog driver as /dev/watchdog0 */
/* Register the watchdog driver as /dev/wdt */
(void)watchdog_register("/dev/watchdog0",
(void)watchdog_register("/dev/wdt",
(FAR struct watchdog_lowerhalf_s *)priv);
return OK;
}