diff --git a/arch/arm/src/arm/pg_macros.h b/arch/arm/src/arm/pg_macros.h
index d30adeb106..efc3a4faa6 100644
--- a/arch/arm/src/arm/pg_macros.h
+++ b/arch/arm/src/arm/pg_macros.h
@@ -121,6 +121,7 @@
 #  define MMU_L2_TEXTFLAGS      (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
 #  define MMU_L1_DATAFLAGS      (PMD_TYPE_COARSE|PMD_BIT4)
 #  define MMU_L2_DATAFLAGS      (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
+#  define MMU_L2_ALLOCFLAGS     (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
 #  define MMU_L1_PGTABFLAGS     (PMD_TYPE_COARSE|PMD_BIT4)
 #  define MMU_L2_PGTABFLAGS     (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
 
diff --git a/arch/arm/src/arm/up_allocpage.c b/arch/arm/src/arm/up_allocpage.c
index 1db32592c6..c2a31d09c0 100755
--- a/arch/arm/src/arm/up_allocpage.c
+++ b/arch/arm/src/arm/up_allocpage.c
@@ -209,6 +209,12 @@ int up_allocpage(FAR _TCB *tcb, FAR void **vpage)
       /* Invalidate the instruction TLB corresponding to the virtual address */
 
       tlb_inst_invalidate_single(oldvaddr);
+
+      /* I do not believe that it is necessary to flush the I-Cache in this
+       * case:  The I-Cache uses a virtual address index and, hence, since the
+       * NuttX address space is flat, the cached instruction value should be
+       * correct even if the page mapping is no longer in place.
+       */ 
     }
 
   /* Then convert the index to a (physical) page address. */