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arch/arm64: Add support for Generic Interrupt Controller Version 2

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Currently NuttX on Arm64 supports Generic Interrupt Controller (GIC) Versions 3 and 4: [`arm64_gicv3.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gicv3.c), [`arm64_gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm64/src/common/arm64_gic.h). This PR adds support for GIC Version 2, which is needed by [Pine64 PinePhone](https://lupyuen.github.io/articles/interrupt) based on Allwinner A64 SoC.

This 64-bit implementation of GIC v2 is mostly identical to the existing GIC v2 for 32-bit Armv7-A ([`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c), [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h)), with minor modifications to support 64-bit Registers (Interrupt Context).

-   `arch/arm64/Kconfig`: Under "ARM64 Options", we added an integer option `ARM_GIC_VERSION` ("GIC version") that selects the GIC Version. Valid values are 2, 3 and 4, default is 3.

-   `arch/arm64/src/common/arm64_gicv2.c`: Implements 64-bit GIC v2 based on 32-bit [`armv7-a/arm_gicv2.c`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/arm_gicv2.c) and [`armv7-a/gic.h`](https://github.com/apache/incubator-nuttx/blob/master/arch/arm/src/armv7-a/gic.h), modified to support 64-bit Registers (Interrupt Context).

    Function and Macro Names have not been changed, for easier cross-referencing between the 32-bit and 64-bit implementations of GIC v2.

-   `arch/arm64/src/common/arm64_gicv3.c`: Added Conditional Compilation for GIC v3. This file will not be compiled if `ARM_GIC_VERSION` is 2.

-   `arch/arm64/src/common/arm64_gic.h`: Added the Version Identifier for GIC v2. At startup we read the GIC Version from hardware and verify that it matches `ARM_GIC_VERSION`.

-   `arch/arm64/include/qemu/chip.h`: Added the QEMU Base Addresses for GIC v2.

-   `arch/arm64/src/common/Make.defs`: Added the source file that implements GIC v2.

-   `boards/arm64/qemu/qemu-armv8a/README.txt`: Added the documentation for testing GIC v2 with QEMU.

-   `boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig`: Added the Board Configuration `qemu-armv8a:nsh_gicv2` for testing GIC v2 with QEMU. Identical to `qemu-armv8a:nsh`, except that `ARM_GIC_VERSION` is 2.
This commit is contained in:
Lee Lup Yuen 2022-11-16 15:29:43 +08:00 committed by Brennan Ashton
parent ce1c945136
commit 6aba739f05
8 changed files with 1500 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm64/Kconfig
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@ -95,6 +95,14 @@ config ARM_HAVE_NEON
---help---
Decide whether support NEON instruction
config ARM_GIC_VERSION
int "GIC version"
default 3
range 2 4
---help---
Version of Generic Interrupt Controller (GIC) supported by the
architecture
if ARCH_CHIP_QEMU
source "arch/arm64/src/qemu/Kconfig"
endif

13
arch/arm64/include/qemu/chip.h
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@ -35,9 +35,22 @@
#if defined(CONFIG_ARCH_CHIP_QEMU)
#if CONFIG_ARM_GIC_VERSION == 2
#define CONFIG_GICD_BASE 0x8000000
#define CONFIG_GICR_BASE 0x8010000
#elif CONFIG_ARM_GIC_VERSION == 3 || CONFIG_ARM_GIC_VERSION == 4
#define CONFIG_GICD_BASE 0x8000000
#define CONFIG_GICR_BASE 0x80a0000
#else
#error CONFIG_ARM_GIC_VERSION should be 2, 3 or 4
#endif /* CONFIG_ARM_GIC_VERSION */
#define CONFIG_RAMBANK1_ADDR 0x40000000
#define CONFIG_RAMBANK1_SIZE MB(128)

2
arch/arm64/src/common/Make.defs
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@ -52,7 +52,7 @@ CMN_CSRCS += arm64_sigdeliver.c
# Common C source files ( hardware BSP )
CMN_CSRCS += arm64_mmu.c arm64_arch_timer.c arm64_cache.c
CMN_CSRCS += arm64_doirq.c arm64_gicv3.c arm64_fatal.c
CMN_CSRCS += arm64_doirq.c arm64_gicv2.c arm64_gicv3.c arm64_fatal.c
CMN_CSRCS += arm64_syscall.c arm64_cpu_psci.c
# Use common heap allocation for now (may need to be customized later)

1
arch/arm64/src/common/arm64_gic.h
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@ -99,6 +99,7 @@
* [3:0] - IMPLEMENTATION DEFINED.
*/
#define GICD_PIDR2_ARCH_MASK 0xf0
#define GICD_PIDR2_ARCH_GICV2 0x20
#define GICD_PIDR2_ARCH_GICV3 0x30
#define GICD_PIDR2_ARCH_GICV4 0x40

1389
arch/arm64/src/common/arm64_gicv2.c Normal file
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4
arch/arm64/src/common/arm64_gicv3.c
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@ -36,6 +36,8 @@
#include "arm64_gic.h"
#include "arm64_fatal.h"
#if CONFIG_ARM_GIC_VERSION == 3 || CONFIG_ARM_GIC_VERSION == 4
/***************************************************************************
* Pre-processor Definitions
***************************************************************************/
@ -615,3 +617,5 @@ void arm64_gic_secondary_init(void)
}
#endif
#endif /* CONFIG_ARM_GIC_VERSION == 3 || CONFIG_ARM_GIC_VERSION == 4 */

21
boards/arm64/qemu/qemu-armv8a/README.txt
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@ -4,7 +4,7 @@ README.txt
This board configuration will use QEMU to emulate generic ARM64 v8-A series
hardware platform and provides support for these devices:
- GICv3 interrupt controller
- GICv2 and GICv3 interrupt controllers
- ARM Generic Timer
- PL011 UART controller
@ -41,7 +41,7 @@ Getting Started
$ qemu-system-aarch64 --help
3. Configuring and running
3.1 Single Core
3.1 Single Core (GICv3)
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh
$ make
@ -51,7 +51,7 @@ Getting Started
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
3.2 SMP
3.2 SMP (GICv3)
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_smp
$ make
@ -61,6 +61,16 @@ Getting Started
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
3.3 Single Core (GICv2)
Configuring NuttX and compile:
$ ./tools/configure.sh -l qemu-armv8a:nsh_gicv2
$ make
Running with qemu
$ qemu-system-aarch64 -cpu cortex-a53 -nographic \
-machine virt,virtualization=on,gic-version=2 \
-net none -chardev stdio,id=con,mux=on -serial chardev:con \
-mon chardev=con,mode=readline -kernel ./nuttx
Note:
1. Make sure the aarch64-none-elf toolchain install PATH has been added to environment variable
2. To quit QEMU, type Ctrl + X
@ -70,6 +80,11 @@ Getting Started
Status
======
2022-11-18:
1. Added support for GICv2.
2. Added board configuration for nsh_gicv2.
2022-10-13:
1. Renamed the board configuration name from qemu-a53 to qemu-v8a.

66
boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig Normal file
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@ -0,0 +1,66 @@
#
# This file is autogenerated: PLEASE DO NOT EDIT IT.
#
# You can use "make menuconfig" to make any modifications to the installed .config file.
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
CONFIG_ARCH="arm64"
CONFIG_ARCH_ARM64=y
CONFIG_ARCH_BOARD="qemu-armv8a"
CONFIG_ARCH_BOARD_QEMU_ARMV8A=y
CONFIG_ARCH_CHIP="qemu"
CONFIG_ARCH_CHIP_QEMU=y
CONFIG_ARCH_CHIP_QEMU_A53=y
CONFIG_ARCH_INTERRUPTSTACK=4096
CONFIG_ARM_GIC_VERSION=2
CONFIG_BUILTIN=y
CONFIG_DEBUG_ASSERTIONS=y
CONFIG_DEBUG_ERROR=y
CONFIG_DEBUG_FEATURES=y
CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_SCHED=y
CONFIG_DEBUG_SCHED_ERROR=y
CONFIG_DEBUG_SCHED_INFO=y
CONFIG_DEBUG_SCHED_WARN=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEBUG_WARN=y
CONFIG_DEFAULT_TASK_STACKSIZE=8192
CONFIG_DEV_ZERO=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_EXPERIMENTAL=y
CONFIG_FS_PROCFS=y
CONFIG_FS_ROMFS=y
CONFIG_HAVE_CXX=y
CONFIG_HAVE_CXXINITIALIZE=y
CONFIG_IDLETHREAD_STACKSIZE=8192
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
CONFIG_NSH_READLINE=y
CONFIG_NSH_ROMFSETC=y
CONFIG_PREALLOC_TIMERS=4
CONFIG_PTHREAD_STACK_MIN=8192
CONFIG_QEMU_UART_PL011=y
CONFIG_RAMLOG=y
CONFIG_RAM_SIZE=134217728
CONFIG_RAM_START=0x40000000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y
CONFIG_SCHED_HPWORKPRIORITY=192
CONFIG_SPINLOCK=y
CONFIG_STACK_COLORATION=y
CONFIG_START_MONTH=3
CONFIG_START_YEAR=2022
CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_TESTING_GETPRIME=y
CONFIG_TESTING_OSTEST=y
CONFIG_UART1_SERIAL_CONSOLE=y
CONFIG_USEC_PER_TICK=1000