Add Ethernet pin/clock configuration logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4148 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
c9ca9fc763
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@ -126,50 +126,52 @@
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#define GPIO_DCMI_VSYNC_1 (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
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#define GPIO_DCMI_VSYNC_2 (GPIO_ALT|GPIO_AF13|GPIO_PORTI|GPIO_PIN5)
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/* Clocks outputs */
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#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
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#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
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/* Ethernet MAC */
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#define GPIO_MCO1 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN8)
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#define GPIO_MCO2 (GPIO_ALT|GPIO_AF0|GPIO_PORTC|GPIO_PIN9)
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#define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN1)
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#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN2)
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#define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN3)
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#define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTH|GPIO_PIN3)
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#define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTH|GPIO_PIN2)
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#define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTH|GPIO_PIN6)
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#define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN1)
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#define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTH|GPIO_PIN7)
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#define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTI|GPIO_PIN10)
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#define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN13)
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#define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN14)
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#define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTE|GPIO_PIN2)
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#define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN11)
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#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN5)
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#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN8)
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#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN13)
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#define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN14)
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#define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_PORTG|GPIO_PIN11)
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#define GPIO_ETH_MDC (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN1)
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#define GPIO_ETH_MDIO (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
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#define GPIO_ETH_MII_COL_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
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#define GPIO_ETH_MII_COL_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN3)
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#define GPIO_ETH_MII_CRS_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
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#define GPIO_ETH_MII_CRS_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN2)
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#define GPIO_ETH_MII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_ETH_MII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_ETH_MII_RXD2_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0)
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#define GPIO_ETH_MII_RXD2_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN6)
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#define GPIO_ETH_MII_RXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1)
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#define GPIO_ETH_MII_RXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTH|GPIO_PIN7)
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#define GPIO_ETH_MII_RX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_ETH_MII_RX_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
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#define GPIO_ETH_MII_RX_ER_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
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#define GPIO_ETH_MII_RX_ER_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN10)
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#define GPIO_ETH_MII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
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#define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
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#define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2)
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#define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
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#define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2)
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#define GPIO_ETH_MII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_ETH_MII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
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#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
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#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
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#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
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#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
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#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
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#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
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#define GPIO_ETH_RMII_TXD0_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN12)
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#define GPIO_ETH_RMII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13)
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#define GPIO_ETH_RMII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13)
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#define GPIO_ETH_RMII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
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#define GPIO_ETH_RMII_TX_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN3)
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#define GPIO_ETH_RMII_TX_EN_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
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#define GPIO_ETH_RMII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
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/* Flexible Static Memory Controller (FSMC) */
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@ -179,11 +179,11 @@
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#define RCC_CFGR_RTCPRE_MASK (31 << RCC_CFGR_RTCPRE)
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# define RCC_CFGR_RTCPRE(n) ((n) << RCC_CFGR_RTCPRE) /* HSE/n, n=1..31 */
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#define RCC_CFGR_MCO1_SHIFT (21) /* Bits 21-22: Microcontroller Clock Output */
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#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO_SHIFT)
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# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO_SHIFT) /* 00: HSI clock selected */
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# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO_SHIFT) /* 01: LSE oscillator selected */
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# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO_SHIFT) /* 10: HSE oscillator clock selected */
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# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO_SHIFT) /* 11: PLL clock selected */
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#define RCC_CFGR_MCO1_MASK (3 << RCC_CFGR_MCO1_SHIFT)
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# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 00: HSI clock selected */
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# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 01: LSE oscillator selected */
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# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 10: HSE oscillator clock selected */
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# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 11: PLL clock selected */
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#define TCC_CFGR_I2SSRC (1 << 23) /* Bit 23: I2S clock selection */
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#define RCC_CFGR_MCO1PRE_SHIFT (24) /* Bits 24-26: MCO1 prescaler */
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#define RCC_CFGR_MCO1PRE_MASK (7 << RCC_CFGR_MCO1PRE_SHIFT)
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@ -2,7 +2,9 @@
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* arch/arm/src/stm32/stm32.h
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*
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* Copyright (C) 2011 Uros Platise. All rights reserved.
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* Author: Uros Platise <uros.platise@isotel.eu>
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Authors: Uros Platise <uros.platise@isotel.eu>
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* Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -55,10 +55,15 @@
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#include <net/uip/uip-arp.h>
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#include <net/uip/uip-arch.h>
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#include "up_internal.h"
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#include "chip.h"
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#include "stm32_gpio.h"
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#include "stm32_rcc.h"
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#include "stm32_syscfg.h"
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#include "stm32_eth.h"
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#include "up_internal.h"
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#include <arch/board/board.h>
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/* STM32_NETHERNET determines the number of physical interfaces
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* that will be supported.
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@ -69,8 +74,33 @@
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per second */
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#ifndef CONFIG_STM32_SYSCFG
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# error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration"
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#endif
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#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII)
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# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined"
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#endif
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#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII)
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# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined"
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#endif
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#ifdef CONFIG_STM32_MII
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# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2)
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# warning "Neither CONFIG_STM32_MII_MCO1 nor CONFIG_STM32_MII_MCO2 defined"
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# endif
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# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2)
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# warning "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined"
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# endif
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#endif
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/* Timing *******************************************************************/
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/* TX poll delay = 1 seconds. CLK_TCK is the number of clock ticks per
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* second
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*/
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#define STM32_WDDELAY (1*CLK_TCK)
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#define STM32_POLLHSEC (1*2)
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@ -79,7 +109,10 @@
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#define STM32_TXTIMEOUT (60*CLK_TCK)
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/* This is a helper pointer for accessing the contents of the Ethernet header */
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/* Helpers ******************************************************************/
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/* This is a helper pointer for accessing the contents of the Ethernet
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* header
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*/
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#define BUF ((struct uip_eth_hdr *)priv->dev.d_buf)
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@ -138,6 +171,10 @@ static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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#endif
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/* Initialization */
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static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv);
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -622,6 +659,127 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
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}
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#endif
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/****************************************************************************
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* Function: stm32_ethgpioconfig
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*
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* Description:
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* Configure GPIOs for the Ethernet interface.
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*
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* Parameters:
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* priv - A reference to the private driver state structure
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*
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* Returned Value:
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* OK on success; Negated errno on failure.
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*
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* Assumptions:
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*
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****************************************************************************/
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#if STM32_NETHERNET == 1
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static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
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{
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/* Configure GPIO pins to support Ethernet */
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#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII)
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/* MDC and MDIO are common to both modes */
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stm32_configgpio(GPIO_ETH_MDC);
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stm32_configgpio(GPIO_ETH_MDIO);
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/* Set up the MII interface */
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#if defined(CONFIG_STM32_MII)
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/* Select the MII interface */
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stm32_selectmii();
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/* Provide clocking via MCO1 or MCO2:
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*
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* "MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
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* clock (through a configurable prescaler) on PA8 pin."
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*
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* "MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or
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* PLLI2S clock (through a configurable prescaler) on PC9 pin."
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*/
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# warning "REVISIT: This is very board-specific"
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# if defined(CONFIG_STM32_MII_MCO1)
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/* Configure MC01 to drive the PHY */
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stm32_configgpio(GPIO_MCO1);
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/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */
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stm32_mco1config(RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1PRE_NONE);
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# elif defined(CONFIG_STM32_MII_MCO2)
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/* Configure MC02 to drive the PHY */
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stm32_configgpio(GPIO_MCO2);
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/* Output HSE clock (25MHz) on MCO pin (PA8) to clock the PHY */
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stm32_mco2config(RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2PRE_NONE);
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# endif
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/* MII interface pins (17):
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*
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* MII_TX_CLK, MII_TXD[3:0], MII_TX_EN, MII_RX_CLK, MII_RXD[3:0], MII_RX_ER,
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* MII_RX_DV, MII_CRS, MII_COL, MDC, MDIO
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*/
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stm32_configgpio(GPIO_ETH_MII_COL);
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stm32_configgpio(GPIO_ETH_MII_CRS);
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stm32_configgpio(GPIO_ETH_MII_RXD0);
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stm32_configgpio(GPIO_ETH_MII_RXD1);
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stm32_configgpio(GPIO_ETH_MII_RXD2);
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stm32_configgpio(GPIO_ETH_MII_RXD3);
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stm32_configgpio(GPIO_ETH_MII_RX_CLK);
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stm32_configgpio(GPIO_ETH_MII_RX_DV);
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stm32_configgpio(GPIO_ETH_MII_RX_ER);
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stm32_configgpio(GPIO_ETH_MII_TXD0);
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stm32_configgpio(GPIO_ETH_MII_TXD1);
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stm32_configgpio(GPIO_ETH_MII_TXD2);
|
||||
stm32_configgpio(GPIO_ETH_MII_TXD3);
|
||||
stm32_configgpio(GPIO_ETH_MII_TX_CLK);
|
||||
stm32_configgpio(GPIO_ETH_MII_TX_EN);
|
||||
|
||||
/* Set up the RMII interface. */
|
||||
|
||||
#elif defined(CONFIG_STM32_RMII)
|
||||
|
||||
/* Select the RMII interface */
|
||||
|
||||
stm32_selectrmii();
|
||||
|
||||
/* RMII interface pins (7):
|
||||
*
|
||||
* RMII_TXD[1:0], RMII_TX_EN, RMII_RXD[1:0], RMII_CRS_DV, MDC, MDIO,
|
||||
* RMII_REF_CLK
|
||||
*/
|
||||
|
||||
stm32_configgpio(GPIO_ETH_RMII_CRS_DV);
|
||||
stm32_configgpio(GPIO_ETH_RMII_REF_CLK);
|
||||
stm32_configgpio(GPIO_ETH_RMII_RXD0);
|
||||
stm32_configgpio(GPIO_ETH_RMII_RXD1);
|
||||
stm32_configgpio(GPIO_ETH_RMII_TXD0);
|
||||
stm32_configgpio(GPIO_ETH_RMII_TXD1);
|
||||
stm32_configgpio(GPIO_ETH_RMII_TX_CLK);
|
||||
stm32_configgpio(GPIO_ETH_RMII_TX_EN);
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Enable pulse-per-second (PPS) output signal */
|
||||
|
||||
stm32_configgpio(GPIO_ETH_PPS_OUT);
|
||||
}
|
||||
#else
|
||||
# warning "This would need to be re-designed to support multiple interfaces"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -659,17 +817,6 @@ int stm32_ethinitialize(int intf)
|
||||
DEBUGASSERT(inf < STM32_NETHERNET);
|
||||
priv = &g_stm32ethmac[intf];
|
||||
|
||||
/* Check if a Ethernet chip is recognized at its I/O base */
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
if (irq_attach(STM32_IRQ_ETH, stm32_interrupt))
|
||||
{
|
||||
/* We could not attach the ISR to the interrupt */
|
||||
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* Initialize the driver structure */
|
||||
|
||||
memset(priv, 0, sizeof(struct stm32_ethmac_s));
|
||||
@ -687,6 +834,21 @@ int stm32_ethinitialize(int intf)
|
||||
priv->txpoll = wd_create(); /* Create periodic poll timer */
|
||||
priv->txtimeout = wd_create(); /* Create TX timeout timer */
|
||||
|
||||
/* Configure GPIO pins to support Ethernet */
|
||||
|
||||
stm32_ethgpioconfig(priv);
|
||||
|
||||
/* Check if a Ethernet chip is recognized at its I/O base */
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
if (irq_attach(STM32_IRQ_ETH, stm32_interrupt))
|
||||
{
|
||||
/* We could not attach the ISR to the interrupt */
|
||||
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/* Put the interface in the down state. This usually amounts to resetting
|
||||
* the device and/or calling stm32_ifdown().
|
||||
*/
|
||||
|
||||
@ -42,6 +42,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F10XX)
|
||||
@ -75,21 +76,109 @@ extern "C" {
|
||||
* and we will need to set the NVIC vector location to this alternative location.
|
||||
*/
|
||||
|
||||
extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
|
||||
extern uint32_t stm32_vectors[]; /* See stm32_vectors.S */
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_mco1config
|
||||
*
|
||||
* Description:
|
||||
* Selects the clock source to output on MCO1 pin (PA8). PA8 should be configured in
|
||||
* alternate function mode.
|
||||
*
|
||||
* Input Parameters:
|
||||
* source - One of the definitions for the RCC_CFGR_MCO1 definitions from
|
||||
* chip/stm32f40xxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE,
|
||||
* RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL}
|
||||
* div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from
|
||||
* chip/stm32f40xxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2,
|
||||
* RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5}
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F40XX)
|
||||
static inline void stm32_mco1config(uint32_t source, uint32_t div)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~(RCC_CFGR_MCO1_MASK|RCC_CFGR_MCO1PRE_MASK);
|
||||
regval |= (source | div);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_mco2config
|
||||
*
|
||||
* Description:
|
||||
* Selects the clock source to output on MCO2 pin (PC9). PC9 should be configured in
|
||||
* alternate function mode.
|
||||
*
|
||||
* Input Parameters:
|
||||
* source - One of the definitions for the RCC_CFGR_MCO2 definitions from
|
||||
* chip/stm32f40xxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S,
|
||||
* RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL}
|
||||
* div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from
|
||||
* chip/stm32f40xxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2,
|
||||
* RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5}
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_STM32F40XX)
|
||||
static inline void stm32_mco2config(uint32_t source, uint32_t div)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
regval &= ~(RCC_CFGR_MCO2_MASK|RCC_CFGR_MCO2PRE_MASK);
|
||||
regval |= (source | div);
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
}
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
* NOTE: This logic needs to be extended so that we can selected low-power
|
||||
* clocking modes as well!
|
||||
*/
|
||||
/************************************************************************************
|
||||
* Name: stm32_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to change to new clock based on settings in board.h
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_clockconfig(void);
|
||||
|
||||
/* Enable LSE Clock */
|
||||
/************************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable LSE Clock
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN void stm32_rcc_enablelse(void);
|
||||
|
||||
|
||||
104
arch/arm/src/stm32/stm32_syscfg.h
Normal file
104
arch/arm/src/stm32/stm32_syscfg.h
Normal file
@ -0,0 +1,104 @@
|
||||
/****************************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_syscfg.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H
|
||||
|
||||
/****************************************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef CONFIG_STM32_STM32F40XX
|
||||
# include "chip/stm32_syscfg.h"
|
||||
|
||||
/****************************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
/****************************************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_selectmii
|
||||
*
|
||||
* Description:
|
||||
* Selects the MII inteface.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static inline void stm32_selectmii(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32_SYSCFG_PMC);
|
||||
regval &= ~SYSCFG_PMC_MII_RMII_SEL;
|
||||
putreg32(regval, STM32_SYSCFG_PMC);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_selectrmii
|
||||
*
|
||||
* Description:
|
||||
* Selects the RMII inteface.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
static inline void stm32_selectrmii(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
regval = getreg32(STM32_SYSCFG_PMC);
|
||||
regval |= SYSCFG_PMC_MII_RMII_SEL;
|
||||
putreg32(regval, STM32_SYSCFG_PMC);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_STM32F40XX */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H */
|
||||
@ -374,6 +374,11 @@ STM3240G-EVAL-specific Configuration Options
|
||||
CONFIG_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
|
||||
4-bit transfer mode.
|
||||
|
||||
CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
|
||||
STM3240G-EVAL LCD Hardware Configuration
|
||||
|
||||
Configurations
|
||||
|
||||
@ -207,6 +207,42 @@
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_2
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_2
|
||||
|
||||
/* Ethernet:
|
||||
*
|
||||
* - PA2 is ETH_MDIO
|
||||
* - PC1 is ETH_MDC
|
||||
* - PB5 is ETH_PPS_OUT
|
||||
* - PH2 is ETH_MII_CRS
|
||||
* - PH3 is ETH_MII_COL
|
||||
* - PI10 is ETH_MII_RX_ER
|
||||
* - PH6 is ETH_MII_RXD2
|
||||
* - PH7 is ETH_MII_RXD3
|
||||
* - PC3 is ETH_MII_TX_CLK
|
||||
* - PC2 is ETH_MII_TXD2
|
||||
* - PB8 is ETH_MII_TXD3
|
||||
* - PA1 is ETH_MII_RX_CLK/ETH_RMII_REF_CLK
|
||||
* - PA7 is ETH_MII_RX_DV/ETH_RMII_CRS_DV
|
||||
* - PC4 is ETH_MII_RXD0/ETH_RMII_RXD0
|
||||
* - PC5 is ETH_MII_RXD1/ETH_RMII_RXD1
|
||||
* - PG11 is ETH_MII_TX_EN/ETH_RMII_TX_EN
|
||||
* - PG13 is ETH_MII_TXD0/ETH_RMII_TXD0
|
||||
* - PG14 is ETH_MII_TXD1/ETH_RMII_TXD1
|
||||
*/
|
||||
|
||||
#define GPIO_ETH_PPS_OUT GPIO_ETH_PPS_OUT_1
|
||||
#define GPIO_ETH_MII_CRS GPIO_ETH_MII_CRS_2
|
||||
#define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_2
|
||||
#define GPIO_ETH_MII_RX_ER GPIO_ETH_MII_RX_ER_2
|
||||
#define GPIO_ETH_MII_RXD2 GPIO_ETH_MII_RXD2_2
|
||||
#define GPIO_ETH_MII_RXD3 GPIO_ETH_MII_RXD3_2
|
||||
#define GPIO_ETH_MII_TXD3 GPIO_ETH_MII_TXD3_1
|
||||
#define GPIO_ETH_MII_TX_EN GPIO_ETH_MII_TX_EN_2
|
||||
#define GPIO_ETH_MII_TXD0 GPIO_ETH_MII_TXD0_2
|
||||
#define GPIO_ETH_MII_TXD1 GPIO_ETH_MII_TXD1_2
|
||||
#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2
|
||||
#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
|
||||
#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
@ -182,7 +182,7 @@ CONFIG_STM32_TIM11=n
|
||||
#CONFIG_STM32_FORCEPOWER=y
|
||||
|
||||
#
|
||||
# STM3240xxx specific serial device driver settings
|
||||
# STM32F40xxx specific serial device driver settings
|
||||
#
|
||||
# CONFIG_USARTn_SERIAL_CONSOLE - selects the USARTn for the
|
||||
# console and ttys0 (default is the USART1).
|
||||
@ -238,7 +238,7 @@ CONFIG_USART4_2STOP=0
|
||||
CONFIG_USART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
# CONFIG_SSIn_DISABLE - select to disable all support for
|
||||
# the SSI
|
||||
@ -255,6 +255,19 @@ CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
# CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
#
|
||||
CONFIG_STM32_MII=y
|
||||
CONFIG_STM32_MII_MCO1=y
|
||||
CONFIG_STM32_MII_MCO2=n
|
||||
CONFIG_STM32_RMII=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
||||
@ -238,7 +238,7 @@ CONFIG_USART4_2STOP=0
|
||||
CONFIG_USART5_2STOP=0
|
||||
|
||||
#
|
||||
# STM32F103Z specific SSI device driver settings
|
||||
# STM32F40xxx specific SSI device driver settings
|
||||
#
|
||||
# CONFIG_SSIn_DISABLE - select to disable all support for
|
||||
# the SSI
|
||||
@ -255,6 +255,19 @@ CONFIG_SSI1_DISABLE=y
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
#CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
#
|
||||
# STM32F40xxx Ethernet device driver settings
|
||||
#
|
||||
# CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
# CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
# CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
# CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
#
|
||||
CONFIG_STM32_MII=y
|
||||
CONFIG_STM32_MII_MCO1=y
|
||||
CONFIG_STM32_MII_MCO2=n
|
||||
CONFIG_STM32_RMII=n
|
||||
|
||||
#
|
||||
# General build options
|
||||
#
|
||||
|
||||
Loading…
Reference in New Issue
Block a user