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XMC4xxx: Move clock utility functions from xmc4_clocconfig.c to new xmc4_clockutils.c

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This commit is contained in:
Gregory Nutt 2017-03-16 14:26:22 -06:00
parent e30e47683b
commit 6b167122c0
4 changed files with 154 additions and 88 deletions
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6
arch/arm/src/xmc4/Make.defs
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@ -110,9 +110,9 @@ endif
CHIP_ASRCS =
CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clrpend.c
CHIP_CSRCS += xmc4_idle.c xmc4_irq.c xmc4_lowputc.c xmc4_gpio.c
CHIP_CSRCS += xmc4_serialinit.c xmc4_serial.c xmc4_start.c xmc4_uid.c
CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c
CHIP_CSRCS += xmc4_clrpend.c xmc4_idle.c xmc4_irq.c xmc4_lowputc.c
CHIP_CSRCS += xmc4_gpio.c xmc4_serial.c xmc4_start.c
# Configuration-dependent Kinetis files

2
arch/arm/src/xmc4/chip/xmc4_memorymap.h
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@ -147,7 +147,7 @@
#define XMC4_USIC2_BASE 0x48024000
#define XMC4_USIC2_CH0_BASE 0x48024000
#define XMC4_USIC2_CH1_BASE 0x48024200
#define XMC4_USIC2_CH1_BASE 0x48024400
#define XMC4_USIC2_RAM_BASE 0x48024400
#define XMC4_PORT0_BASE 0x48028000
#define XMC4_PORT1_BASE 0x48028100
#define XMC4_PORT2_BASE 0x48028200

84
arch/arm/src/xmc4/xmc4_clockconfig.c
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@ -529,87 +529,3 @@ void xmc4_clock_configure(void)
putreg32(CLKSET_VALUE, XMC4_SCU_CLKSET);
}
/****************************************************************************
* Name: xmc4_get_coreclock
*
* Description:
* Return the current core clock frequency (fCPU).
*
****************************************************************************/
uint32_t xmc4_get_coreclock(void)
{
uint32_t pdiv;
uint32_t ndiv;
uint32_t kdiv;
uint32_t sysdiv;
uint32_t regval;
uint32_t temp;
if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0)
{
/* fPLL is clock source for fSYS */
if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0)
{
/* PLL input clock is the backup clock (fOFI) */
temp = OFI_FREQUENCY;
}
else
{
/* PLL input clock is the high performance oscillator (fOSCHP);
* Only board specific logic knows this value.
*/
temp = BOARD_XTAL_FREQUENCY;
}
/* Check if PLL is locked */
regval = getreg32(XMC4_SCU_PLLSTAT);
if ((regval & SCU_PLLSTAT_VCOLOCK) != 0)
{
/* PLL normal mode */
regval = getreg32(XMC4_SCU_PLLCON1);
pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1;
ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1;
kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
else
{
/* PLL prescalar mode */
regval = getreg32(XMC4_SCU_PLLCON1);
kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1;
temp = (temp / kdiv);
}
}
else
{
/* fOFI is clock source for fSYS */
temp = OFI_FREQUENCY;
}
/* Divide by SYSDIV to get fSYS */
regval = getreg32(XMC4_SCU_SYSCLKCR);
sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1;
temp = temp / sysdiv;
/* Check if the fSYS clock is divided by two to produce fCPU clock. */
regval = getreg32(XMC4_SCU_CPUCLKCR);
if ((regval & SCU_CPUCLKCR_CPUDIV) != 0)
{
temp = temp >> 1;
}
return temp;
}

150
arch/arm/src/xmc4/xmc4_clockutils.c Normal file
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@ -0,0 +1,150 @@
/****************************************************************************
* arch/arm/src/xmc4/xmc4_clockutils.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* May include some logic from sample code provided by Infineon:
*
* Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved.
*
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed within
* development tools that are supporting such microcontrollers.
*
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "up_arch.h"
#include "chip/xmc4_scu.h"
#include "xmc4_clockconfig.h"
#include <arch/board/board.h>
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: xmc4_get_coreclock
*
* Description:
* Return the current core clock frequency (fCPU).
*
****************************************************************************/
uint32_t xmc4_get_coreclock(void)
{
uint32_t pdiv;
uint32_t ndiv;
uint32_t kdiv;
uint32_t sysdiv;
uint32_t regval;
uint32_t temp;
if ((getreg32(XMC4_SCU_SYSCLKCR) & SCU_SYSCLKCR_SYSSEL) != 0)
{
/* fPLL is clock source for fSYS */
if ((getreg32(XMC4_SCU_PLLCON2) & SCU_PLLCON2_PINSEL) != 0)
{
/* PLL input clock is the backup clock (fOFI) */
temp = OFI_FREQUENCY;
}
else
{
/* PLL input clock is the high performance oscillator (fOSCHP);
* Only board specific logic knows this value.
*/
temp = BOARD_XTAL_FREQUENCY;
}
/* Check if PLL is locked */
regval = getreg32(XMC4_SCU_PLLSTAT);
if ((regval & SCU_PLLSTAT_VCOLOCK) != 0)
{
/* PLL normal mode */
regval = getreg32(XMC4_SCU_PLLCON1);
pdiv = ((regval & SCU_PLLCON1_PDIV_MASK) >> SCU_PLLCON1_PDIV_SHIFT) + 1;
ndiv = ((regval & SCU_PLLCON1_NDIV_MASK) >> SCU_PLLCON1_NDIV_SHIFT) + 1;
kdiv = ((regval & SCU_PLLCON1_K2DIV_MASK) >> SCU_PLLCON1_K2DIV_SHIFT) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
else
{
/* PLL prescalar mode */
regval = getreg32(XMC4_SCU_PLLCON1);
kdiv = ((regval & SCU_PLLCON1_K1DIV_MASK) >> SCU_PLLCON1_K1DIV_SHIFT) + 1;
temp = (temp / kdiv);
}
}
else
{
/* fOFI is clock source for fSYS */
temp = OFI_FREQUENCY;
}
/* Divide by SYSDIV to get fSYS */
regval = getreg32(XMC4_SCU_SYSCLKCR);
sysdiv = ((regval & SCU_SYSCLKCR_SYSDIV_MASK) >> SCU_SYSCLKCR_SYSDIV_SHIFT) + 1;
temp = temp / sysdiv;
/* Check if the fSYS clock is divided by two to produce fCPU clock. */
regval = getreg32(XMC4_SCU_CPUCLKCR);
if ((regval & SCU_CPUCLKCR_CPUDIV) != 0)
{
temp = temp >> 1;
}
return temp;
}