Add SDRAM initialization
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2454 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -46,6 +46,7 @@
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#include "arm.h"
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#include "up_internal.h"
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#include "up_arch.h"
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#include "lpc313x_internal.h"
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/************************************************************************************
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* Private Types
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@ -5,8 +5,8 @@
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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* - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - lpc313x.cdl.drivers.zip example driver code
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* - NXP UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
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* - NXP lpc313x.cdl.drivers.zip example driver code
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -241,6 +241,28 @@
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#define MPMC_DYNCONFIG0_AM (1 << 14) /* Bit 14: Address mapping */
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#define MPMC_DYNCONFIG0_AM_SHIFT (7) /* Bits 7-12: Address mapping */
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#define MPMC_DYNCONFIG0_AM_MASK (0x3c << MPMC_DYNCONFIG0_AM_SHIFT)
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/* 16-bit external bus high-performance address mapping */
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# define MPMC_DYNCONFIG_HP16_2MX8 (0x00 << MPMC_DYNCONFIG0_AM_SHIFT) /* 16Mb (2Mx8), 2 banks, row length=11, column length=9 */
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# define MPMC_DYNCONFIG_HP16_1MX16 (0x01 << MPMC_DYNCONFIG0_AM_SHIFT) /* 16Mb (1Mx16), 2 banks, row length=11, column length=8 */
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# define MPMC_DYNCONFIG_HP16_8MX8 (0x04 << MPMC_DYNCONFIG0_AM_SHIFT) /* 64Mb (8Mx8), 4 banks, row length=12, column length=9 */
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# define MPMC_DYNCONFIG_HP16_4MX16 (0x05 << MPMC_DYNCONFIG0_AM_SHIFT) /* 64Mb (4Mx16), 4 banks, row length=12, column length=8 */
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# define MPMC_DYNCONFIG_HP16_16MX8 (0x08 << MPMC_DYNCONFIG0_AM_SHIFT) /* 128Mb (16Mx8), 4 banks, row length=12, column length=10 */
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# define MPMC_DYNCONFIG_HP16_8MX16 (0x09 << MPMC_DYNCONFIG0_AM_SHIFT) /* 128Mb (8Mx16), 4 banks, row length=12, column length=9 */
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# define MPMC_DYNCONFIG_HP16_32MX8 (0x0c << MPMC_DYNCONFIG0_AM_SHIFT) /* 256Mb (32Mx8), 4 banks, row length=13, column length=10 */
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# define MPMC_DYNCONFIG_HP16_16MX16 (0x0d << MPMC_DYNCONFIG0_AM_SHIFT) /* 256Mb (16Mx16), 4 banks, row length=13, column length=9 */
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# define MPMC_DYNCONFIG_HP16_64MX8 (0x10 << MPMC_DYNCONFIG0_AM_SHIFT) /* 512Mb (64Mx8), 4 banks, row length=13, column length=11 */
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# define MPMC_DYNCONFIG_HP16_32MX16 (0x11 << MPMC_DYNCONFIG0_AM_SHIFT) /* 512Mb (32Mx16), 4 banks, row length=13, column length=10 */
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/* 16-bit external bus low power SDRAM address mapping */
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# define MPMC_DYNCONFIG_LP16_2MX8 (0x20 << MPMC_DYNCONFIG0_AM_SHIFT) /* 6Mb (2Mx8), 2 banks, row length=11, column length=9 */
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# define MPMC_DYNCONFIG_LP16_1MX16 (0x21 << MPMC_DYNCONFIG0_AM_SHIFT) /* 16Mb (1Mx16), 2 banks, row length=11, column length=8 */
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# define MPMC_DYNCONFIG_LP16_8MX8 (0x24 << MPMC_DYNCONFIG0_AM_SHIFT) /* 64Mb (8Mx8), 4 banks, row length=12, column length=9 */
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# define MPMC_DYNCONFIG_LP16_4MX16 (0x25 << MPMC_DYNCONFIG0_AM_SHIFT) /* 64Mb (4Mx16), 4 banks, row length=12, column length=8 */
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# define MPMC_DYNCONFIG_LP16_16MX8 (0x28 << MPMC_DYNCONFIG0_AM_SHIFT) /* 128Mb (16Mx8), 4 banks, row length=12, column length=10 */
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# define MPMC_DYNCONFIG_LP16_8MX16 (0x29 << MPMC_DYNCONFIG0_AM_SHIFT) /* 128Mb (8Mx16), 4 banks, row length=12, column length=9 */
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# define MPMC_DYNCONFIG_LP16_32MX8 (0x2c << MPMC_DYNCONFIG0_AM_SHIFT) /* 256Mb (32Mx8), 4 banks, row length=13, column length=10 */
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# define MPMC_DYNCONFIG_LP16_16MX16 (0x2d << MPMC_DYNCONFIG0_AM_SHIFT) /* 256Mb (16Mx16), 4 banks, row length=13, column length=9 */
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# define MPMC_DYNCONFIG_LP16_64MX8 (0x30 << MPMC_DYNCONFIG0_AM_SHIFT) /* 512Mb (64Mx8), 4 banks, row length=13, column length=11 */
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# define MPMC_DYNCONFIG_LP16_32MX16 (0x31 << MPMC_DYNCONFIG0_AM_SHIFT) /* 512Mb (32Mx16), 4 banks, row length=13, column length=10 */
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#define MPMC_DYNCONFIG0_MD_SHIFT (3) /* Bits 3-4: Memory device */
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#define MPMC_DYNCONFIG0_MD_MASK (3 << MPMC_DYNCONFIG0_MD_SHIFT)
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# define MPMC_DYNCONFIG0_MDSDRAM (0 << MPMC_DYNCONFIG0_MD_SHIFT) /* SDRAM */
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@ -40,7 +40,7 @@ CFLAGS += -I$(TOPDIR)/sched
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ASRCS =
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AOBJS = $(ASRCS:.S=$(OBJEXT))
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CSRCS = up_boot.c up_buttons.c up_cgu.c up_leds.c up_spi.c
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CSRCS = up_boot.c up_buttons.c up_cgu.c up_leds.c up_sdram.c up_spi.c
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ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
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CSRCS += up_nsh.c
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endif
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@ -74,6 +74,16 @@
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* Public Functions
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************************************************************************************/
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/****************************************************************************
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* Name: lpc313x_sdraminitialize
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*
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* Description:
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* Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board
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*
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****************************************************************************/
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extern void lpc313x_sdraminitialize(void);
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/************************************************************************************
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* Name: lpc313x_spiinitialize
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*
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@ -73,6 +73,10 @@
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void lpc313x_boardinitialize(void)
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{
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/* Configure Micron MT48LC32M16A2 SDRAM on the EA3131 board */
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lpc313x_sdraminitialize();
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/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
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* lpc313x_spiinitialize() has been brought into the link.
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*/
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267
configs/ea3131/src/up_sdram.c
Executable file
267
configs/ea3131/src/up_sdram.c
Executable file
@ -0,0 +1,267 @@
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/****************************************************************************
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* configs/ea3131/src/up_sdram.c
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* arch/arm/src/board/up_sdram.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* References:
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* - NXP lpc313x.cdl.drivers.zip example driver code
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include "chip.h"
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#include "up_arch.h"
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#include "lpc313x_mpmc.h"
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#include "lpc313x_cgudrvr.h"
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#include "ea3131_internal.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Enables debug output from this file (needs CONFIG_DEBUG with
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* CONFIG_DEBUG_VERBOSE too)
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*/
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#undef SDRAM_DEBUG /* Define to enable debug */
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#ifdef SDRAM_DEBUG
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# define sdramdbg lldbg
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# define sdramvdbg llvdbg
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#else
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# define sdramdbg(x...)
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# define sdramvdbg(x...)
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#endif
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/*Delay constants in nanosecondss for MT48LC32M16LF SDRAM on board */
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#define EA3131_SDRAM_TRP (20)
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#define EA3131_SDRAM_TRFC (66)
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#define EA3131_SDRAM_TRAS (44)
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#define EA3131_SDRAM_TREX (75)
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#define EA3131_SDRAM_TARP 4
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#define EA3131_SDRAM_TWR (75)
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#define EA3131_SDRAM_TRC (66)
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#define EA3131_SDRAM_TRRD (15)
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#define EA3131_SDRAM_TMRD (20)
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#define EA3131_SDRAM_TXSR (75)
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#define EA3131_SDRAM_TDAL (50)
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#define EA3131_SDRAM_REFRESH (100)
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#define EA3131_SDRAM_OPERREFRESH (7812)
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/* Macro used to convert the above values (in nanoseconds) into units of
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* the HCLK.
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*/
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#define NS2HCLKS(ns,hclk2,mask) \
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((uint32_t)(((uint64_t)ns *(uint64_t)hclk2) / 1000000000ull) & mask)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc313x_sdraminitialize
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*
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* Description:
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* Configure SDRAM on the EA3131 board
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*
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* Micron Initialization Sequence from their data sheet for the Micron
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* MT48LC32M16A2 32M x 16 SDRAM chip:
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*
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* "SDRAMs must be powered up and initialized in a predefined manner.
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* Operational procedures other than those specified may result in
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* undefined operation. Once power is applied to VDD and VDDQ
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* (simultaneously) and the clock is stable (stable clock is defined as
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* a signal cycling within timing constraints specified for the clock
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* pin), the SDRAM requires a 100µs delay prior to issuing any command
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* other than a COMMAND INHIBIT or NOP.
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*
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* "Starting at some point during this 100µs period and continuing at least
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* through the end of this period, COMMAND INHIBIT or NOP commands should
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* be applied. Once the 100µs delay has been satisfied with at least one
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* COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command
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* should be applied. All banks must then be precharged, thereby placing
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* the device in the all banks idle state.
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*
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* "Once in the idle state, two AUTO REFRESH cycles must be performed. After
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* the AUTO REFRESH cycles are complete, the SDRAM is ready for mode
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* register programming.
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*
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* "Because the mode register will power up in an unknown state, it should
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* be loaded prior to applying any operational command."
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*
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* The JEDEC recommendation for initializing SDRAM is:
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*
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* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
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* Wait 200uS
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* PRECHARGE all
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* 8 AUTO REFRESH COMMANDS
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* LOAD MODE REGISTER
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* SDRAM is ready for operation
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*
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* The Micron SDRAM parts will work fine with the JEDEC sequence, but also
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* allow for a quicker init sequence of:
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*
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* APPLY POWER (Vdd/Vddq equally, and CLK is stable)
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* Wait at least 100uS (during which time start applying and
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* continue applying NOP or COMMAND INHIBIT)
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* PRECHARGE all
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* 2 AUTO REFRESH COMMANDS (min requirement, more than 2 is also ok)
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* LOAD MODE REGISTER
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* SDRAM is ready for operation
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*
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****************************************************************************/
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void lpc313x_sdraminitialize(void)
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{
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uint32_t tmp;
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uint32_t regval;
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/* These run-time calculations can be reduced dramatically if hclk is
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* replaced with an apriori value.
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*/
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#ifdef CONFIG_LPC313X_SDRAMHCLK
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# define HCLK CONFIG_LPC313X_SDRAMHCLK
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#else
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uint32_t hclk = lpc313x_clkfreq(CLKID_MPMCCFGCLK2, DOMAINID_SYS);
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# define HCLK hclk
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#endif
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/* Check RTL for divide by 2 possible. If so change then enable the following logic */
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#if 0
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uint32_t hclk2 = hclk;
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if (((getreg32(LPC313X_MPMC_CONFIG) & MPMC_CONFIG_CLK)) != 0)
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{
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hclk2 >>= 1;
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}
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# define HCLK2 hclk2
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#else
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# define HCLK2 hclk
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#endif
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up_udelay(100);
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/* Set command delay startergy */
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putreg32(MPMC_DYNREADCONFIG_CMDDEL, LPC313X_MPMC_DYNREADCONFIG);
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/* Configure device config register nSDCE0 for proper width SDRAM */
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putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16), LPC313X_MPMC_DYNCONFIG0);
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putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK), LPC313X_MPMC_DYNRASCAS0);
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/* Min 20ns program 1 so that at least 2 HCLKs are used */
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putreg32(NS2HCLKS(EA3131_SDRAM_TRP, HCLK2, MPMC_DYNTRP_MASK), LPC313X_MPMC_DYNTRP);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRAS, HCLK2, MPMC_DYNTRAS_MASK), LPC313X_MPMC_DYNTRAS);
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putreg32(NS2HCLKS(EA3131_SDRAM_TREX, HCLK2, MPMC_DYNTSREX_MASK), LPC313X_MPMC_DYNTSREX);
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putreg32(EA3131_SDRAM_TARP, LPC313X_MPMC_DYNTAPR);
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putreg32(NS2HCLKS(EA3131_SDRAM_TDAL, HCLK2, MPMC_DYNTDAL_MASK), LPC313X_MPMC_DYNTDAL);
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putreg32(NS2HCLKS(EA3131_SDRAM_TWR, HCLK2, MPMC_DYNTWR_MASK), LPC313X_MPMC_DYNTWR);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRC, HCLK2, MPMC_DYNTRC_MASK), LPC313X_MPMC_DYNTRC);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRFC, HCLK2, MPMC_DYNTRFC_MASK), LPC313X_MPMC_DYNTRFC);
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putreg32(NS2HCLKS(EA3131_SDRAM_TXSR, HCLK2, MPMC_DYNTXSR_MASK), LPC313X_MPMC_DYNTXSR);
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putreg32(NS2HCLKS(EA3131_SDRAM_TRRD, HCLK2, MPMC_DYNTRRD_MASK), LPC313X_MPMC_DYNTRRD);
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putreg32(NS2HCLKS(EA3131_SDRAM_TMRD, HCLK2, MPMC_DYNTMRD_MASK), LPC313X_MPMC_DYNTMRD);
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up_udelay(100);
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/* Issue continuous NOP commands */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INOP), LPC313X_MPMC_DYNCONTROL);
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/* Load ~200us delay value to timer1 */
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up_udelay(200);
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/* Issue a "pre-charge all" command */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IPALL), LPC313X_MPMC_DYNCONTROL);
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/* Minimum refresh pulse interval (tRFC) for MT48LC32M16A2=80nsec, 100nsec provides more than adequate interval.
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*/
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putreg32(NS2HCLKS(EA3131_SDRAM_REFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK), LPC313X_MPMC_DYNREFRESH);
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/* Load ~250us delay value to timer1 */
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up_udelay(250);
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/* Recommended refresh interval for normal operation of the Micron MT48LC16LFFG = 7.8125usec (128KHz rate). ((HCLK / 128000) - 1) = refresh counter interval rate, (subtract one for safety margin).
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*/
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putreg32(NS2HCLKS(EA3131_SDRAM_OPERREFRESH, HCLK, MPMC_DYNREFRESH_TIMER_MASK), LPC313X_MPMC_DYNREFRESH);
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/* Select mode register update mode */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_IMODE), LPC313X_MPMC_DYNCONTROL);
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/* Program the SDRAM internal mode registers on bank nSDCE0 and reconfigure the SDRAM chips. Bus speeds up to 90MHz requires use of a CAS latency = 2. To get correct value on address bus CAS cycle, requires a shift by 13 for 16bit mode
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*/
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tmp = getreg32(LPC313X_EXTSDRAM0_VSECTION | (0x23 << 13));
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putreg32((MPMC_DYNCONFIG0_MDSDRAM|MPMC_DYNCONFIG_HP16_32MX16), LPC313X_MPMC_DYNCONFIG0);
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putreg32((MPMC_DYNRASCAS0_RAS2CLK|MPMC_DYNRASCAS0_CAS2CLK), LPC313X_MPMC_DYNRASCAS0);
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/* Select normal operating mode */
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putreg32((MPMC_DYNCONTROL_CE|MPMC_DYNCONTROL_CS|MPMC_DYNCONTROL_INORMAL), LPC313X_MPMC_DYNCONTROL);
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/* Enable buffers */
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regval = getreg32(LPC313X_MPMC_DYNCONFIG0);
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regval |= MPMC_DYNCONFIG0_B;
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putreg32(regval, LPC313X_MPMC_DYNCONFIG0);
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putreg32((MPMC_DYNCONTROL_INORMAL|MPMC_DYNCONTROL_CS), LPC313X_MPMC_DYNCONTROL);
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}
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