Ensure SFR CKTRIM register correctly set, SAMA5D2/D3 only
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@ -144,6 +144,8 @@
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#define SFR_SECURE_ROM (1 << 0) /* Bit 0: Disable Access to ROM Code */
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#define SFR_SECURE_FUSE (1 << 8) /* Bit 8: Disable Access to Fuse Controller */
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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/* UTMI Clock Trimming Register */
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#define SFR_UTMICKTRIM_FREQ_SHIFT (0) /* Bits 0-1: UTMI Reference Clock Frequency */
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@ -151,17 +153,14 @@
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# define SFR_UTMICKTRIM_FREQ_12MHZ (0 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 12 MHz reference clock */
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# define SFR_UTMICKTRIM_FREQ_16MHZ (1 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 16 MHz reference clock */
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# define SFR_UTMICKTRIM_FREQ_24MHZ (2 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 24 MHz reference clock */
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#ifndef ATSAMA5D2
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#ifdef ATSAMA5D3
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# define SFR_UTMICKTRIM_FREQ_48MHZ (3 << SFR_UTMICKTRIM_FREQ_SHIFT) /* 48 MHz reference clock */
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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# define SFR_UTMICKTRIM_VBG_SHIFT (16) /* Bits 16-19: UTMI Band Gap Voltage Trimming */
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# define SFR_UTMICKTRIM_VBG_MASK (15 << SFR_UTMICKTRIM_VBG_SHIFT)
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# define SFR_UTMICKTRIM_VBG(n) ((uint32_t)(n) << SFR_UTMICKTRIM_VBG_SHIFT)
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* UTMI High Speed Trimming Register */
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# define SFR_UTMIHSTRIM_SQUELCH_SHIFT (0) /* Bits 0-2: UTMI HS SQUELCH Voltage Trimming */
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@ -179,9 +178,7 @@
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# define SFR_UTMIHSTRIM_SLOPE2_SHIFT (16) /* Bits 16-18: UTMI HS PORT2 Transceiver Slope Trimming */
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# define SFR_UTMIHSTRIM_SLOPE2_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT)
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# define SFR_UTMIHSTRIM_SLOPE2(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT)
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* UTMI Full Speed Trimming Register */
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# define SFR_UTMIFSTRIM_RISE_SHIFT (0) /* Bits 0-2: FS Transceiver Output Rising Slope Trimming */
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@ -199,16 +196,15 @@
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# define SFR_UTMIFSTRIM_ZP_SHIFT (20) /* Bits 20-22: FS Transceiver PMOS Impedance Trimming */
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# define SFR_UTMIFSTRIM_ZP_MASK (7 << SFR_UTMIHSTRIM_SLOPE2_SHIFT)
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# define SFR_UTMIFSTRIM_ZP(n) ((uint32_t)(n) << SFR_UTMIHSTRIM_SLOPE2_SHIFT)
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#endif
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#if defined(ATSAMA5D2) || defined(ATSAMA5D4)
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/* UTMI DP/DM Pin Swapping Register */
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# define SFR_UTMISWAP_PORT(n) (1 << (n)) /* Bit n: PORT n DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT0 (1 << 0) /* Bit 0: PORT 0 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT1 (1 << 1) /* Bit 1: PORT 1 DP/DM Pin Swapping */
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# define SFR_UTMISWAP_PORT2 (1 << 2) /* Bit 2: PORT 2 DP/DM Pin Swapping */
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#endif
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#endif /* if defined(ATSAMA5D2) || defined(ATSAMA5D3) */
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/* EBI Configuration Register */
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@ -432,6 +432,7 @@ static inline void sam_usbclockconfig(void)
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
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* PMC_PCER register.
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* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
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* Set CLKTRIM register if required.
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* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
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* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
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* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
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@ -448,6 +449,28 @@ static inline void sam_usbclockconfig(void)
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/* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register. */
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#if defined(ATSAMA5D2) || defined(ATSAMA5D3)
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/* get UTMI timing register */
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regval = getreg32(SAM_SFR_VBASE + SAM_SFR_UTMICKTRIM_OFFSET);
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regval &= ~SFR_UTMICKTRIM_FREQ_MASK;
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#if BOARD_MAINOSC_FREQUENCY == (12000000)
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regval |= SFR_UTMICKTRIM_FREQ_12MHZ;
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#elif BOARD_MAINOSC_FREQUENCY == (16000000)
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regval |= SFR_UTMICKTRIM_FREQ_16MHZ;
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#elif BOARD_MAINOSC_FREQUENCY == (24000000)
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regval |= SFR_UTMICKTRIM_FREQ_24MHZ;
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#elif (BOARD_MAINOSC_FREQUENCY == (48000000)) && defined(ATSAMA5D3)
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regval |= SFR_UTMICKTRIM_FREQ_48MHZ;
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#else
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# error Board oscillator frequency not compatible with use of UPLL
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#endif
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#endif
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putreg32(regval, (SAM_SFR_VBASE + SAM_SFR_UTMICKTRIM_OFFSET));
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regval = PMC_CKGR_UCKR_UPLLCOUNT(BOARD_CKGR_UCKR_UPLLCOUNT);
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putreg32(regval, SAM_PMC_CKGR_UCKR);
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