SAML21: Add DMA descriptor management logic
This commit is contained in:
Gregory Nutt
parent
41fa4c7dbe
commit
6b8ae61dad
@ -84,6 +84,7 @@
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# define SAMDL_FLASH_SIZE (16*1024) /* 16KB */
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# define SAMDL_SRAM0_SIZE (2*1024) /* 2KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E15)
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@ -96,6 +97,7 @@
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E16)
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@ -108,6 +110,7 @@
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E17)
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@ -120,6 +123,7 @@
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20E18)
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@ -132,6 +136,7 @@
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G14)
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@ -144,6 +149,7 @@
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# define SAMDL_FLASH_SIZE (16*1024) /* 16KB */
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# define SAMDL_SRAM0_SIZE (2*1024) /* 2KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G15)
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@ -156,6 +162,7 @@
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G16)
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@ -168,6 +175,7 @@
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G17)
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@ -180,6 +188,7 @@
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20G18)
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@ -192,6 +201,7 @@
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J14)
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@ -204,6 +214,7 @@
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# define SAMDL_FLASH_SIZE (16*1024) /* 16KB */
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# define SAMDL_SRAM0_SIZE (2*1024) /* 2KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J15)
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@ -216,6 +227,7 @@
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J16)
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@ -228,6 +240,7 @@
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J17)
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@ -240,6 +253,7 @@
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#elif defined(CONFIG_ARCH_CHIP_SAMD20J18)
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@ -252,6 +266,7 @@
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (0*1024) /* None */
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#else
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@ -383,6 +398,7 @@
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# define SAMDL_FLASH_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASHRWW_SIZE (1*1024) /* 1KB */
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# define SAMDL_SRAM0_SIZE (4*1024) /* 4KB */
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# define SAMDL_LPRAM_SIZE (2*1024) /* 2KB */
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/* TCC waveform outputs */
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@ -400,6 +416,7 @@
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (4*1024) /* 4KB */
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/* TCC waveform outputs */
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@ -417,6 +434,7 @@
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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@ -434,6 +452,7 @@
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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@ -451,6 +470,7 @@
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (4*1024) /* 4KB */
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/* TCC waveform outputs */
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@ -465,9 +485,10 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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@ -482,9 +503,10 @@
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/* Internal memory */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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@ -502,6 +524,7 @@
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# define SAMDL_FLASH_SIZE (64*1024) /* 64KB */
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# define SAMDL_FLASHRWW_SIZE (2*1024) /* 2KB */
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# define SAMDL_SRAM0_SIZE (8*1024) /* 8KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 4KB */
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/* TCC waveform outputs */
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@ -519,6 +542,7 @@
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# define SAMDL_FLASH_SIZE (128*1024) /* 128KB */
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# define SAMDL_FLASHRWW_SIZE (4*1024) /* 4KB */
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# define SAMDL_SRAM0_SIZE (16*1024) /* 16KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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@ -536,6 +560,7 @@
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# define SAMDL_FLASH_SIZE (256*1024) /* 256KB */
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# define SAMDL_FLASHRWW_SIZE (8*1024) /* 8KB */
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# define SAMDL_SRAM0_SIZE (32*1024) /* 32KB */
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# define SAMDL_LPRAM_SIZE (8*1024) /* 8KB */
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/* TCC waveform outputs */
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@ -1384,7 +1384,7 @@ void weak_function up_dmainitialize(void)
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/* Initialize semaphores */
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sem_init(&g_chsem, 0, 1);
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sem_init(&g_dsem, 0, SAM34_NDMACHAN);
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sem_init(&g_dsem, 0, CONFIG_SAM34_NLLDESC);
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}
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/****************************************************************************
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@ -241,6 +241,7 @@ config ARCH_FAMILY_SAMD20J
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config ARCH_FAMILY_SAML21
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bool
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default n
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selest SAMDL_HAVE_DMAC
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config ARCH_FAMILY_SAML21E
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bool
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@ -261,6 +262,12 @@ config ARCH_FAMILY_SAML21J
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select SAMDL_HAVE_TC3
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select SAMDL_HAVE_TC5
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menu "SAMD/L Peripheral Support"
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config SAMDL_HAVE_DMAC
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bool
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default n
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config SAMDL_HAVE_SERCOM4
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bool
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default n
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@ -289,8 +296,6 @@ config SAMDL_HAVE_TC7
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bool
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default n
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menu "SAMD/L Peripheral Support"
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config SAMDL_AC
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bool "Analog Comparator"
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default n
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@ -307,7 +312,7 @@ config SAMDL_DMAC
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bool "DMA Controller"
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default n
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select ARCH_DMA
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depends on EXPERIMENTAL
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depends on SAMDL_HAVE_DMAC && EXPERIMENTAL
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config SAMDL_EVSYS
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bool "Event System"
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@ -414,6 +419,11 @@ config SAMDL_SERCOM0_ISUSART
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endchoice
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config SAMDL_DMAC_NDESC
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int "Number of DMA Descriptors"
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default 64
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depends on SAMDL_DMAC
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choice
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prompt "SERCOM1 mode"
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default SAMDL_SERCOM1_ISUSART
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@ -365,6 +365,16 @@ trigger */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/* DMA descriptor */
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struct dma_desc_s
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{
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uint16_t btctrl; /* Block Transfer Control Register */
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uint16_t btcnt; /* Block Transfer Count Register */
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uint32_t srcaddr; /* Block Transfer Source Address Register */
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uint32_t dstaddr; /* Block Transfer Destination Address Register */
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uint32_t descaddr; /* Next Address Descriptor Register */
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};
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/********************************************************************************************
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* Public Data
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@ -74,6 +74,12 @@
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# warning "SAM3/4 DMA enabled but CONFIG_ARCH_DMA disabled"
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#endif
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/* Number of DMA descriptors in LPRAM */
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#ifndef CONFIG_SAMDL_DMAC_NDESC
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# define CONFIG_SAMDL_DMAC_NDESC 64
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -82,25 +88,56 @@
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struct sam_dmach_s
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{
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uint8_t dc_chan; /* DMA channel number (0-6) */
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bool dc_inuse; /* TRUE: The DMA channel is in use */
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uint32_t dc_flags; /* DMA channel flags */
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dma_callback_t dc_callback; /* Callback invoked when the DMA completes */
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void *dc_arg; /* Argument passed to callback function */
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uint8_t dc_chan; /* DMA channel number (0-6) */
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bool dc_inuse; /* TRUE: The DMA channel is in use */
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uint32_t dc_flags; /* DMA channel flags */
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dma_callback_t dc_callback; /* Callback invoked when the DMA completes */
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void *dc_arg; /* Argument passed to callback function */
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struct dma_desc_s *llhead; /* DMA link list head */
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struct dma_desc_s *lltail; /* DMA link list head */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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static void sam_takechsem(void);
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static inline void sam_givechsem(void);
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static void sam_takedsem(void);
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static inline void sam_givedsem(void);
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static void sam_dmaterminate(struct sam_dmach_s *dmach, int result);
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static int sam_dmainterrupt(int irq, void *context);
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static struct dma_desc_s *
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sam_allocdesc(struct sam_dmach_s *dmach,
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struct dma_desc_s *prev, uint16_t btctrl, uint16_t btcnt,
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uint32_t srcaddr,uint32_t dstaddr);
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static void sam_freelinklist(struct sam_dmach_s *dmach);
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static size_t sam_maxtransfer(struct sam_dmach_s *dmach);
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static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
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uint32_t maddr, size_t nbytes);
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static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
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uint32_t maddr, size_t nbytes);
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static int sam_single(struct sam_dmach_s *dmach);
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static int sam_multiple(struct sam_dmach_s *dmach);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* These semaphores protect the DMA channel tables */
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/* These semaphores protect the DMA channel and descriptor tables */
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static sem_t g_chsem;
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static sem_t g_dsem;
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/* This array describes the state of each DMA channel */
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static struct sam_dmach_s g_dmach[SAMDL_NDMACHAN];
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/* DMA descriptors positioned in LPRAM */
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static struct dma_desc_s g_dma_desc[CONFIG_SAMDL_DMAC_NDESC]
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__attribute__ ((section(".lpram"),aligned(16)));
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -132,6 +169,33 @@ static inline void sam_givechsem(void)
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(void)sem_post(&g_chsem);
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}
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/****************************************************************************
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* Name: sam_takedsem() and sam_givedsem()
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*
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* Description:
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* Used to wait for availability of descriptors in the descriptor table.
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*
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****************************************************************************/
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static void sam_takedsem(void)
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{
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/* Take the semaphore (perhaps waiting) */
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while (sem_wait(&g_dsem) != 0)
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{
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/* The only case that an error should occur here is if the wait was
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* awakened by a signal.
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*/
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ASSERT(errno == EINTR);
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}
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}
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static inline void sam_givedsem(void)
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{
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(void)sem_post(&g_dsem);
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}
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/****************************************************************************
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* Name: sam_dmaterminate
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*
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@ -148,8 +212,9 @@ static void sam_dmaterminate(struct sam_dmach_s *dmach, int result)
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/* Disable the channel */
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#warning Missing logic
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/* Free the resources */
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#warning Missing logic
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/* Free the linklist */
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sam_freelinklist(dmach);
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/* Perform the DMA complete callback */
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@ -246,6 +311,141 @@ static size_t sam_addrincr(struct sam_dmach_s *dmach)
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}
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#endif
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/****************************************************************************
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* Name: sam_allocdesc
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*
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* Description:
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* Allocate and add one descriptor to the DMA channel's link list.
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*
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* NOTE: link list entries are freed by the DMA interrupt handler. However,
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* since the setting/clearing of the 'in use' indication is atomic, no
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* special actions need be performed. It would be a good thing to add logic
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* to handle the case where all of the entries are exhausted and we could
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* wait for some to be freed by the interrupt handler.
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*
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****************************************************************************/
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static struct dma_desc_s *
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sam_allocdesc(struct sam_dmach_s *dmach, struct dma_desc_s *prev,
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uint16_t btctrl, uint16_t btcnt, uint32_t srcaddr,
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uint32_t dstaddr)
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{
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struct dma_desc_s *desc = NULL;
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int i;
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/* Sanity check -- src == 0 is the indication that the link is unused.
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* Obviously setting it to zero would break that usage.
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*/
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#ifdef CONFIG_DEBUG
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if (src != 0)
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#endif
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{
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/* Table a descriptor table semaphore count. When we get one, then there
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* is at least one free descriptor in the table and it is ours.
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*/
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sam_takedsem();
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/* Examine each link list entry to find an available one -- i.e., one
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* with src == 0. That src field is set to zero by the DMA transfer
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* complete interrupt handler. The following should be safe because
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* that is an atomic operation.
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*/
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sam_takechsem();
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for (i = 0; i < CONFIG_SAMDL_DMAC_NDESC; i++)
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{
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if (g_dma_desc[i].srcaddr == 0)
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{
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/* We have it. Initialize the new link list entry */
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desc = &g_dma_desc[i];
|
||||
desc->btctrl = btctrl; /* Block Transfer Control Register */
|
||||
desc->btcnt = btcnt; /* Block Transfer Count Register */
|
||||
desc->srcaddr = srcaddr; /* Block Transfer Source Address Register */
|
||||
desc->dstaddr = dstaddr; /* Block Transfer Destination Address Register */
|
||||
desc->descaddr = 0; /* Next Address Descriptor Register */
|
||||
|
||||
/* And then hook it at the tail of the link list */
|
||||
|
||||
if (!prev)
|
||||
{
|
||||
/* There is no previous link. This is the new head of
|
||||
* the list
|
||||
*/
|
||||
|
||||
DEBUGASSERT(dmach->llhead == NULL && dmach->lltail == NULL);
|
||||
dmach->llhead = desc;
|
||||
}
|
||||
else
|
||||
{
|
||||
DEBUGASSERT(dmach->llhead != NULL && dmach->lltail == prev);
|
||||
|
||||
/* When the second link is added to the list, that is the
|
||||
* cue that we are going to do the link list transfer.
|
||||
*/
|
||||
#warning Missing logic
|
||||
|
||||
/* Link the previous tail to the new tail */
|
||||
|
||||
prev->descaddr = (uint32_t)desc;
|
||||
}
|
||||
|
||||
/* In any event, this is the new tail of the list. */
|
||||
#warning Missing logic
|
||||
|
||||
dmach->lltail = desc;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Because we hold a count from the counting semaphore, the above
|
||||
* search loop should always be successful.
|
||||
*/
|
||||
|
||||
sam_givechsem();
|
||||
DEBUGASSERT(desc != NULL);
|
||||
}
|
||||
|
||||
return desc;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_freelinklist
|
||||
*
|
||||
* Description:
|
||||
* Free all descriptors in the DMA channel's link list.
|
||||
*
|
||||
* NOTE: Called from the DMA interrupt handler.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void sam_freelinklist(struct sam_dmach_s *dmach)
|
||||
{
|
||||
struct dma_desc_s *desc;
|
||||
struct dma_desc_s *next;
|
||||
|
||||
/* Get the head of the link list and detach the link list from the DMA
|
||||
* channel
|
||||
*/
|
||||
|
||||
desc = dmach->llhead;
|
||||
dmach->llhead = NULL;
|
||||
dmach->lltail = NULL;
|
||||
|
||||
/* Reset each descriptor in the link list (thereby freeing them) */
|
||||
|
||||
while (desc != NULL)
|
||||
{
|
||||
next = (struct dma_desc_s *)desc->descaddr;
|
||||
DEBUGASSERT(desc->src != 0);
|
||||
memset(desc, 0, sizeof(struct dma_desc_s));
|
||||
sam_givedsem();
|
||||
desc = next;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_maxtransfer
|
||||
*
|
||||
@ -273,7 +473,18 @@ static size_t sam_maxtransfer(struct sam_dmach_s *dmach)
|
||||
static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
|
||||
uint32_t maddr, size_t nbytes)
|
||||
{
|
||||
uint16_t btctrl;
|
||||
uint16_t btcnt;
|
||||
|
||||
#warning Missing logic
|
||||
|
||||
/* Add the new link list entry */
|
||||
|
||||
if (!sam_allocdesc(dmach, dmach->lltail, btctrl, btcnt, maddr, paddr))
|
||||
{
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -290,7 +501,18 @@ static int sam_txbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
|
||||
static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
|
||||
uint32_t maddr, size_t nbytes)
|
||||
{
|
||||
uint16_t btctrl;
|
||||
uint16_t btcnt;
|
||||
|
||||
#warning Missing logic
|
||||
|
||||
/* Add the new link list entry */
|
||||
|
||||
if (!sam_allocdesc(dmach, dmach->lltail, btctrl, btcnt, maddr, paddr))
|
||||
{
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -302,8 +524,10 @@ static int sam_rxbuffer(struct sam_dmach_s *dmach, uint32_t paddr,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_single(struct sam_dmach_s *dmach)
|
||||
static int sam_single(struct sam_dmach_s *dmach)
|
||||
{
|
||||
struct dma_desc_s *llhead = dmach->llhead;
|
||||
|
||||
/* Clear any pending interrupts from any previous DMAC transfer.
|
||||
*
|
||||
* REVISIT: If DMAC interrupts are disabled at the NVIKC, then reading the
|
||||
@ -313,6 +537,7 @@ static inline int sam_single(struct sam_dmach_s *dmach)
|
||||
|
||||
/* Set up the DMA */
|
||||
#warning Missing logic
|
||||
DEBUGASSERT(llhead != NULL && llhead->src != 0);
|
||||
|
||||
/* Enable the channel */
|
||||
#warning Missing logic
|
||||
@ -331,8 +556,10 @@ static inline int sam_single(struct sam_dmach_s *dmach)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int sam_multiple(struct sam_dmach_s *dmach)
|
||||
static int sam_multiple(struct sam_dmach_s *dmach)
|
||||
{
|
||||
struct dma_desc_s *llhead = dmach->llhead;
|
||||
|
||||
/* Clear any pending interrupts from any previous DMAC transfer.
|
||||
*
|
||||
* REVISIT: If DMAC interrupts are disabled at the NVIKC, then reading the
|
||||
@ -342,6 +569,8 @@ static inline int sam_multiple(struct sam_dmach_s *dmach)
|
||||
|
||||
/* Set up the initial DMA */
|
||||
#warning Missing logic
|
||||
DEBUGASSERT(llhead != NULL && llhead->src != 0);
|
||||
|
||||
|
||||
/* Enable the channel */
|
||||
#warning Missing logic
|
||||
@ -375,6 +604,7 @@ void weak_function up_dmainitialize(void)
|
||||
/* Initialize global semaphores */
|
||||
|
||||
sem_init(&g_chsem, 0, 1);
|
||||
sem_init(&g_dsem, 0, CONFIG_SAMDL_DMAC_NDESC);
|
||||
|
||||
/* Initialized the DMA channel table */
|
||||
|
||||
@ -676,9 +906,11 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
dmavdbg("dmach: %p callback: %p arg: %p\n", dmach, callback, arg);
|
||||
DEBUGASSERT(dmach != NULL);
|
||||
|
||||
/* Verify that the DMA has been setup */
|
||||
#warning Missing logic
|
||||
/* Verify that the DMA has been setup (i.e., at least one entry in the
|
||||
* link list).
|
||||
*/
|
||||
|
||||
if (dmach->llhead)
|
||||
{
|
||||
/* Save the callback info. This will be invoked when the DMA completes */
|
||||
|
||||
@ -686,9 +918,8 @@ int sam_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
dmach->dc_arg = arg;
|
||||
|
||||
/* Is this a single block transfer? Or a multiple block transfer? */
|
||||
#warning Missing logic
|
||||
|
||||
if (true)
|
||||
if (dmach->llhead == dmach->lltail)
|
||||
{
|
||||
ret = sam_single(dmach);
|
||||
}
|
||||
@ -766,16 +997,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
|
||||
regs->chctrlb = getreg32(SAM_DMAC_CHCTRLB); /* Channel Control B Register */
|
||||
regs->chintflag = getreg8(SAM_DMAC_CHINTFLAG); /* Channel Interrupt Flag Status and Clear Register */
|
||||
regs->chstatus = getreg8(SAM_DMAC_CHSTATUS); /* Channel Status Register */
|
||||
|
||||
/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
|
||||
#warning How do we get the base address
|
||||
|
||||
regs->btctrl = getreg16(base + SAM_LPSRAM_BTCTRL_OFFSET);
|
||||
regs->btcnt = getreg16(base + SAM_LPSRAM_BTCNT_OFFSET);
|
||||
regs->srcaddr = getreg32(base + SAM_LPSRAM_SRCADDR_OFFSET);
|
||||
regs->dstaddr = getreg32(base + SAM_LPSRAM_DSTADDR_OFFSET);
|
||||
regs->descaddr = getreg32(base + SAM_LPSRAM_DESCADDR_OFFSET);
|
||||
irqrestore(flags);
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_DMA */
|
||||
|
||||
@ -812,14 +1033,6 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
|
||||
regs->chid, regs->chctrla, regs->chctrlb, regs->chintflag,
|
||||
dmadbg(" CHSTATUS: %02x\n",
|
||||
regs->chstatus);
|
||||
|
||||
/* LPSRAM Registers Relative to BASEADDR or WRBADDR */
|
||||
#warning How do we get the base address
|
||||
|
||||
dmadbg(" LPSRAM Values:\n");
|
||||
dmadbg(" BTCTRL: %04x BTCNT: %04x SRCADDR: %08x DSTADDR: %08x\n",
|
||||
regs->btctrl, regs->btcnt, regs->srcaddr, regs->dstaddr);
|
||||
dmadbg(" DESCADDR: %08x\n", regs->descaddr);
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_DMA */
|
||||
#endif /* CONFIG_SAMDL_DMAC */
|
||||
|
||||
@ -34,13 +34,15 @@
|
||||
****************************************************************************/
|
||||
|
||||
/* The ATSAML21J18A has 256KB of FLASH beginning at address 0x0000:0000 and
|
||||
* 32KB of SRAM beginning at address 0x2000:0000
|
||||
* 32KB of SRAM beginning at address 0x2000:0000. There is also 8KB low-
|
||||
* power SRAM at 0x30000000 that may be used by the DMAC.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x00000000, LENGTH = 256K
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
|
||||
lpram (rw) : ORIGIN = 0x30000000, LENGTH = 8K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
@ -107,6 +109,10 @@ SECTIONS
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
.lpram : {
|
||||
*(.lpram)
|
||||
} > lpram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user