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clear spi int before the transfer starts

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In spi_irq handler the data is written into txfifo and transfer
is started before the TXDONE interrupt is cleared. If the bus/memory
access is in some cases delayed, the spi transfer may have been
finished already before the interrupt register is cleaned for the
transfer. This leads the early arrived interrupt to be just removed
and never handled, which would cause a timeout error.
This patch moves the clearing of the interrupt to the place before
the tx is started, so the interrupt is not missed in above cases.
This commit is contained in:
Jari Nippula 2023-02-24 21:33:46 +02:00 committed by Xiang Xiao
parent ab5d6d759a
commit 6ba906691a
1 changed files with 1 additions and 2 deletions
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3
arch/risc-v/src/mpfs/mpfs_spi.c
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@ -1278,6 +1278,7 @@ static int mpfs_spi_irq(int cpuint, void *context, void *arg)
if (status & MPFS_SPI_TXDONEMSKINT)
{
remaining = priv->txwords - priv->tx_pos;
putreg32(MPFS_SPI_TXDONECLR, MPFS_SPI_INT_CLEAR);
if (remaining == 0)
{
@ -1300,8 +1301,6 @@ static int mpfs_spi_irq(int cpuint, void *context, void *arg)
mpfs_spi_load_tx_fifo(priv, priv->txbuf, priv->fifolevel);
}
}
putreg32(MPFS_SPI_TXDONECLR, MPFS_SPI_INT_CLEAR);
}
if (status & MPFS_SPI_RXCHOVRFMSKINT)