diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S index 97553a0d44..cc08054094 100644 --- a/arch/risc-v/src/common/riscv_exception_common.S +++ b/arch/risc-v/src/common/riscv_exception_common.S @@ -72,6 +72,7 @@ .section EXCEPTION_SECTION .global exception_common + .global return_from_exception .align 8 exception_common: @@ -142,6 +143,8 @@ exception_common: addi sp, sp, XCPTCONTEXT_SIZE #endif +return_from_exception: + /* If context switch is needed, return a new sp */ mv sp, a0 diff --git a/arch/risc-v/src/common/supervisor/riscv_syscall.S b/arch/risc-v/src/common/supervisor/riscv_syscall.S index 3e4515fea7..bda64d3de2 100644 --- a/arch/risc-v/src/common/supervisor/riscv_syscall.S +++ b/arch/risc-v/src/common/supervisor/riscv_syscall.S @@ -119,52 +119,8 @@ sys_call6: /* Run the handler */ - jal x1, riscv_perform_syscall - - /* Restore (potentially new) context */ - - mv sp, a0 /* use sp, as a0 gets wiped */ - - REGLOAD s0, REG_EPC(sp) /* restore epc */ - csrw CSR_EPC, s0 - - /* Restore status register, but don't enable interrupts yet */ - - REGLOAD s0, REG_INT_CTX(sp) /* restore status */ - li s1, STATUS_IE /* move IE -> PIE */ - and s1, s0, s1 /* if (STATUS & IE) */ - beqz s1, 1f - li s1, ~STATUS_IE /* clear IE */ - and s0, s0, s1 - li s1, STATUS_PIE /* set PIE */ - or s0, s0, s1 - -1: - csrw CSR_STATUS, s0 - -#ifdef CONFIG_ARCH_KERNEL_STACK - /* Returning to userspace ? */ - - li s1, STATUS_PPP - and s0, s0, s1 - bnez s0, 1f - - /* Set the next task's kernel stack to the scratch area */ - - jal x1, riscv_current_ksp - csrr s0, CSR_SCRATCH - REGSTORE a0, RISCV_PERCPU_KSP(s0) - -1: -#endif - - load_ctx sp - - REGLOAD sp, REG_SP(sp) /* restore original sp */ - - /* return from exception, which updates the status register */ - - ERET + la x1, return_from_exception + tail riscv_perform_syscall .size sys_call0, .-sys_call0 .size sys_call1, .-sys_call1