bcmf: enable DMA for SDIO transfers
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1c97025484
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6bb2db8c15
@ -2721,7 +2721,17 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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/* Then set up the SDIO data path */
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dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
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#ifdef CONFIG_SDIO_BLOCKSETUP
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if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
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{
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dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
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}
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else
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#endif
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{
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dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
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}
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stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize | SDIO_DCTRL_DTDIR);
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/* Configure the RX DMA */
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@ -2790,7 +2800,17 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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/* Then set up the SDIO data path */
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dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
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#ifdef CONFIG_SDIO_BLOCKSETUP
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if (priv->block_size != STM32_SDIO_USE_DEFAULT_BLOCKSIZE)
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{
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dblocksize = priv->block_size << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
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}
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else
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#endif
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{
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dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT;
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}
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stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize);
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/* Configure the TX DMA */
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@ -237,6 +237,17 @@
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# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA Channl/Stream Selections *****************************************************/
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/* Stream selections are arbitrary for now but might become important in the future
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* if we set aside more DMA channels/streams.
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*
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* SDIO DMA
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* DMAMAP_SDIO_1 = Channel 4, Stream 3
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* DMAMAP_SDIO_2 = Channel 4, Stream 6
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*/
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#define DMAMAP_SDIO DMAMAP_SDIO_1
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/************************************************************************************
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* Public Data
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************************************************************************************/
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@ -16,7 +16,7 @@ CONFIG_HOST_LINUX=y
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#
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# Build Configuration
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#
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# CONFIG_APPS_DIR="../apps"
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CONFIG_APPS_DIR="../apps"
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CONFIG_BUILD_FLAT=y
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# CONFIG_BUILD_2PASS is not set
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@ -75,6 +75,7 @@ CONFIG_DEBUG_WIRELESS_INFO=y
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#
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# OS Function Debug Options
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#
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# CONFIG_DEBUG_DMA is not set
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# CONFIG_DEBUG_IRQ is not set
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#
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@ -449,7 +450,7 @@ CONFIG_STM32_HAVE_SPI3=y
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# CONFIG_STM32_CAN2 is not set
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# CONFIG_STM32_CRC is not set
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# CONFIG_STM32_DMA1 is not set
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# CONFIG_STM32_DMA2 is not set
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CONFIG_STM32_DMA2=y
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# CONFIG_STM32_DAC1 is not set
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# CONFIG_STM32_DAC2 is not set
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# CONFIG_STM32_I2C1 is not set
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@ -499,6 +500,7 @@ CONFIG_STM32_JTAG_SW_ENABLE=y
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# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set
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# CONFIG_STM32_FORCEPOWER is not set
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# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set
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# CONFIG_STM32_DMACAPABLE is not set
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#
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# Timer Configuration
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@ -529,6 +531,7 @@ CONFIG_STM32_SERIALDRIVER=y
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CONFIG_STM32_USART1_SERIALDRIVER=y
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# CONFIG_STM32_USART1_1WIREDRIVER is not set
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# CONFIG_USART1_RS485 is not set
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# CONFIG_USART1_RXDMA is not set
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#
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# Serial Driver Configuration
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@ -541,6 +544,7 @@ CONFIG_STM32_USART1_SERIALDRIVER=y
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#
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# SDIO Configuration
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#
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CONFIG_STM32_SDIO_DMA=y
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CONFIG_STM32_SDIO_DMAPRIO=0x00010000
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# CONFIG_STM32_SDIO_WIDTH_D1_ONLY is not set
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# CONFIG_STM32_HAVE_RTC_COUNTER is not set
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@ -567,7 +571,7 @@ CONFIG_STM32_SDIO_DMAPRIO=0x00010000
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#
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# CONFIG_ARCH_NOINTC is not set
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# CONFIG_ARCH_VECNOTIRQ is not set
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# CONFIG_ARCH_DMA is not set
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CONFIG_ARCH_DMA=y
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CONFIG_ARCH_HAVE_IRQPRIO=y
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# CONFIG_ARCH_L2CACHE is not set
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# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set
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@ -853,7 +857,7 @@ CONFIG_MMCSD_NSLOTS=1
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# CONFIG_MMCSD_MMCSUPPORT is not set
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# CONFIG_MMCSD_HAVECARDDETECT is not set
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CONFIG_ARCH_HAVE_SDIO=y
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# CONFIG_SDIO_DMA is not set
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CONFIG_SDIO_DMA=y
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CONFIG_ARCH_HAVE_SDIOWAIT_WRCOMPLETE=y
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CONFIG_MMCSD_SDIO=y
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CONFIG_SDIO_PREFLIGHT=y
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@ -1280,6 +1284,10 @@ CONFIG_HAVE_CXXINITIALIZE=y
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# Application Configuration
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#
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#
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# NxWidgets/NxWM
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#
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#
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# Built-In Applications
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#
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@ -1514,10 +1522,6 @@ CONFIG_NSH_MAX_ROUNDTRIP=20
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# CONFIG_NSH_LOGIN is not set
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# CONFIG_NSH_CONSOLE_LOGIN is not set
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#
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# NxWidgets/NxWM
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#
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#
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# Platform-specific Support
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#
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@ -78,6 +78,8 @@ int sdio_io_rw_direct(FAR struct sdio_dev_s *dev, bool write,
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/* Setup CMD52 argument */
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arg.value = 0;
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if (write)
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{
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arg.cmd52.write_data = inb;
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@ -135,6 +137,7 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
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/* Setup CMD53 argument */
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arg.value = 0;
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arg.cmd53.register_address = address & 0x1ffff;
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arg.cmd53.op_code = inc_addr;
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arg.cmd53.function_number = function & 7;
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@ -169,13 +172,13 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
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sdio_sendcmdpoll(dev, SDIO_ACMD53, (uint32_t)arg.value);
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ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t*)&resp);
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SDIO_SENDSETUP(dev, buf, blocklen * nblocks);
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SDIO_DMASENDSETUP(dev, buf, blocklen * nblocks);
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wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
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}
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else
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{
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// wlinfo("prep read %d\n", blocklen * nblocks);
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SDIO_RECVSETUP(dev, buf, blocklen * nblocks);
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SDIO_DMARECVSETUP(dev, buf, blocklen * nblocks);
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SDIO_SENDCMD(dev, SDIO_ACMD53, (uint32_t)arg.value);
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wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
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